Skip to content
View rpjayaraman's full-sized avatar
11 followers · 9 following
  • Samsung Semiconductor
  • India

Block or report rpjayaraman

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
rpjayaraman/README.md
  • 👋 Hi, I’m @rpjayaraman
  • 👀 I’m interested in Hardware
  • 🌱 I’m working as an ASIC DV Engineer
  • 📫 How to reach me jrp.postbox@gmail.com

Pinned Loading

  1. RTL2UVM RTL2UVM Public

    Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

    Python 6 1

  2. LLMxVLSI LLMxVLSI Public

    Generate, Simulate & Summarize Verilog Code with GenAI and Iverilog tool

    Python 5 1