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Within the scope of this project, we are going to design ALU and Instruction decoder blocks of a RISC-V processor by using the basic SystemVerilog language features.

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Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
Evrim_Arda_Kalafat_cv.pdf		Evrim_Arda_Kalafat_cv.pdf
Proje_Dosyasi.zip		Proje_Dosyasi.zip
Proje_Teslim_Dokumani.docx		Proje_Teslim_Dokumani.docx
Proje_Teslim_Dokumani.pdf		Proje_Teslim_Dokumani.pdf
README.md		README.md
Sunum.pdf		Sunum.pdf
alu.sv		alu.sv
instruction_decoder.sv		instruction_decoder.sv
tasarım.png		tasarım.png

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RISC-V_Project

Within the scope of this project, we are going to design ALU and Instruction decoder blocks of a RISC-V processor by using the basic SystemVerilog language features.

Turkish Presentation: https://youtu.be/S0RCmj7MAG0

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Within the scope of this project, we are going to design ALU and Instruction decoder blocks of a RISC-V processor by using the basic SystemVerilog language features.

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