Labs of USTC 2020 Spring Computer Organization and Design course
- ALU & sort
- Regfile & RAM & FIFO
- Single cycle CPU
- Multiple cycle CPU
- 5-stage pipeline CPU
- CPU & UART on ebaz4205 (testing video in report.md)
Rebuild projects from TCL(for example):
vivado -mode batch -source lab6.tcl -tclargs --project_name lab6