data_Zpn.txt

//for vX.Y  of P


// BPICK -> B CMIX
// CLZ32 -> B CLZ
// MAXW  -> B MAX
// MINW  -> B MIN
// PKBB16 -> B PACK
// PKTT16 -> B PACKU
// PKBB32 -> B PACK
// PKTT32 -> B PACKU
// so far instructions using OV flag unsupported
I	ADD8    ADD8	0100100----------000-----1110111	pdpiadd8	Zpn
I	ADD16   ADD16	0100000----------000-----1110111	pdpiadd16	Zpn
I	AVE     AVE	1110000----------000-----1110111	pdpiadd32	Zpn
I	BITREV  BITREV	1110011----------000-----1110111	pdpibit	Zpn
I	BITREVI BITREV	1110010----------000-----1110111	pdpibit	Zpn
I	CLRS8	CLRS8	101011100000-----000-----1110111	pdpibit	Zpn
//I	CLRS16	CLRS16	101011101000-----000-----1110111	pdpibit	Zpn
//I	CLRS32	CLRS32	101011111000-----000-----1110111	pdpibit	Zpn
I	CLO8	CLO8	101011100011-----000-----1110111	pdpibit	Zpn
//I	CLO16	CLO16	101011101011-----000-----1110111	pdpibit	Zpn
//I	CLO32	CLO32	101011111011-----000-----1110111	pdpibit	Zpn
I	CLZ8	CLZ8	101011100001-----000-----1110111	pdpibit	Zpn
//I	CLZ16	CLZ16	101011101001-----000-----1110111	pdpibit	Zpn
//I	CLZ32	CLZ32	101011111001-----000-----1110111	pdpibit	Zpn
I	CMPEQ8	CMPEQ8	0100111----------000-----1110111	pdpicmp	Zpn
I	CMPEQ16	CMPEQ16	0100110----------000-----1110111	pdpicmp	Zpn
I	PKxx16	PKxx16	00--111----------001-----1110111	pdpicpct Zpn
I	RADD8	RADD8	0000100----------000-----1110111	pdpiadd8	Zpn
I	RADD16	RADD16	0000000----------000-----1110111	pdpiadd16	Zpn
I	RADDW	RADDW	0010000----------001-----1110111	pdpiadd32	Zpn
I	RSUB8	RSUB8	0000101----------000-----1110111	pdpiadd8	Zpn
I	RSUB16	RSUB16	0000001----------000-----1110111	pdpiadd16	Zpn
I	RSUBW	RSUBW	0010001----------001-----1110111	pdpiadd32	Zpn
//I	CRAS16	CRAS16	0100010----------000-----1110111	pdpisubadd	Zpn
//I	CRSA16	CRSA16	0100011----------000-----1110111	pdpisubadd	Zpn
//I	RCRAS16	RCRAS16	0000010----------000-----1110111	pdpisubadd	Zpn
//I	RCRSA16	RCRSA16	0000011----------000-----1110111	pdpisubadd	Zpn
//I	RSTAS16	RCRAS16	1011010----------000-----1110111	pdpisubadd	Zpn
//I	RSTSA16	RCRSA16	1011011----------000-----1110111	pdpisubadd	Zpn
//I	STAS16	STAS16	1111010----------010-----1110111	pdpisubadd	Zpn
//I	STSA16	STSA16	1111011----------010-----1110111	pdpisubadd	Zpn
I	SCMPLE8	SCMPLE8	  0001111----------000-----1110111	pdpicmp	Zpn
I	SCMPLE16 SCMPLE16 0001110----------000-----1110111	pdpicmp	Zpn
I	SCMPLT8	SCMPLT8	  0000111----------000-----1110111	pdpicmp	Zpn
I	SCMPLT16 SCMPLT16 0000110----------000-----1110111	pdpicmp	Zpn
I	SLL8	 SLL8	0101110----------000-----1110111	pdpishift	Zpn
I	SLLI8	 SLL8	011111000--------000-----1110111	pdpishift	Zpn
I	SRL8	 SRL8	0101101----------000-----1110111	pdpishift	Zpn
I	SRLI8	 SRL8	011110100--------000-----1110111	pdpishift	Zpn
I	SRA8	 SRA8	0101100----------000-----1110111	pdpishift	Zpn
I	SRAI8	 SRA8	011110000--------000-----1110111	pdpishift	Zpn
I	SLL16	 SLL16	0101010----------000-----1110111	pdpishift	Zpn
I	SLLI16	 SLL16	01110100---------000-----1110111	pdpishift	Zpn
I	SRL16	 SRL16	0101001----------000-----1110111	pdpishift	Zpn
I	SRLI16	 SRL16	01110010---------000-----1110111	pdpishift	Zpn
I	SRA16	 SRA16	0101000----------000-----1110111	pdpishift	Zpn
I	SRAI16	 SRA16	01110000---------000-----1110111	pdpishift	Zpn
I	SMAX8	 SMAX8	1000101----------000-----1110111	pdpicmp	Zpn
I	SMAX16	 SMAX16	1000001----------000-----1110111	pdpicmp	Zpn
I	SMIN8	 SMIN8	1000100----------000-----1110111	pdpicmp	Zpn
I	SMIN16	 SMIN16	1000000----------000-----1110111	pdpicmp	Zpn
I	SUB8     SUB8	0100101----------000-----1110111	pdpiadd8	Zpn
I	SUB16    SUB16	0100001----------000-----1110111	pdpiadd16	Zpn
I	SUNPKD810 SUNPKD8 101011001000-----000-----1110111	pdpicpct	Zpn
I	SUNPKD820 SUNPKD8 101011001001-----000-----1110111	pdpicpct	Zpn
I	SUNPKD830 SUNPKD8 101011001010-----000-----1110111	pdpicpct	Zpn
I	SUNPKD831 SUNPKD8 101011001011-----000-----1110111	pdpicpct	Zpn
I	SUNPKD832 SUNPKD8 101011010011-----000-----1110111	pdpicpct	Zpn
I	SWAP8	 SWAP8	101011011000-----000-----1110111	pdpibit	Zpn
I	SWAP16	 SWAP16 101011011001-----000-----1110111	pdpibit	Zpn
I	UCMPLE8	 UCMPLE8  0011111----------000-----1110111	pdpicmp	Zpn
I	UCMPLE16 UCMPLE16 0011110----------000-----1110111	pdpicmp	Zpn
I	UCMPLT8	 UCMPLT8  0010111----------000-----1110111	pdpicmp	Zpn
I	UCMPLT16 UCMPLT16 0010110----------000-----1110111	pdpicmp	Zpn
I	UMAX8	 UMAX8	1001101----------000-----1110111	pdpicmp	Zpn
I	UMAX16	 UMAX16	1001001----------000-----1110111	pdpicmp	Zpn
I	UMIN8	 UMIN8	1001100----------000-----1110111	pdpicmp	Zpn
I	UMIN16	 UMIN16	1001000----------000-----1110111	pdpicmp	Zpn
I	URADD8	URADD8	0010100----------000-----1110111	pdpiadd8	Zpn
I	URADD16	URADD16	0010000----------000-----1110111	pdpiadd16	Zpn
I	URADDW	URADDW	0011000----------001-----1110111	pdpiadd32	Zpn
I	URSUB8	URSUB8	0010101----------000-----1110111	pdpiadd8	Zpn
I	URSUB16	URSUB16	0010001----------000-----1110111	pdpiadd16	Zpn
I	URSUBW	URSUBW	0011001----------001-----1110111	pdpiadd32	Zpn
I	ZUNPKD810 ZUNPKD8 101011001100-----000-----1110111	pdpicpct	Zpn
I	ZUNPKD820 ZUNPKD8 101011001101-----000-----1110111	pdpicpct	Zpn
I	ZUNPKD830 ZUNPKD8 101011001110-----000-----1110111	pdpicpct	Zpn
I	ZUNPKD831 ZUNPKD8 101011001111-----000-----1110111	pdpicpct	Zpn
I	ZUNPKD832 ZUNPKD8 101011010111-----000-----1110111	pdpicpct	Zpn

// the following needs to read Rd, so need a patch to VexRiscv
//INSB need the I in the name to get the immediate from the tool
I	INSBI	INSBI	101011000--------000-----1110111	pdpibit	Zpn
//I	MADDR32	MADDR32	1100010----------001-----1110111	pdpimac	Zpn
//I	MSUBR32	MSUBR32	1100011----------001-----1110111	pdpimac	Zpn
// ternary
I	SMAQA   SMAQA	1100100----------000----01110111	pdpiumul8	Zpnslow
I	UMAQA   UMAQA	1100110----------000----01110111	pdpismul8	Zpnslow
// ternary + binary (bit 25)
I	PBSADx	PBSADx	111111-----------000-----1110111	pdpipsad	Zpn

// Saturating, currently doesn't set the CSR
I  KADD8	KADD8	0001100----------000-----1110111	pdpikadd8	Zpn
I  UKADD8	UKADD8	0011100----------000-----1110111	pdpikadd8	Zpn
I  KSUB8	KSUB8	0001101----------000-----1110111	pdpikadd8	Zpn
I  UKSUB8	UKSUB8	0011101----------000-----1110111	pdpikadd8	Zpn

// binary
S	ADD8	"fun_add8(input(SRC1), input(SRC2))"
S	ADD16	"fun_add16(input(SRC1), input(SRC2))"
S	AVE	"fun_ave(input(SRC1), input(SRC2))"
S	BITREV	"fun_bitrev(input(SRC1), input(SRC2))"
S	CMPEQ8	"fun_cmpeq8(input(SRC1), input(SRC2))"
S	CMPEQ16	"fun_cmpeq16(input(SRC1), input(SRC2))"
S	PKxx16  "fun_pkbbtt16(input(SRC1), input(SRC2), input(INSTRUCTION)(29).asUInt, input(INSTRUCTION)(28).asUInt)"
S	RADD8	"fun_radd8(input(SRC1), input(SRC2))"
S	RADD16	"fun_radd16(input(SRC1), input(SRC2))"
S	RADDW	"fun_radd32(input(SRC1), input(SRC2))"
S	RSUB8	"fun_rsub8(input(SRC1), input(SRC2))"
S	RSUB16	"fun_rsub16(input(SRC1), input(SRC2))"
S	RSUBW	"fun_rsub32(input(SRC1), input(SRC2))"
S	SCMPLE8	"fun_scmple8(input(SRC1), input(SRC2))"
S	SCMPLE16	"fun_scmple16(input(SRC1), input(SRC2))"
S	SCMPLT8	"fun_scmplt8(input(SRC1), input(SRC2))"
S	SCMPLT16	"fun_scmplt16(input(SRC1), input(SRC2))"
S	SLL8	"fun_sll8(input(SRC1), input(SRC2))"
S	SRL8	"fun_srl8(input(SRC1), input(SRC2))"
S	SRA8	"fun_sra8(input(SRC1), input(SRC2))"
S	SLL16	"fun_sll16(input(SRC1), input(SRC2))"
S	SRL16	"fun_srl16(input(SRC1), input(SRC2))"
S	SRA16	"fun_sra16(input(SRC1), input(SRC2))"
S	SMAX8	"fun_smax8(input(SRC1), input(SRC2))"
S	SMAX16	"fun_smax16(input(SRC1), input(SRC2))"
S	SMIN8	"fun_smin8(input(SRC1), input(SRC2))"
S	SMIN16	"fun_smin16(input(SRC1), input(SRC2))"
S	SUB8	"fun_sub8(input(SRC1), input(SRC2))"
S	SUB16	"fun_sub16(input(SRC1), input(SRC2))"
S	UCMPLE8	"fun_ucmple8(input(SRC1), input(SRC2))"
S	UCMPLE16	"fun_ucmple16(input(SRC1), input(SRC2))"
S	UCMPLT8	"fun_ucmplt8(input(SRC1), input(SRC2))"
S	UCMPLT16	"fun_ucmplt16(input(SRC1), input(SRC2))"
S	UMAX8	"fun_umax8(input(SRC1), input(SRC2))"
S	UMAX16	"fun_umax16(input(SRC1), input(SRC2))"
S	UMIN8	"fun_umin8(input(SRC1), input(SRC2))"
S	UMIN16	"fun_umin16(input(SRC1), input(SRC2))"
S	URADD8	"fun_uradd8(input(SRC1), input(SRC2))"
S	URADD16	"fun_uradd16(input(SRC1), input(SRC2))"
S	URADDW	"fun_uradd32(input(SRC1), input(SRC2))"
S	URSUB8	"fun_ursub8(input(SRC1), input(SRC2))"
S	URSUB16	"fun_ursub16(input(SRC1), input(SRC2))"
S	URSUBW	"fun_ursub32(input(SRC1), input(SRC2))"
// unary
S	CLRS8	"fun_clrs8(input(SRC1))"
S	CLO8	"fun_clo8(input(SRC1))"
S	CLZ8	"fun_clz8(input(SRC1))"
S	SWAP8	"fun_swap8(input(SRC1))"
S	SWAP16	"fun_swap16(input(SRC1))"
S	SUNPKD8 "fun_sunpkd8(input(RS1), input(INSTRUCTION)(24 downto 23) ## input(INSTRUCTION)(21 downto 20))"
S	ZUNPKD8 "fun_zunpkd8(input(RS1), input(INSTRUCTION)(24 downto 23) ## input(INSTRUCTION)(21 downto 20))"
// ternary
S	PBSADx	"fun_pbsada(input(SRC1), input(SRC2), (input(INSTRUCTION)(25).asUInt === 0) ? U(0, 32 bits).asBits | input(SRC3))"
S	INSBI	"fun_insb(input(SRC1), input(SRC2), input(SRC3))"
S	SMAQA	"fun_smaqa(input(SRC1), input(SRC2), input(SRC3))"
S	UMAQA	"fun_umaqa(input(SRC1), input(SRC2), input(SRC3))"

// saturating, fixme for csr
S  KADD8	"fun_kadd8(input(SRC1), input(SRC2))"
S  UKADD8	"fun_ukadd8(input(SRC1), input(SRC2))"
S  KSUB8	"fun_ksub8(input(SRC1), input(SRC2))"
S  UKSUB8	"fun_uksub8(input(SRC1), input(SRC2))"

P	"""
	def fun_add8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt + rs2( 7 downto  0).asUInt).asBits.resize(8)
	    val b1 = (rs1(15 downto  8).asUInt + rs2(15 downto  8).asUInt).asBits.resize(8)
	    val b2 = (rs1(23 downto 16).asUInt + rs2(23 downto 16).asUInt).asBits.resize(8)
	    val b3 = (rs1(31 downto 24).asUInt + rs2(31 downto 24).asUInt).asBits.resize(8)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_radd8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = ((rs1( 7) ## rs1( 7 downto  0)).asSInt + (rs2( 7) ## rs2( 7 downto  0)).asSInt).asBits.resize(9)
	    val b1 = ((rs1(15) ## rs1(15 downto  8)).asSInt + (rs2(15) ## rs2(15 downto  8)).asSInt).asBits.resize(9)
	    val b2 = ((rs1(23) ## rs1(23 downto 16)).asSInt + (rs2(23) ## rs2(23 downto 16)).asSInt).asBits.resize(9)
	    val b3 = ((rs1(31) ## rs1(31 downto 24)).asSInt + (rs2(31) ## rs2(31 downto 24)).asSInt).asBits.resize(9)

	    b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
	}
	def fun_rsub8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = ((rs1( 7) ## rs1( 7 downto  0)).asSInt - (rs2( 7) ## rs2( 7 downto  0)).asSInt).asBits.resize(9)
	    val b1 = ((rs1(15) ## rs1(15 downto  8)).asSInt - (rs2(15) ## rs2(15 downto  8)).asSInt).asBits.resize(9)
	    val b2 = ((rs1(23) ## rs1(23 downto 16)).asSInt - (rs2(23) ## rs2(23 downto 16)).asSInt).asBits.resize(9)
	    val b3 = ((rs1(31) ## rs1(31 downto 24)).asSInt - (rs2(31) ## rs2(31 downto 24)).asSInt).asBits.resize(9)

	    b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
	}
	
	def fun_add16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt + rs2(15 downto  0).asUInt).asBits.resize(16)
	    val h1 = (rs1(31 downto 16).asUInt + rs2(31 downto 16).asUInt).asBits.resize(16)

	    h1 ## h0 // return value
	}
	def fun_radd16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = ((rs1(15) ## rs1(15 downto  0)).asSInt + (rs2(15) ## rs2(15 downto  0)).asSInt).asBits.resize(17)
	    val h1 = ((rs1(31) ## rs1(31 downto 16)).asSInt + (rs2(31) ## rs2(31 downto 16)).asSInt).asBits.resize(17)

	    h1(16 downto 1) ## h0(16 downto 1) // return value
	}
	def fun_rsub16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = ((rs1(15) ## rs1(15 downto  0)).asSInt - (rs2(15) ## rs2(15 downto  0)).asSInt).asBits.resize(17)
	    val h1 = ((rs1(31) ## rs1(31 downto 16)).asSInt - (rs2(31) ## rs2(31 downto 16)).asSInt).asBits.resize(17)

	    h1(16 downto 1) ## h0(16 downto 1) // return value
	}
	
	def fun_radd32(rs1: Bits, rs2: Bits) : Bits = {
	    val s = ((rs1(31) ## rs1).asSInt + (rs2(31) ## rs2).asSInt).asBits.resize(33)

	    s(32 downto 1) // return value
	}
	def fun_rsub32(rs1: Bits, rs2: Bits) : Bits = {
	    val s = ((rs1(31) ## rs1).asSInt - (rs2(31) ## rs2).asSInt).asBits.resize(33)

	    s(32 downto 1) // return value
	}
	def fun_ave(rs1: Bits, rs2: Bits) : Bits = {
	    val inter = (1 + (rs1 ## B"1'b0").asUInt + (rs2 ## B"1'b0").asUInt).asBits.resize(33)

	    inter(32 downto 1) // return value
	}
	
	def fun_bitrev(rs1: Bits, rs2: Bits) : Bits = {
	    val msb = rs2(4 downto 0).asUInt
       	    val rs1r = rs1(0) ## rs1(1) ## rs1(2) ## rs1(3) ## rs1(4) ## rs1(5) ## rs1(6) ## rs1(7) ## rs1(8) ## rs1(9) ## rs1(10) ## rs1(11) ## rs1(12) ## rs1(13) ## rs1(14) ## rs1(15) ## rs1(16) ## rs1(17) ## rs1(18) ## rs1(19) ## rs1(20) ## rs1(21) ## rs1(22) ## rs1(23) ## rs1(24) ## rs1(25) ## rs1(26) ## rs1(27) ## rs1(28) ## rs1(29) ## rs1(30) ## rs1(31)
	    val rs1rs = rs1r |>> (31-msb)

	    rs1rs // return value
	}
	
	// this is trying to look like DOI 10.2478/jee-2015-0054
	def fun_clz_NLCi(x:Bits): Bits = {
	    val r2 = (~(x(0) | x(1) | x(2) | x(3)))
	    val r1 = (~(x(2) | x(3)))
	    val r0 = (~(x(3) | (x(1) & ~x(2))))
	    val r = r2 ## r1 ## r0
	    r // return value
        }
	def fun_clz_byte(in: Bits): Bits = {
	    val nlc1 = fun_clz_NLCi(in( 7 downto  4))
 	    val nlc0 = fun_clz_NLCi(in( 3 downto  0))
	    val x = ((nlc1(2).asUInt === 1) ? (4 + nlc0(1 downto 0).asUInt) | (nlc1(1 downto 0).asUInt))
	    val y = B"8'x08"
	    ((nlc0(2).asUInt === 1) && (nlc1(2).asUInt === 1)) ? y | x.asBits.resize(8) // return value
	}
	def fun_clrs8(rs1: Bits) : Bits = {
	    val b0 = rs1( 7 downto  0)
	    val b1 = rs1(15 downto  8)
	    val b2 = rs1(23 downto 16)
	    val b3 = rs1(31 downto 24)

	    val b0s = (b0(7).asUInt === 1) ? (~b0) | (b0)
	    val b1s = (b1(7).asUInt === 1) ? (~b1) | (b1)
	    val b2s = (b2(7).asUInt === 1) ? (~b2) | (b2)
	    val b3s = (b3(7).asUInt === 1) ? (~b3) | (b3)

	    val c0 = fun_clz_byte(b0s).asUInt - 1
	    val c1 = fun_clz_byte(b1s).asUInt - 1
	    val c2 = fun_clz_byte(b2s).asUInt - 1
	    val c3 = fun_clz_byte(b3s).asUInt - 1

	    c3.asBits.resize(8) ## c2.asBits.resize(8) ## c1.asBits.resize(8) ## c0.asBits.resize(8) // return value
	}
	def fun_clo8(rs1: Bits) : Bits = {
	    val b0 = rs1( 7 downto  0)
	    val b1 = rs1(15 downto  8)
	    val b2 = rs1(23 downto 16)
	    val b3 = rs1(31 downto 24)

	    val c0 = fun_clz_byte(~b0)
	    val c1 = fun_clz_byte(~b1)
	    val c2 = fun_clz_byte(~b2)
	    val c3 = fun_clz_byte(~b3)

	    c3 ## c2 ## c1 ## c0 // return value
	}
	def fun_clz8(rs1: Bits) : Bits = {
	    val b0 = rs1( 7 downto  0)
	    val b1 = rs1(15 downto  8)
	    val b2 = rs1(23 downto 16)
	    val b3 = rs1(31 downto 24)

	    val c0 = fun_clz_byte(b0)
	    val c1 = fun_clz_byte(b1)
	    val c2 = fun_clz_byte(b2)
	    val c3 = fun_clz_byte(b3)

	    c3 ## c2 ## c1 ## c0 // return value
	}
	
	def fun_swap8(rs1: Bits) : Bits = {
	    val b0 = rs1( 7 downto  0)
	    val b1 = rs1(15 downto  8)
	    val b2 = rs1(23 downto 16)
	    val b3 = rs1(31 downto 24)
	    
	    b2 ## b3 ## b0 ## b1 // return value
	}
	def fun_swap16(rs1: Bits) : Bits = {
	    val h0 = rs1(15 downto  0)
	    val h1 = rs1(31 downto 16)

	    h0 ## h1 // return value
	}
	

	def fun_cmpeq8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt === rs2( 7 downto  0).asUInt) ? B"8'xFF" | B"8'x00"
	    val b1 = (rs1(15 downto  8).asUInt === rs2(15 downto  8).asUInt) ? B"8'xFF" | B"8'x00"
	    val b2 = (rs1(23 downto 16).asUInt === rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
	    val b3 = (rs1(31 downto 24).asUInt === rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_cmpeq16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt === rs2(15 downto  0).asUInt) ? B"16'xFFFF" | B"16'x0000"
	    val h1 = (rs1(31 downto 16).asUInt === rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"

	    h1 ## h0 // return value
	}
	def fun_pkbbtt16(rs1: Bits, rs2: Bits, h:UInt, l:UInt) : Bits = {
	    val hr = (h === 0) ? rs1(15 downto 0) | rs1(31 downto 16)
	    val hl = (l === 0) ? rs2(15 downto 0) | rs2(31 downto 16)
	    
	    hr ## hl // return value
	}


	def fun_scmple8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt <= rs2( 7 downto  0).asSInt) ? B"8'xFF" | B"8'x00"
	    val b1 = (rs1(15 downto  8).asSInt <= rs2(15 downto  8).asSInt) ? B"8'xFF" | B"8'x00"
	    val b2 = (rs1(23 downto 16).asSInt <= rs2(23 downto 16).asSInt) ? B"8'xFF" | B"8'x00"
	    val b3 = (rs1(31 downto 24).asSInt <= rs2(31 downto 24).asSInt) ? B"8'xFF" | B"8'x00"

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_scmple16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asSInt <= rs2(15 downto  0).asSInt) ? B"16'xFFFF" | B"16'x0000"
	    val h1 = (rs1(31 downto 16).asSInt <= rs2(31 downto 16).asSInt) ? B"16'xFFFF" | B"16'x0000"

	    h1 ## h0 // return value
	}
	def fun_scmplt8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt < rs2( 7 downto  0).asSInt) ? B"8'xFF" | B"8'x00"
	    val b1 = (rs1(15 downto  8).asSInt < rs2(15 downto  8).asSInt) ? B"8'xFF" | B"8'x00"
	    val b2 = (rs1(23 downto 16).asSInt < rs2(23 downto 16).asSInt) ? B"8'xFF" | B"8'x00"
	    val b3 = (rs1(31 downto 24).asSInt < rs2(31 downto 24).asSInt) ? B"8'xFF" | B"8'x00"

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_scmplt16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asSInt < rs2(15 downto  0).asSInt) ? B"16'xFFFF" | B"16'x0000"
	    val h1 = (rs1(31 downto 16).asSInt < rs2(31 downto 16).asSInt) ? B"16'xFFFF" | B"16'x0000"

	    h1 ## h0 // return value
	}
	def fun_ucmple8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt <= rs2( 7 downto  0).asUInt) ? B"8'xFF" | B"8'x00"
	    val b1 = (rs1(15 downto  8).asUInt <= rs2(15 downto  8).asUInt) ? B"8'xFF" | B"8'x00"
	    val b2 = (rs1(23 downto 16).asUInt <= rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
	    val b3 = (rs1(31 downto 24).asUInt <= rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_ucmple16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt <= rs2(15 downto  0).asUInt) ? B"16'xFFFF" | B"16'x0000"
	    val h1 = (rs1(31 downto 16).asUInt <= rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"

	    h1 ## h0 // return value
	}
	def fun_ucmplt8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt < rs2( 7 downto  0).asUInt) ? B"8'xFF" | B"8'x00"
	    val b1 = (rs1(15 downto  8).asUInt < rs2(15 downto  8).asUInt) ? B"8'xFF" | B"8'x00"
	    val b2 = (rs1(23 downto 16).asUInt < rs2(23 downto 16).asUInt) ? B"8'xFF" | B"8'x00"
	    val b3 = (rs1(31 downto 24).asUInt < rs2(31 downto 24).asUInt) ? B"8'xFF" | B"8'x00"

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_ucmplt16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt < rs2(15 downto  0).asUInt) ? B"16'xFFFF" | B"16'x0000"
	    val h1 = (rs1(31 downto 16).asUInt < rs2(31 downto 16).asUInt) ? B"16'xFFFF" | B"16'x0000"

	    h1 ## h0 // return value
	}
	
	def fun_sll8(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(2 downto 0).asUInt
	    val b0 = rs1( 7 downto  0).asUInt |<< o
	    val b1 = rs1(15 downto  8).asUInt |<< o
	    val b2 = rs1(23 downto 16).asUInt |<< o
	    val b3 = rs1(31 downto 24).asUInt |<< o

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_srl8(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(2 downto 0).asUInt
	    val b0 = rs1( 7 downto  0).asUInt |>> o
	    val b1 = rs1(15 downto  8).asUInt |>> o
	    val b2 = rs1(23 downto 16).asUInt |>> o
	    val b3 = rs1(31 downto 24).asUInt |>> o

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_sra8(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(2 downto 0).asUInt
	    val b0 = rs1( 7 downto  0).asSInt |>> o
	    val b1 = rs1(15 downto  8).asSInt |>> o
	    val b2 = rs1(23 downto 16).asSInt |>> o
	    val b3 = rs1(31 downto 24).asSInt |>> o

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_sll16(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(3 downto 0).asUInt
	    val h0 = rs1(15 downto  0).asUInt |<< o
	    val h1 = rs1(31 downto 16).asUInt |<< o

	    h1 ## h0 // return value
	}
	def fun_srl16(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(3 downto 0).asUInt
	    val h0 = rs1(15 downto  0).asUInt |>> o
	    val h1 = rs1(31 downto 16).asUInt |>> o

	    h1 ## h0 // return value
	}
	def fun_sra16(rs1: Bits, rs2: Bits) : Bits = {
	    val o = rs2(3 downto 0).asUInt
	    val h0 = rs1(15 downto  0).asSInt |>> o
	    val h1 = rs1(31 downto 16).asSInt |>> o

	    h1 ## h0 // return value
	}
	
	def fun_smax8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt >= rs2( 7 downto  0).asSInt) ? rs1( 7 downto  0) | rs2( 7 downto  0)
	    val b1 = (rs1(15 downto  8).asSInt >= rs2(15 downto  8).asSInt) ? rs1(15 downto  8) | rs2(15 downto  8)
	    val b2 = (rs1(23 downto 16).asSInt >= rs2(23 downto 16).asSInt) ? rs1(23 downto 16) | rs2(23 downto 16)
	    val b3 = (rs1(31 downto 24).asSInt >= rs2(31 downto 24).asSInt) ? rs1(31 downto 24) | rs2(31 downto 24)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_smax16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asSInt >= rs2(15 downto  0).asSInt) ? rs1(15 downto  0) | rs2(15 downto  0)
	    val h1 = (rs1(31 downto 16).asSInt >= rs2(31 downto 16).asSInt) ? rs1(31 downto 16) | rs2(31 downto 16)

	    h1 ## h0 // return value
	}
	def fun_smin8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt <= rs2( 7 downto  0).asSInt) ? rs1( 7 downto  0) | rs2( 7 downto  0)
	    val b1 = (rs1(15 downto  8).asSInt <= rs2(15 downto  8).asSInt) ? rs1(15 downto  8) | rs2(15 downto  8)
	    val b2 = (rs1(23 downto 16).asSInt <= rs2(23 downto 16).asSInt) ? rs1(23 downto 16) | rs2(23 downto 16)
	    val b3 = (rs1(31 downto 24).asSInt <= rs2(31 downto 24).asSInt) ? rs1(31 downto 24) | rs2(31 downto 24)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_smin16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asSInt <= rs2(15 downto  0).asSInt) ? rs1(15 downto  0) | rs2(15 downto  0)
	    val h1 = (rs1(31 downto 16).asSInt <= rs2(31 downto 16).asSInt) ? rs1(31 downto 16) | rs2(31 downto 16)

	    h1 ## h0 // return value
	}
	def fun_umax8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt >= rs2( 7 downto  0).asUInt) ? rs1( 7 downto  0) | rs2( 7 downto  0)
	    val b1 = (rs1(15 downto  8).asUInt >= rs2(15 downto  8).asUInt) ? rs1(15 downto  8) | rs2(15 downto  8)
	    val b2 = (rs1(23 downto 16).asUInt >= rs2(23 downto 16).asUInt) ? rs1(23 downto 16) | rs2(23 downto 16)
	    val b3 = (rs1(31 downto 24).asUInt >= rs2(31 downto 24).asUInt) ? rs1(31 downto 24) | rs2(31 downto 24)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_umax16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt >= rs2(15 downto  0).asUInt) ? rs1(15 downto  0) | rs2(15 downto  0)
	    val h1 = (rs1(31 downto 16).asUInt >= rs2(31 downto 16).asUInt) ? rs1(31 downto 16) | rs2(31 downto 16)

	    h1 ## h0 // return value
	}
	def fun_umin8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt <= rs2( 7 downto  0).asUInt) ? rs1( 7 downto  0) | rs2( 7 downto  0)
	    val b1 = (rs1(15 downto  8).asUInt <= rs2(15 downto  8).asUInt) ? rs1(15 downto  8) | rs2(15 downto  8)
	    val b2 = (rs1(23 downto 16).asUInt <= rs2(23 downto 16).asUInt) ? rs1(23 downto 16) | rs2(23 downto 16)
	    val b3 = (rs1(31 downto 24).asUInt <= rs2(31 downto 24).asUInt) ? rs1(31 downto 24) | rs2(31 downto 24)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_umin16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt <= rs2(15 downto  0).asUInt) ? rs1(15 downto  0) | rs2(15 downto  0)
	    val h1 = (rs1(31 downto 16).asUInt <= rs2(31 downto 16).asUInt) ? rs1(31 downto 16) | rs2(31 downto 16)

	    h1 ## h0 // return value
	}

	def fun_sub8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt - rs2( 7 downto  0).asUInt).asBits.resize(8)
	    val b1 = (rs1(15 downto  8).asUInt - rs2(15 downto  8).asUInt).asBits.resize(8)
	    val b2 = (rs1(23 downto 16).asUInt - rs2(23 downto 16).asUInt).asBits.resize(8)
	    val b3 = (rs1(31 downto 24).asUInt - rs2(31 downto 24).asUInt).asBits.resize(8)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_sub16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = (rs1(15 downto  0).asUInt - rs2(15 downto  0).asUInt).asBits.resize(16)
	    val h1 = (rs1(31 downto 16).asUInt - rs2(31 downto 16).asUInt).asBits.resize(16)

	    h1 ## h0 // return value
	}

	def fun_uradd8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = ((B"1'b0" ## rs1( 7 downto  0)).asUInt + (B"1'b0" ## rs2( 7 downto  0)).asUInt).asBits.resize(9)
	    val b1 = ((B"1'b0" ## rs1(15 downto  8)).asUInt + (B"1'b0" ## rs2(15 downto  8)).asUInt).asBits.resize(9)
	    val b2 = ((B"1'b0" ## rs1(23 downto 16)).asUInt + (B"1'b0" ## rs2(23 downto 16)).asUInt).asBits.resize(9)
	    val b3 = ((B"1'b0" ## rs1(31 downto 24)).asUInt + (B"1'b0" ## rs2(31 downto 24)).asUInt).asBits.resize(9)

	    b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
	}
	def fun_ursub8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = ((B"1'b0" ## rs1( 7 downto  0)).asUInt - (B"1'b0" ## rs2( 7 downto  0)).asUInt).asBits.resize(9)
	    val b1 = ((B"1'b0" ## rs1(15 downto  8)).asUInt - (B"1'b0" ## rs2(15 downto  8)).asUInt).asBits.resize(9)
	    val b2 = ((B"1'b0" ## rs1(23 downto 16)).asUInt - (B"1'b0" ## rs2(23 downto 16)).asUInt).asBits.resize(9)
	    val b3 = ((B"1'b0" ## rs1(31 downto 24)).asUInt - (B"1'b0" ## rs2(31 downto 24)).asUInt).asBits.resize(9)

	    b3(8 downto 1) ## b2(8 downto 1) ## b1(8 downto 1) ## b0(8 downto 1) // return value
	}
	def fun_uradd16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = ((B"1'b0" ## rs1(15 downto  0)).asUInt + (B"1'b0" ## rs2(15 downto  0)).asUInt).asBits.resize(17)
	    val h1 = ((B"1'b0" ## rs1(31 downto 16)).asUInt + (B"1'b0" ## rs2(31 downto 16)).asUInt).asBits.resize(17)

	    h1(16 downto 1) ## h0(16 downto 1) // return value
	}
	def fun_ursub16(rs1: Bits, rs2: Bits) : Bits = {
	    val h0 = ((B"1'b0" ## rs1(15 downto  0)).asUInt - (B"1'b0" ## rs2(15 downto  0)).asUInt).asBits.resize(17)
	    val h1 = ((B"1'b0" ## rs1(31 downto 16)).asUInt - (B"1'b0" ## rs2(31 downto 16)).asUInt).asBits.resize(17)

	    h1(16 downto 1) ## h0(16 downto 1) // return value
	}
	def fun_uradd32(rs1: Bits, rs2: Bits) : Bits = {
	    val s = ((B"1'b0" ## rs1).asUInt + (B"1'b0" ## rs2).asUInt).asBits.resize(33)

	    s(32 downto 1) // return value
	}
	def fun_ursub32(rs1: Bits, rs2: Bits) : Bits = {
	    val s = ((B"1'b0" ## rs1).asUInt - (B"1'b0" ## rs2).asUInt).asBits.resize(33)

	    s(32 downto 1) // return value
	}

	def fun_pbsada(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
	    // zero-extend to handle as unsigned
	    val b0 = ((B"1'b0" ## rs1( 7 downto  0)).asSInt - (B"1'b0" ## rs2( 7 downto  0)).asSInt)
	    val b1 = ((B"1'b0" ## rs1(15 downto  8)).asSInt - (B"1'b0" ## rs2(15 downto  8)).asSInt)
	    val b2 = ((B"1'b0" ## rs1(23 downto 16)).asSInt - (B"1'b0" ## rs2(23 downto 16)).asSInt)
	    val b3 = ((B"1'b0" ## rs1(31 downto 24)).asSInt - (B"1'b0" ## rs2(31 downto 24)).asSInt)

	    val sum = rs3.asUInt + b0.abs + b1.abs + b2.abs + b3.abs

	    sum.asBits.resize(32) // return value
	}
	
	def fun_insb(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
	    val idx = rs2(1 downto 0).asUInt
	    val b = rs1(7 downto 0)
	    val r = (idx).mux(
		0 -> rs3(31 downto  8) ## b,
		1 -> rs3(31 downto 16) ## b ## rs3( 7 downto  0),
		2 -> rs3(31 downto 24) ## b ## rs3(15 downto  0),
		3 ->                      b ## rs3(23 downto  0)
	    )
	    r // return value
	}

	def fun_smaqa(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
	    val h0 = (rs1( 7 downto  0).asSInt * rs2( 7 downto  0).asSInt).resize(18)
	    val h1 = (rs1(15 downto  8).asSInt * rs2(15 downto  8).asSInt).resize(18)
	    val h2 = (rs1(23 downto 16).asSInt * rs2(23 downto 16).asSInt).resize(18)
	    val h3 = (rs1(31 downto 24).asSInt * rs2(31 downto 24).asSInt).resize(18)
	    val r = rs3.asSInt + (h0 + h1 + h2 + h3)

	    r.asBits.resize(32) // return value
	}
	def fun_umaqa(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
	// 18 bits needed so that intermediate sums don't overflow
	    val h0 = (rs1( 7 downto  0).asUInt * rs2( 7 downto  0).asUInt).resize(18)
	    val h1 = (rs1(15 downto  8).asUInt * rs2(15 downto  8).asUInt).resize(18)
	    val h2 = (rs1(23 downto 16).asUInt * rs2(23 downto 16).asUInt).resize(18)
	    val h3 = (rs1(31 downto 24).asUInt * rs2(31 downto 24).asUInt).resize(18)
	    val r = rs3.asUInt + (h0 + h1 + h2 + h3)

	    r.asBits.resize(32) // return value
	}

	def fun_zunpkd8(rs1: Bits, ctrl: Bits) : Bits = {
		val r = (ctrl).mux(
			default    -> rs1(15 downto  8).resize(16) ## rs1( 7 downto  0).resize(16), // B"4'b0100"
			B"4'b0101" -> rs1(23 downto 16).resize(16) ## rs1( 7 downto  0).resize(16),
			B"4'b0110" -> rs1(31 downto 24).resize(16) ## rs1( 7 downto  0).resize(16),
			B"4'b0111" -> rs1(31 downto 24).resize(16) ## rs1(15 downto  8).resize(16),
			B"4'b1011" -> rs1(31 downto 24).resize(16) ## rs1(23 downto 16).resize(16)
		)
		r // return value
	}
	def fun_sunpkd8(rs1: Bits, ctrl: Bits) : Bits = {
		val r = (ctrl).mux(
			default    -> rs1(15 downto  8).asSInt.resize(16).asBits ## rs1( 7 downto  0).asSInt.resize(16).asBits, // B"4'b0100"
			B"4'b0101" -> rs1(23 downto 16).asSInt.resize(16).asBits ## rs1( 7 downto  0).asSInt.resize(16).asBits,
			B"4'b0110" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1( 7 downto  0).asSInt.resize(16).asBits,
			B"4'b0111" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1(15 downto  8).asSInt.resize(16).asBits,
			B"4'b1011" -> rs1(31 downto 24).asSInt.resize(16).asBits ## rs1(23 downto 16).asSInt.resize(16).asBits
		)
		r // return value
	}

// saturating, csr is missing
// it seems sat() (and its shortcut +| and -|) in SpinalHDL don't do what I need
// for unsigned substraction (no way to tell the difference between overflow
// and underflow unless going signed, I think)
   def fun_satsub8u(a: Bits, b: Bits) : Bits = {
   	   val s = (B"1'b0" ## a).asSInt -^ (B"1'b0" ## b).asSInt // -^ will keep 10 bits
	   // if sign bit set -> underflow, else if bit eight set -> overflow
	   val r = ((s(9).asUInt === 1) ? (B"8'x00") | ((s(8).asUInt === 1) ? (B"8'xFF") | (s(7 downto 0).asBits)))
	   
	   r // return value
   }

	def fun_kadd8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt +| rs2( 7 downto  0).asSInt).asBits.resize(8)
	    val b1 = (rs1(15 downto  8).asSInt +| rs2(15 downto  8).asSInt).asBits.resize(8)
	    val b2 = (rs1(23 downto 16).asSInt +| rs2(23 downto 16).asSInt).asBits.resize(8)
	    val b3 = (rs1(31 downto 24).asSInt +| rs2(31 downto 24).asSInt).asBits.resize(8)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_ukadd8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asUInt +| rs2( 7 downto  0).asUInt).asBits.resize(8)
	    val b1 = (rs1(15 downto  8).asUInt +| rs2(15 downto  8).asUInt).asBits.resize(8)
	    val b2 = (rs1(23 downto 16).asUInt +| rs2(23 downto 16).asUInt).asBits.resize(8)
	    val b3 = (rs1(31 downto 24).asUInt +| rs2(31 downto 24).asUInt).asBits.resize(8)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_ksub8(rs1: Bits, rs2: Bits) : Bits = {
	    val b0 = (rs1( 7 downto  0).asSInt -| rs2( 7 downto  0).asSInt).asBits.resize(8)
	    val b1 = (rs1(15 downto  8).asSInt -| rs2(15 downto  8).asSInt).asBits.resize(8)
	    val b2 = (rs1(23 downto 16).asSInt -| rs2(23 downto 16).asSInt).asBits.resize(8)
	    val b3 = (rs1(31 downto 24).asSInt -| rs2(31 downto 24).asSInt).asBits.resize(8)

	    b3 ## b2 ## b1 ## b0 // return value
	}
	def fun_uksub8(rs1: Bits, rs2: Bits) : Bits = {
		val b0 = fun_satsub8u(rs1( 7 downto  0), rs2( 7 downto  0)).asBits
		val b1 = fun_satsub8u(rs1(15 downto  8), rs2(15 downto  8)).asBits
		val b2 = fun_satsub8u(rs1(23 downto 16), rs2(23 downto 16)).asBits
		val b3 = fun_satsub8u(rs1(31 downto 24), rs2(31 downto 24)).asBits

	    b3 ## b2 ## b1 ## b0 // return value
	}
"""