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42 | 42 |
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43 | 43 | /* Video path registers */ |
44 | 44 | #define VP_CTRL 0x0450 /* Video Path Control */ |
45 | | -#define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ |
46 | | -#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ |
47 | | -#define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ |
48 | | -#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ |
| 45 | +#define VP_CTRL_MSF BIT(0) /* Magic square in RGB666 */ |
| 46 | +#define VP_CTRL_VTGEN BIT(4) /* Use chip clock for timing */ |
| 47 | +#define VP_CTRL_EVTMODE BIT(5) /* Event mode */ |
| 48 | +#define VP_CTRL_RGB888 BIT(8) /* RGB888 mode */ |
49 | 49 | #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ |
50 | 50 | #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ |
51 | 51 | #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ |
@@ -233,8 +233,8 @@ static int tc358764_init(struct tc358764 *ctx) |
233 | 233 | tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START); |
234 | 234 |
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235 | 235 | /* configure video path */ |
236 | | - tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) | |
237 | | - VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL); |
| 236 | + tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888 | |
| 237 | + VP_CTRL_EVTMODE | VP_CTRL_HSPOL | VP_CTRL_VSPOL); |
238 | 238 |
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239 | 239 | /* reset PHY */ |
240 | 240 | tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) | |
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