Support Synopsys ARC HS44/HS46/HS4 architecture

[XVilka]

The ARC HS4x CPUs like the HS44, HS46, and HS48 are 32-bit superscalar CPUs for embedded environments. The HS44/HS46/HS48 CPUs support up to 1.9GHz clock speeds, 2.5 DMIPS/MHz, and use the ARCv2 instruction set. These embedded ARC processors are used in everything from networking devices and smart IoT appliances to SSD controllers.

http://linleygroup.com/synopsys/whitepaper/pdf/

Seems instruction set is not in public, while the support was pushed into GCC 9.0. Silly people, sigh.

https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f158ddd48e23b6b38cccf16a9628c46cfded4bc7

https://github.com/foss-for-synopsys-dwc-arc-processors

[Maijin]

Do you have some docs ?

[ret2libc]

This issue has been moved from radareorg/radare2 to radareorg/ideas as we are trying to clean our backlog and this issue has probably been created a long while ago. This is an effort to help contributors understand what are the actionable items they can work on, prioritize issues better and help users find active/duplicated issues more easily. If this is not an enhancement/improvement/general idea but a bug, feel free to ask for re-transfer to main repo. Thanks for your understanding and contribution with this issue.