target/hexagon: raise exception on multiple writes to same reg

As specified by the PRM, we should raise an exception when a packet
contains multiple writes to the same register. Lets introduce a bitmap
at the CPUArchState, looking for writes to already written registers and
properly generate an exception when needed. Also add a test case to
tests/tcg/system.

Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>

Author: quic-mathbern

target/hexagon/cpu.h

@@ -28,6 +28,7 @@
 
 #define NUM_PREGS 4
 #define TOTAL_PER_THREAD_REGS 64
+#define NUM_GPREGS 32
 
 #define SLOTS_MAX 4
 #define STORES_MAX 2
@@ -78,6 +79,9 @@ typedef struct CPUArchState {
 
     uint8_t slot_cancelled;
     target_ulong new_value_usr;
+    target_ulong gpreg_written;
+    QEMU_BUILD_BUG_MSG(NUM_GPREGS > CHAR_BIT * sizeof(target_ulong),
+                       "Hexagon's CPUArchState.gpreg_written type is too small");
 
     MemLog mem_log_stores[STORES_MAX];
 

target/hexagon/cpu_bits.h

@@ -26,6 +26,7 @@
 enum hex_event {
     HEX_EVENT_NONE           = -1,
     HEX_EVENT_TRAP0          =  0x008,
+    HEX_EVENT_PRECISE        =  0x2,
 };
 
 enum hex_cause {
@@ -34,6 +35,7 @@ enum hex_cause {
     HEX_CAUSE_FETCH_NO_UPAGE =  0x012,
     HEX_CAUSE_INVALID_PACKET =  0x015,
     HEX_CAUSE_INVALID_OPCODE =  0x015,
+    HEX_CAUSE_REG_WRITE_CONFLICT = 0x01d,
     HEX_CAUSE_PC_NOT_ALIGNED =  0x01e,
     HEX_CAUSE_PRIV_NO_UREAD  =  0x024,
     HEX_CAUSE_PRIV_NO_UWRITE =  0x025,

target/hexagon/genptr.c

@@ -100,6 +100,7 @@ void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val)
 
     gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
     tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val);
+    gen_helper_check_reg_write(tcg_env, tcg_constant_tl(rnum));
 }
 
 static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val)
@@ -113,6 +114,8 @@ static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val)
     /* High word */
     tcg_gen_extrh_i64_i32(val32, val);
     gen_log_reg_write(ctx, rnum + 1, val32);
+
+    gen_helper_check_reg_write_pair(tcg_env, tcg_constant_tl(rnum));
 }
 
 TCGv get_result_pred(DisasContext *ctx, int pnum)

target/hexagon/helper.h

@@ -30,6 +30,10 @@ DEF_HELPER_5(vacsh_val, s64, env, s64, s64, s64, i32)
 DEF_HELPER_FLAGS_4(vacsh_pred, TCG_CALL_NO_RWG_SE, s32, env, s64, s64, s64)
 DEF_HELPER_FLAGS_2(cabacdecbin_val, TCG_CALL_NO_RWG_SE, s64, s64, s64)
 DEF_HELPER_FLAGS_2(cabacdecbin_pred, TCG_CALL_NO_RWG_SE, s32, s64, s64)
+DEF_HELPER_2(check_reg_write, void, env, int)
+DEF_HELPER_3(check_cond_reg_write, void, env, int, int)
+DEF_HELPER_2(check_reg_write_pair, void, env, int)
+DEF_HELPER_3(check_cond_reg_write_pair, void, env, int, int)
 
 /* Floating point */
 DEF_HELPER_2(conv_sf2df, f64, env, f32)

target/hexagon/op_helper.c

@@ -59,6 +59,24 @@ void log_store32(CPUHexagonState *env, target_ulong addr,
     env->mem_log_stores[slot].data32 = val;
 }
 
+static void do_check_reg_write(CPUHexagonState *env, int rnum)
+{
+    target_ulong mask = 1 << rnum;
+    if (rnum >= NUM_GPREGS) {
+        return;
+    }
+    if ((env->gpreg_written & mask) == 0) {
+        env->gpreg_written |= mask;
+        return;
+    }
+#ifdef CONFIG_USER_ONLY
+    hexagon_raise_exception_err(env, HEX_CAUSE_REG_WRITE_CONFLICT, 0);
+#else
+    env->cause_code = HEX_CAUSE_REG_WRITE_CONFLICT;
+    hexagon_raise_exception_err(env, HEX_EVENT_PRECISE, 0);
+#endif
+}
+
 void log_store64(CPUHexagonState *env, target_ulong addr,
                  int64_t val, int width, int slot)
 {
@@ -67,6 +85,32 @@ void log_store64(CPUHexagonState *env, target_ulong addr,
     env->mem_log_stores[slot].data64 = val;
 }
 
+void HELPER(check_reg_write)(CPUHexagonState *env, int rnum)
+{
+    do_check_reg_write(env, rnum);
+}
+
+void HELPER(check_cond_reg_write)(CPUHexagonState *env, int rnum, int skip)
+{
+    if (!skip) {
+        do_check_reg_write(env, rnum);
+    }
+}
+
+void HELPER(check_reg_write_pair)(CPUHexagonState *env, int rnum)
+{
+    do_check_reg_write(env, rnum);
+    do_check_reg_write(env, rnum + 1);
+}
+
+void HELPER(check_cond_reg_write_pair)(CPUHexagonState *env, int rnum, int skip)
+{
+    if (!skip) {
+        do_check_reg_write(env, rnum);
+        do_check_reg_write(env, rnum + 1);
+    }
+}
+
 static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
 {
     uint8_t width = env->mem_log_stores[slot_num].width;

target/hexagon/translate.c

@@ -50,6 +50,7 @@ TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 TCGv hex_pred[NUM_PREGS];
 TCGv hex_slot_cancelled;
 TCGv hex_new_value_usr;
+TCGv hex_gpreg_written;
 TCGv hex_store_addr[STORES_MAX];
 TCGv hex_store_width[STORES_MAX];
 TCGv hex_store_val32[STORES_MAX];
@@ -438,6 +439,7 @@ static void gen_start_packet(DisasContext *ctx)
      * gen phase, so clear it again.
      */
     bitmap_zero(ctx->pregs_written, NUM_PREGS);
+    tcg_gen_movi_tl(hex_gpreg_written, 0);
 
     /* Initialize the runtime state for packet semantics */
     if (need_slot_cancelled(pkt)) {
@@ -1057,6 +1059,9 @@ void hexagon_translate_init(void)
     hex_new_value_usr = tcg_global_mem_new(tcg_env,
         offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
 
+    hex_gpreg_written = tcg_global_mem_new(tcg_env,
+                offsetof(CPUHexagonState, gpreg_written), "gpreg_written");
+
     for (i = 0; i < NUM_PREGS; i++) {
         hex_pred[i] = tcg_global_mem_new(tcg_env,
             offsetof(CPUHexagonState, pred[i]),

target/hexagon/translate.h

@@ -270,6 +270,7 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 extern TCGv hex_pred[NUM_PREGS];
 extern TCGv hex_slot_cancelled;
 extern TCGv hex_new_value_usr;
+extern TCGv hex_gpreg_written;
 extern TCGv hex_store_addr[STORES_MAX];
 extern TCGv hex_store_width[STORES_MAX];
 extern TCGv hex_store_val32[STORES_MAX];