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target/hexagon: s/pkt_has_store/pkt_has_scalar_store
To remove any confusion with HVX or other potential store instructions, we'll qualify this context var with "scalar". Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
1 parent dba1c56 commit 9f19722

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9 files changed

+21
-19
lines changed

9 files changed

+21
-19
lines changed

target/hexagon/decode.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -236,9 +236,9 @@ static void decode_set_insn_attr_fields(Packet *pkt)
236236
if (GET_ATTRIB(opcode, A_SCALAR_STORE) &&
237237
!GET_ATTRIB(opcode, A_MEMSIZE_0B)) {
238238
if (pkt->insn[i].slot == 0) {
239-
pkt->pkt_has_store_s0 = true;
239+
pkt->pkt_has_scalar_store_s0 = true;
240240
} else {
241-
pkt->pkt_has_store_s1 = true;
241+
pkt->pkt_has_scalar_store_s1 = true;
242242
}
243243
}
244244
}

target/hexagon/gen_helper_funcs.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
6969
if hex_common.need_slot(tag):
7070
if "A_LOAD" in hex_common.attribdict[tag]:
7171
f.write(hex_common.code_fmt(f"""\
72-
bool pkt_has_store_s1 = slotval & 0x1;
72+
bool pkt_has_scalar_store_s1 = slotval & 0x1;
7373
"""))
7474
f.write(hex_common.code_fmt(f"""\
7575
uint32_t slot = slotval >> 1;

target/hexagon/genptr.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,8 @@ static inline void gen_store_conditional8(DisasContext *ctx,
395395
#ifndef CONFIG_HEXAGON_IDEF_PARSER
396396
static TCGv gen_slotval(DisasContext *ctx)
397397
{
398-
int slotval = (ctx->pkt->pkt_has_store_s1 & 1) | (ctx->insn->slot << 1);
398+
int slotval =
399+
(ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
399400
return tcg_constant_tl(slotval);
400401
}
401402
#endif

target/hexagon/idef-parser/README.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -637,7 +637,7 @@ tinycode for the Hexagon ``add`` instruction
637637
::
638638

639639
---- 00021094
640-
mov_i32 pkt_has_store_s1,$0x0
640+
mov_i32 pkt_has_scalar_store_s1,$0x0
641641
add_i32 tmp0,r2,r2
642642
mov_i32 loc2,tmp0
643643
mov_i32 new_r1,loc2

target/hexagon/idef-parser/parser-helpers.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1725,7 +1725,7 @@ void gen_cancel(Context *c, YYLTYPE *locp)
17251725

17261726
void gen_load_cancel(Context *c, YYLTYPE *locp)
17271727
{
1728-
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
1728+
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
17291729
OUT(c, locp, "ctx->s1_store_processed = false;\n");
17301730
OUT(c, locp, "process_store(ctx, 1);\n");
17311731
OUT(c, locp, "}\n");
@@ -1750,7 +1750,7 @@ void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
17501750

17511751
/* Lookup the effective address EA */
17521752
find_variable(c, locp, ea, ea);
1753-
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
1753+
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
17541754
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
17551755
OUT(c, locp, "process_store(ctx, 1);\n");
17561756
OUT(c, locp, "}\n");

target/hexagon/insn.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,8 @@ struct Packet {
6666

6767
bool pkt_has_dczeroa;
6868

69-
bool pkt_has_store_s0;
70-
bool pkt_has_store_s1;
69+
bool pkt_has_scalar_store_s0;
70+
bool pkt_has_scalar_store_s1;
7171

7272
bool pkt_has_hvx;
7373
Insn *vhist_insn;

target/hexagon/macros.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@
8282
*/
8383
#define CHECK_NOSHUF(VA, SIZE) \
8484
do { \
85-
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
85+
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
8686
probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
8787
process_store(ctx, 1); \
8888
} \
@@ -93,11 +93,11 @@
9393
TCGLabel *noshuf_label = gen_new_label(); \
9494
tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
9595
GET_EA; \
96-
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
96+
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
9797
probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
9898
} \
9999
gen_set_label(noshuf_label); \
100-
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
100+
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
101101
process_store(ctx, 1); \
102102
} \
103103
} while (0)
@@ -524,7 +524,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
524524

525525
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
526526
do { \
527-
check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
527+
check_noshuf(env, pkt_has_scalar_store_s1, slot, EA, SIZE, GETPC()); \
528528
DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
529529
} while (0)
530530
#endif

target/hexagon/op_helper.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -463,11 +463,11 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
463463
* If the load is in slot 0 and there is a store in slot1 (that
464464
* wasn't cancelled), we have to do the store first.
465465
*/
466-
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
466+
static void check_noshuf(CPUHexagonState *env, bool pkt_has_scalar_store_s1,
467467
uint32_t slot, target_ulong vaddr, int size,
468468
uintptr_t ra)
469469
{
470-
if (slot == 0 && pkt_has_store_s1 &&
470+
if (slot == 0 && pkt_has_scalar_store_s1 &&
471471
((env->slot_cancelled & (1 << 1)) == 0)) {
472472
probe_read(env, vaddr, size, MMU_USER_IDX, ra);
473473
commit_store(env, 1, ra);

target/hexagon/translate.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -693,11 +693,11 @@ static void process_store_log(DisasContext *ctx)
693693
* the memory accesses overlap.
694694
*/
695695
Packet *pkt = ctx->pkt;
696-
if (pkt->pkt_has_store_s1) {
696+
if (pkt->pkt_has_scalar_store_s1) {
697697
g_assert(!pkt->pkt_has_dczeroa);
698698
process_store(ctx, 1);
699699
}
700-
if (pkt->pkt_has_store_s0) {
700+
if (pkt->pkt_has_scalar_store_s0) {
701701
g_assert(!pkt->pkt_has_dczeroa);
702702
process_store(ctx, 0);
703703
}
@@ -822,8 +822,9 @@ static void gen_commit_packet(DisasContext *ctx)
822822
* involved in committing the packet.
823823
*/
824824
Packet *pkt = ctx->pkt;
825-
bool has_store_s0 = pkt->pkt_has_store_s0;
826-
bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
825+
bool has_store_s0 = pkt->pkt_has_scalar_store_s0;
826+
bool has_store_s1 =
827+
(pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed);
827828
bool has_hvx_store = pkt_has_hvx_store(pkt);
828829
if (pkt->pkt_has_dczeroa) {
829830
/*

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