Merge pull request #1 from pythonspeed/raw-events

Raw events

Author: itamarst

Cargo.lock

@@ -1,6 +1,6 @@
 [package]
 name = "py-perf-event"
-version = "0.1.0"
+version = "0.2.0"
 edition = "2021"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

Cargo.toml

@@ -25,4 +25,5 @@ Until more docs are available, you can use the underlying Rust libraries docs to
 
 ## Changelog
 
+* **0.2:** Exposed `Raw` events.
 * **0.1:** Initial, very minimal release.

README.md

@@ -1 +1,3 @@
 pytest
+numba
+numpy

requirements-dev.txt

@@ -68,6 +68,19 @@ pub struct Hardware(events::Hardware);
 
 expose_consts!(Hardware, CPU_CYCLES, INSTRUCTIONS, CACHE_REFERENCES, CACHE_MISSES, BRANCH_INSTRUCTIONS, BRANCH_MISSES, BUS_CYCLES, STALLED_CYCLES_FRONTEND, STALLED_CYCLES_BACKEND, REF_CPU_CYCLES);
 
+/// A raw, model-specific CPU counter.
+#[derive(Clone, Copy)]
+#[pyclass]
+pub struct Raw(events::Raw);
+
+#[pymethods]
+impl Raw {
+    #[new]
+    fn new(config: u64) -> Self {
+        Raw(events::Raw::new(config))
+    }
+}
+
 /// Start gathering counter information, given a list of Hardware or Cache
 /// instances.
 #[pyclass]
@@ -87,6 +100,10 @@ impl Measure {
                 counters.push(group.add(&perf_event::Builder::new(hw.0))?);
                 continue;
             }
+            if let Ok(raw) = event.extract::<Raw>() {
+                counters.push(group.add(&perf_event::Builder::new(raw.0))?);
+                continue;
+            }
             let cache: Cache = event.extract()?;
             let cache: events::Cache = cache.into();
             counters.push(group.add(&perf_event::Builder::new(cache))?);
@@ -136,6 +153,7 @@ fn py_perf_event(_py: Python, m: &PyModule) -> PyResult<()> {
     m.add_class::<CacheResult>()?;
     m.add_class::<Cache>()?;
     m.add_class::<Hardware>()?;
+    m.add_class::<Raw>()?;
     m.add_class::<Measure>()?;
     m.add_function(wrap_pyfunction!(measure, m)?)?;
     Ok(())

src/lib.rs

@@ -1,10 +1,13 @@
+import numpy as np
+from numba import njit
 from py_perf_event import (
     Measure,
     Hardware,
     Cache,
     CacheId,
     CacheOp,
     CacheResult,
+    Raw,
     measure,
 )
 
@@ -57,3 +60,32 @@ def traverse(l):
     assert small_misses <= small_reads
     assert large_reads > 1000 * small_reads
     assert (large_misses / large_reads) > 0.2
+
+
+def test_raw():
+    """
+    ``Raw()`` events get measured.
+
+    TODO: This test is model-specific, only tested on i7-12700K.
+    """
+    # SIMD on float64:
+    simd_f64 = [Raw(0x4c7), Raw(0x10c7)]
+
+    f64_data = np.ones((1_000_000,), dtype=np.float64)
+    f32_data = np.ones((1_000_000,), dtype=np.float32)
+
+    @njit
+    def double(arr):
+        result = np.empty(arr.shape, dtype=arr.dtype)
+        # Should auto-vectorize to SIMD;
+        for i in range(len(arr)):
+            result[i] = 2 * arr[i]
+        return result
+
+    double(f64_data)
+    double(f32_data)
+
+    with_f64 = sum(measure(simd_f64, double, f64_data))
+    assert with_f64 > (1_000_000 / 8) * 0.5
+    with_f32 = sum(measure(simd_f64, double, f32_data))
+    assert with_f32 < 100