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41 | 41 | (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) |
42 | 42 |
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43 | 43 | #define MIDR_CPU_MODEL(imp, partnum) \ |
44 | | - (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ |
| 44 | + ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \ |
45 | 45 | (0xf << MIDR_ARCHITECTURE_SHIFT) | \ |
46 | 46 | ((partnum) << MIDR_PARTNUM_SHIFT)) |
47 | 47 |
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80 | 80 | #define ARM_CPU_PART_CORTEX_X1 0xD44 |
81 | 81 | #define ARM_CPU_PART_CORTEX_A510 0xD46 |
82 | 82 | #define ARM_CPU_PART_CORTEX_A710 0xD47 |
| 83 | +#define ARM_CPU_PART_CORTEX_A715 0xD4D |
83 | 84 | #define ARM_CPU_PART_CORTEX_X2 0xD48 |
84 | 85 | #define ARM_CPU_PART_NEOVERSE_N2 0xD49 |
85 | 86 | #define ARM_CPU_PART_CORTEX_A78C 0xD4B |
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123 | 124 | #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 |
124 | 125 | #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 |
125 | 126 | #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 |
| 127 | +#define APPLE_CPU_PART_M2_BLIZZARD 0x032 |
| 128 | +#define APPLE_CPU_PART_M2_AVALANCHE 0x033 |
126 | 129 |
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127 | 130 | #define AMPERE_CPU_PART_AMPERE1 0xAC3 |
128 | 131 |
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142 | 145 | #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) |
143 | 146 | #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) |
144 | 147 | #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) |
| 148 | +#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) |
145 | 149 | #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) |
146 | 150 | #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) |
147 | 151 | #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) |
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175 | 179 | #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) |
176 | 180 | #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) |
177 | 181 | #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) |
| 182 | +#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD) |
| 183 | +#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) |
178 | 184 | #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) |
179 | 185 |
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180 | 186 | /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ |
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