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Adds missing opcodes for part. implemented xpulp sets
- immediate for xpulpbitop and xpulpclip are not in [CORE-V Instruction Set Extensions](https://cv32e40p.readthedocs.io/en/latest/instruction_set_extensions/#simd-alu-encoding) and therefore not encoded - for xpulpvect replaced opcodes for form pv.<op1>.h.<op2> with ones of form pv.<op1>.<op2> for op1={add,sub} and op2={div2,div4,div8} - for xpulpminmax used p.addN, p.adduN instead of p.avg, p.avgu as suggested in [Pulp Extensions](https://iis-people.ee.ethz.ch/~balasr/pulp-ext/pulp.html#xpulpminmax)
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,22 @@ | ||
# format of a line in this file: | ||
# <instruction name> <args> <opcode> | ||
# | ||
# <opcode> is given by specifying one or more range/value pairs: | ||
# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) | ||
# | ||
# <args> is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, | ||
# shamtw, shamt, rm | ||
|
||
pv.shuffle.h rd rs1 rs2 31..27=24 26=0 25=0 14..12=0 6..2=0x15 1..0=3 | ||
pv.shuffle.sci.h rd rs1 imm6 31..27=24 26=0 14..12=6 6..2=0x15 1..0=3 | ||
pv.shuffle.b rd rs1 rs2 31..27=24 26=0 25=0 14..12=1 6..2=0x15 1..0=3 | ||
pv.shufflei0.sci.b rd rs1 imm6 31..27=24 26=0 14..12=7 6..2=0x15 1..0=3 | ||
pv.shufflei1.sci.b rd rs1 imm6 31..27=29 26=0 14..12=7 6..2=0x15 1..0=3 | ||
pv.shufflei2.sci.b rd rs1 imm6 31..27=30 26=0 14..12=7 6..2=0x15 1..0=3 | ||
pv.shufflei3.sci.b rd rs1 imm6 31..27=31 26=0 14..12=7 6..2=0x15 1..0=3 | ||
pv.shuffle.h rd rs1 rs2 31..27=24 26=0 25=0 14..12=0 6..2=0x15 1..0=3 | ||
pv.shuffle.b rd rs1 rs2 31..27=24 26=0 25=0 14..12=1 6..2=0x15 1..0=3 | ||
pv.pack rd rs1 rs2 31..27=26 26=0 25=0 14..12=0 6..2=0x15 1..0=3 | ||
pv.pack.h rd rs1 rs2 31..27=26 26=0 25=1 14..12=0 6..2=0x15 1..0=3 | ||
pv.packhi.b rd rs1 rs2 31..27=27 26=0 25=0 14..12=1 6..2=0x15 1..0=3 | ||
pv.packlo.b rd rs1 rs2 31..27=28 26=0 25=0 14..12=1 6..2=0x15 1..0=3 |
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