From 1e5fa7787b4e388c51956f6e7fd26d4d249a7d80 Mon Sep 17 00:00:00 2001 From: oswaldlo1 Date: Tue, 8 Mar 2022 18:08:23 +0100 Subject: [PATCH] Adds snitch opcodes - Makefile supports now enabling different sets of xpulp - Makefile and parse_opcodes adapted to support snitch opcodes - fixes some minor mistakes --- Makefile | 51 +- README.md | 29 +- encoding_out.h | 4697 -------------------- inst.sverilog | 1552 ------- opcodes-dma | 8 + opcodes-flt-occamy | 789 ++++ opcodes-ipu | 97 + opcodes-rep | 3 + opcodes-rv32b_CUSTOM | 71 + opcodes_sflt_CUSTOM => opcodes-sflt_CUSTOM | 0 opcodes-ssr | 4 + opcodes-xpulpabs_CUSTOM | 10 + opcodes-xpulpminmax_CUSTOM | 4 +- opcodes-xpulpvectshufflepack_CUSTOM | 4 +- parse_opcodes | 281 ++ 15 files changed, 1343 insertions(+), 6257 deletions(-) delete mode 100644 encoding_out.h delete mode 100644 inst.sverilog create mode 100644 opcodes-dma create mode 100644 opcodes-flt-occamy create mode 100644 opcodes-ipu create mode 100644 opcodes-rep create mode 100644 opcodes-rv32b_CUSTOM rename opcodes_sflt_CUSTOM => opcodes-sflt_CUSTOM (100%) create mode 100644 opcodes-ssr create mode 100644 opcodes-xpulpabs_CUSTOM diff --git a/Makefile b/Makefile index 2b9f9f55..d9e2e89d 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,36 @@ SHELL := /bin/sh ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system -ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv +ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom +# set with possible overlap +# ALL_REAL_OPCODES += opcodes-rvv + # Add here your opcodes -XPULPIMG_OPCODES := opcodes-xpulpbitop_CUSTOM opcodes-xpulpbitopsmall_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulphwloop_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM -MY_OPCODES := opcodes-frep_CUSTOM opcodes-xpulpimg_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes_sflt_CUSTOM +XPULPIMG_OPCODES := opcodes-xpulpbr_CUSTOM +XPULPIMG_OPCODES += opcodes-xpulpclip_CUSTOM +XPULPIMG_OPCODES += opcodes-xpulpmacsi_CUSTOM +XPULPIMG_OPCODES += opcodes-xpulpslet_CUSTOM +XPULPIMG_OPCODES += opcodes-xpulpvect_CUSTOM +XPULPIMG_OPCODES += opcodes-xpulpvectshufflepack_CUSTOM +# sets with possible overlaps +#XPULPIMG_OPCODES += opcodes-xpulpminmax_CUSTOM +#XPULPIMG_OPCODES += opcodes-xpulphwloop_CUSTOM +#XPULPIMG_OPCODES += opcodes-xpulpbitop_CUSTOM +# XPULPIMG_OPCODES += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM + +SNITCH_OPCODES := opcodes-dma +SNITCH_OPCODES += opcodes-ipu +SNITCH_OPCODES += opcodes-rep +SNITCH_OPCODES += opcodes-ssr +SNITCH_OPCODES += opcodes-rv32b_CUSTOM +# sets with possible overlaps +# SNITCH_OPCODES += opcodes-flt-occamy + +MY_OPCODES := opcodes-frep_CUSTOM +MY_OPCODES += opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT +MY_OPCODES += opcodes-sflt_CUSTOM +MY_OPCODES += $(XPULPIMG_OPCODES) +#MY_OPCODES += $(SNITCH_OPCODES) ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) $(MY_OPCODES) opcodes-rvv-pseudo # Opcodes to be discarded @@ -12,6 +38,12 @@ DISCARDED_OPCODES := opcodes-frep_CUSTOM OPCODES = $(filter-out $(sort $(DISCARDED_OPCODES)), $(sort $(ALL_OPCODES))) +# Snitch legacy opcode collection +OPCODES_C := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM opcodes-ipu opcodes-dma +OPCODES_SV := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM opcodes-ipu +OPCODES_PY := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) +OPCODES_RS := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM + all: encoding_out.h inst.sverilog # Makefile inserted as prerequisite of every recipe because it can change due to DISCARDED_OPCODES @@ -30,6 +62,19 @@ inst.chisel: $(OPCODES) parse_opcodes Makefile inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes Makefile cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@ +inst.c: $(OPCODES) parse_opcodes Makefile + cat $(OPCODES_C) | ./parse_opcodes -c > $@ + +inst.sv: $(OPCODES) parse_opcodes Makefile + cat $(OPCODES_SV) | ./parse_opcodes -sv > $@ + +inst.py: $(OPCODES) parse_opcodes Makefile + cat $(OPCODES_PY) | ./parse_opcodes -py > $@ + +inst.rs: $(OPCODES) parse_opcodes Makefile + cat $(OPCODES_RS) | ./parse_opcodes -rust > $@ + rustfmt $@ + inst.sverilog: $(OPCODES) parse_opcodes Makefile cat $(OPCODES) | ./parse_opcodes -sverilog > $@ diff --git a/README.md b/README.md index 4b811022..76b0197f 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ riscv-opcodes This repo enumerates standard RISC-V instruction opcodes and control and status registers, as well as some custom modifications. It also contains a -script to convert them into several formats (C, SystemVerilog, Scala, LaTeX), +script to convert them into several formats (C, Python, Go, SystemVerilog, Scala, LaTeX), starting from their high-level, human-readable description. ## Practical info @@ -37,3 +37,30 @@ starting from their high-level, human-readable description. (`opcodes-rvv` file) have been set as pseudo-instruction due to the overlapping of their opcodes space with the opcodes space of the SIMD instructions from Xpulpv2, defined in `opcodes-xpulpimg_CUSTOM`. + + +## Smallfloat notice + +The Snitch cores use `opcodes-flt-occamy` to decode smallfloat instructions. +`opcodes-sflt` is not used but describes how ariane (CVA6) decodes +instructions. This file is not used but kept in this repository for reference. +Ariane and Snitch do not use the same FPU configuration. + + +## Snitch notices +`opcodes-sflt = opcodes-sflt_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT` +for instructions `flb, fsb, fcvt.h.b, fcvt.b.h` an `@` is now used in front + +`opcodes-flt-occamy` will conflict with `opcodes-sflt_CUSTOM`, `opcodes-rv32d-zfh_DRAFT`, `opcodes-rv32q-zfh_DRAFT`, `opcodes-rv32zfh_DRAFT`, `opcodes-rv64zfh_DRAFT` + +`hfence.bvma` was renamed to `hfence.vvma` (same opcode) + +the RV32B opcodes were put into its own custom file `opcodes-rv32b_CUSTOM` + +## Overlap notices +`opcodes-rvv` and `opcodes-xpulpbitop` overlap +`opcodes-xpulpbitop` is superset of `opcodes-xpulpbitopsmall` +`opcodes-flt-occamy` overlaps `opcodes-sflt_CUSTOM`, `opcodes-rv32d-zfh_DRAFT`, `opcodes-rv32q-zfh_DRAFT`, `opcodes-rv32zfh_DRAFT`, `opcodes-rv64zfh_DRAFT` +`opcodes-rv32b_CUSTOM` overlaps `opcodes-xpulpbitop`,`opcodes-xpulpbitopsmall` +`opcodes-xpulphwloop_CUSTOM` overlaps `opcodes-ipu` +`opcodes-minmax` overlaps `opcodes-rv32b_CUSTOM` \ No newline at end of file diff --git a/encoding_out.h b/encoding_out.h deleted file mode 100644 index a3727ecf..00000000 --- a/encoding_out.h +++ /dev/null @@ -1,4697 +0,0 @@ -/* - * This file is auto-generated by running 'make encoding_out.h' in 'riscv-opcodes' - */ - -/* See LICENSE for license details. */ - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS_GVA 0x0000004000000000 -#define MSTATUS_MPV 0x0000008000000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_VS_MASK (SSTATUS_SIE | SSTATUS_SPIE | \ - SSTATUS_SPP | SSTATUS_SUM | \ - SSTATUS_MXR | SSTATUS_UXL) - -#define HSTATUS_VSXL 0x300000000 -#define HSTATUS_VTSR 0x00400000 -#define HSTATUS_VTW 0x00200000 -#define HSTATUS_VTVM 0x00100000 -#define HSTATUS_VGEIN 0x0003f000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_SPVP 0x00000100 -#define HSTATUS_SPV 0x00000080 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_VSBE 0x00000020 - -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 -#define DCSR_CAUSE_GROUP 6 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_VSSIP (1 << IRQ_VS_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_VSTIP (1 << IRQ_VS_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_VSEIP (1 << IRQ_VS_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) -#define MIP_SGEIP (1 << IRQ_S_GEXT) - -#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) - -#define MIDELEG_FORCED_MASK MIP_HS_MASK - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_M 3 - -#define PRV_HS (PRV_S + 1) - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define HGATP32_MODE 0x80000000 -#define HGATP32_VMID 0x1FC00000 -#define HGATP32_PPN 0x003FFFFF - -#define HGATP64_MODE 0xF000000000000000 -#define HGATP64_VMID 0x03FFF00000000000 -#define HGATP64_PPN 0x00000FFFFFFFFFFF - -#define HGATP_MODE_OFF 0 -#define HGATP_MODE_SV32X4 1 -#define HGATP_MODE_SV39X4 8 -#define HGATP_MODE_SV48X4 9 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -/* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse_opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f -#define MATCH_FRFLAGS 0x102073 -#define MASK_FRFLAGS 0xfffff07f -#define MATCH_FSFLAGS 0x101073 -#define MASK_FSFLAGS 0xfff0707f -#define MATCH_FSFLAGSI 0x105073 -#define MASK_FSFLAGSI 0xfff0707f -#define MATCH_FRRM 0x202073 -#define MASK_FRRM 0xfffff07f -#define MATCH_FSRM 0x201073 -#define MASK_FSRM 0xfff0707f -#define MATCH_FSRMI 0x205073 -#define MASK_FSRMI 0xfff0707f -#define MATCH_FSCSR 0x301073 -#define MASK_FSCSR 0xfff0707f -#define MATCH_FRCSR 0x302073 -#define MASK_FRCSR 0xfffff07f -#define MATCH_RDCYCLE 0xc0002073 -#define MASK_RDCYCLE 0xfffff07f -#define MATCH_RDTIME 0xc0102073 -#define MASK_RDTIME 0xfffff07f -#define MATCH_RDINSTRET 0xc0202073 -#define MASK_RDINSTRET 0xfffff07f -#define MATCH_RDCYCLEH 0xc8002073 -#define MASK_RDCYCLEH 0xfffff07f -#define MATCH_RDTIMEH 0xc8102073 -#define MASK_RDTIMEH 0xfffff07f -#define MATCH_RDINSTRETH 0xc8202073 -#define MASK_RDINSTRETH 0xfffff07f -#define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff -#define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FENCE_TSO 0x8330000f -#define MASK_FENCE_TSO 0xfff0707f -#define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_C_SRLI_RV32 0x8001 -#define MASK_C_SRLI_RV32 0xfc03 -#define MATCH_C_SRAI_RV32 0x8401 -#define MASK_C_SRAI_RV32 0xfc03 -#define MATCH_C_SLLI_RV32 0x2 -#define MASK_C_SLLI_RV32 0xf003 -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff -#define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff -#define MATCH_HLV_B 0x60004073 -#define MASK_HLV_B 0xfff0707f -#define MATCH_HLV_BU 0x60104073 -#define MASK_HLV_BU 0xfff0707f -#define MATCH_HLV_H 0x64004073 -#define MASK_HLV_H 0xfff0707f -#define MATCH_HLV_HU 0x64104073 -#define MASK_HLV_HU 0xfff0707f -#define MATCH_HLVX_HU 0x64304073 -#define MASK_HLVX_HU 0xfff0707f -#define MATCH_HLV_W 0x68004073 -#define MASK_HLV_W 0xfff0707f -#define MATCH_HLVX_WU 0x68304073 -#define MASK_HLVX_WU 0xfff0707f -#define MATCH_HSV_B 0x62004073 -#define MASK_HSV_B 0xfe007fff -#define MATCH_HSV_H 0x66004073 -#define MASK_HSV_H 0xfe007fff -#define MATCH_HSV_W 0x6a004073 -#define MASK_HSV_W 0xfe007fff -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_HLV_WU 0x68104073 -#define MASK_HLV_WU 0xfff0707f -#define MATCH_HLV_D 0x6c004073 -#define MASK_HLV_D 0xfff0707f -#define MATCH_HSV_D 0x6e004073 -#define MASK_HSV_D 0xfe007fff -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f -#define MATCH_VLE8_V 0x7 -#define MASK_VLE8_V 0x1df0707f -#define MATCH_VLE16_V 0x5007 -#define MASK_VLE16_V 0x1df0707f -#define MATCH_VLE32_V 0x6007 -#define MASK_VLE32_V 0x1df0707f -#define MATCH_VLE64_V 0x7007 -#define MASK_VLE64_V 0x1df0707f -#define MATCH_VLE128_V 0x10000007 -#define MASK_VLE128_V 0x1df0707f -#define MATCH_VLE256_V 0x10005007 -#define MASK_VLE256_V 0x1df0707f -#define MATCH_VLE512_V 0x10006007 -#define MASK_VLE512_V 0x1df0707f -#define MATCH_VLE1024_V 0x10007007 -#define MASK_VLE1024_V 0x1df0707f -#define MATCH_VSE8_V 0x27 -#define MASK_VSE8_V 0x1df0707f -#define MATCH_VSE16_V 0x5027 -#define MASK_VSE16_V 0x1df0707f -#define MATCH_VSE32_V 0x6027 -#define MASK_VSE32_V 0x1df0707f -#define MATCH_VSE64_V 0x7027 -#define MASK_VSE64_V 0x1df0707f -#define MATCH_VSE128_V 0x10000027 -#define MASK_VSE128_V 0x1df0707f -#define MATCH_VSE256_V 0x10005027 -#define MASK_VSE256_V 0x1df0707f -#define MATCH_VSE512_V 0x10006027 -#define MASK_VSE512_V 0x1df0707f -#define MATCH_VSE1024_V 0x10007027 -#define MASK_VSE1024_V 0x1df0707f -#define MATCH_VLSE8_V 0x8000007 -#define MASK_VLSE8_V 0x1c00707f -#define MATCH_VLSE16_V 0x8005007 -#define MASK_VLSE16_V 0x1c00707f -#define MATCH_VLSE32_V 0x8006007 -#define MASK_VLSE32_V 0x1c00707f -#define MATCH_VLSE64_V 0x8007007 -#define MASK_VLSE64_V 0x1c00707f -#define MATCH_VLSE128_V 0x18000007 -#define MASK_VLSE128_V 0x1c00707f -#define MATCH_VLSE256_V 0x18005007 -#define MASK_VLSE256_V 0x1c00707f -#define MATCH_VLSE512_V 0x18006007 -#define MASK_VLSE512_V 0x1c00707f -#define MATCH_VLSE1024_V 0x18007007 -#define MASK_VLSE1024_V 0x1c00707f -#define MATCH_VSSE8_V 0x8000027 -#define MASK_VSSE8_V 0x1c00707f -#define MATCH_VSSE16_V 0x8005027 -#define MASK_VSSE16_V 0x1c00707f -#define MATCH_VSSE32_V 0x8006027 -#define MASK_VSSE32_V 0x1c00707f -#define MATCH_VSSE64_V 0x8007027 -#define MASK_VSSE64_V 0x1c00707f -#define MATCH_VSSE128_V 0x18000027 -#define MASK_VSSE128_V 0x1c00707f -#define MATCH_VSSE256_V 0x18005027 -#define MASK_VSSE256_V 0x1c00707f -#define MATCH_VSSE512_V 0x18006027 -#define MASK_VSSE512_V 0x1c00707f -#define MATCH_VSSE1024_V 0x18007027 -#define MASK_VSSE1024_V 0x1c00707f -#define MATCH_VLXEI8_V 0xc000007 -#define MASK_VLXEI8_V 0x1c00707f -#define MATCH_VLXEI16_V 0xc005007 -#define MASK_VLXEI16_V 0x1c00707f -#define MATCH_VLXEI32_V 0xc006007 -#define MASK_VLXEI32_V 0x1c00707f -#define MATCH_VLXEI64_V 0xc007007 -#define MASK_VLXEI64_V 0x1c00707f -#define MATCH_VLXEI128_V 0x1c000007 -#define MASK_VLXEI128_V 0x1c00707f -#define MATCH_VLXEI256_V 0x1c005007 -#define MASK_VLXEI256_V 0x1c00707f -#define MATCH_VLXEI512_V 0x1c006007 -#define MASK_VLXEI512_V 0x1c00707f -#define MATCH_VLXEI1024_V 0x1c007007 -#define MASK_VLXEI1024_V 0x1c00707f -#define MATCH_VSXEI8_V 0xc000027 -#define MASK_VSXEI8_V 0x1c00707f -#define MATCH_VSXEI16_V 0xc005027 -#define MASK_VSXEI16_V 0x1c00707f -#define MATCH_VSXEI32_V 0xc006027 -#define MASK_VSXEI32_V 0x1c00707f -#define MATCH_VSXEI64_V 0xc007027 -#define MASK_VSXEI64_V 0x1c00707f -#define MATCH_VSXEI128_V 0x1c000027 -#define MASK_VSXEI128_V 0x1c00707f -#define MATCH_VSXEI256_V 0x1c005027 -#define MASK_VSXEI256_V 0x1c00707f -#define MATCH_VSXEI512_V 0x1c006027 -#define MASK_VSXEI512_V 0x1c00707f -#define MATCH_VSXEI1024_V 0x1c007027 -#define MASK_VSXEI1024_V 0x1c00707f -#define MATCH_VSUXEI8_V 0x4000027 -#define MASK_VSUXEI8_V 0x1c00707f -#define MATCH_VSUXEI16_V 0x4005027 -#define MASK_VSUXEI16_V 0x1c00707f -#define MATCH_VSUXEI32_V 0x4006027 -#define MASK_VSUXEI32_V 0x1c00707f -#define MATCH_VSUXEI64_V 0x4007027 -#define MASK_VSUXEI64_V 0x1c00707f -#define MATCH_VSUXEI128_V 0x14000027 -#define MASK_VSUXEI128_V 0x1c00707f -#define MATCH_VSUXEI256_V 0x14005027 -#define MASK_VSUXEI256_V 0x1c00707f -#define MATCH_VSUXEI512_V 0x14006027 -#define MASK_VSUXEI512_V 0x1c00707f -#define MATCH_VSUXEI1024_V 0x14007027 -#define MASK_VSUXEI1024_V 0x1c00707f -#define MATCH_VLE8FF_V 0x1000007 -#define MASK_VLE8FF_V 0x1df0707f -#define MATCH_VLE16FF_V 0x1005007 -#define MASK_VLE16FF_V 0x1df0707f -#define MATCH_VLE32FF_V 0x1006007 -#define MASK_VLE32FF_V 0x1df0707f -#define MATCH_VLE64FF_V 0x1007007 -#define MASK_VLE64FF_V 0x1df0707f -#define MATCH_VLE128FF_V 0x11000007 -#define MASK_VLE128FF_V 0x1df0707f -#define MATCH_VLE256FF_V 0x11005007 -#define MASK_VLE256FF_V 0x1df0707f -#define MATCH_VLE512FF_V 0x11006007 -#define MASK_VLE512FF_V 0x1df0707f -#define MATCH_VLE1024FF_V 0x11007007 -#define MASK_VLE1024FF_V 0x1df0707f -#define MATCH_VL1RE8_V 0x2800007 -#define MASK_VL1RE8_V 0xfff0707f -#define MATCH_VL1RE16_V 0x2805007 -#define MASK_VL1RE16_V 0xfff0707f -#define MATCH_VL1RE32_V 0x2806007 -#define MASK_VL1RE32_V 0xfff0707f -#define MATCH_VL1RE64_V 0x2807007 -#define MASK_VL1RE64_V 0xfff0707f -#define MATCH_VL2RE8_V 0x22800007 -#define MASK_VL2RE8_V 0xfff0707f -#define MATCH_VL2RE16_V 0x22805007 -#define MASK_VL2RE16_V 0xfff0707f -#define MATCH_VL2RE32_V 0x22806007 -#define MASK_VL2RE32_V 0xfff0707f -#define MATCH_VL2RE64_V 0x22807007 -#define MASK_VL2RE64_V 0xfff0707f -#define MATCH_VL4RE8_V 0x62800007 -#define MASK_VL4RE8_V 0xfff0707f -#define MATCH_VL4RE16_V 0x62805007 -#define MASK_VL4RE16_V 0xfff0707f -#define MATCH_VL4RE32_V 0x62806007 -#define MASK_VL4RE32_V 0xfff0707f -#define MATCH_VL4RE64_V 0x62807007 -#define MASK_VL4RE64_V 0xfff0707f -#define MATCH_VL8RE8_V 0xe2800007 -#define MASK_VL8RE8_V 0xfff0707f -#define MATCH_VL8RE16_V 0xe2805007 -#define MASK_VL8RE16_V 0xfff0707f -#define MATCH_VL8RE32_V 0xe2806007 -#define MASK_VL8RE32_V 0xfff0707f -#define MATCH_VL8RE64_V 0xe2807007 -#define MASK_VL8RE64_V 0xfff0707f -#define MATCH_VS1R_V 0x2800027 -#define MASK_VS1R_V 0xfff0707f -#define MATCH_VS2R_V 0x22800027 -#define MASK_VS2R_V 0xfff0707f -#define MATCH_VS4R_V 0x62800027 -#define MASK_VS4R_V 0xfff0707f -#define MATCH_VS8R_V 0xe2800027 -#define MASK_VS8R_V 0xfff0707f -#define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f -#define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f -#define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f -#define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f -#define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f -#define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f -#define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f -#define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f -#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f -#define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f -#define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f -#define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f -#define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f -#define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f -#define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f -#define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f -#define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f -#define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f -#define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f -#define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f -#define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f -#define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f -#define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f -#define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f -#define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f -#define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f -#define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f -#define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f -#define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f -#define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f -#define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f -#define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f -#define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f -#define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f -#define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f -#define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f -#define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f -#define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f -#define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f -#define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f -#define MATCH_VFREDSUM_VS 0x4001057 -#define MASK_VFREDSUM_VS 0xfc00707f -#define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f -#define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f -#define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f -#define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f -#define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f -#define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f -#define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f -#define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f -#define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f -#define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f -#define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f -#define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f -#define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f -#define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f -#define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f -#define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f -#define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f -#define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f -#define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f -#define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f -#define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f -#define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f -#define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f -#define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f -#define MATCH_VFCVT_XU_F_V 0x48001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_F_XU_V 0x48011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFCVT_F_X_V 0x48019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_XU_F_V 0x48041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_X_F_V 0x48049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_F_XU_V 0x48051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFWCVT_F_X_V 0x48059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f -#define MATCH_VFWCVT_F_F_V 0x48061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFNCVT_XU_F_W 0x48081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_X_F_W 0x48089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_F_XU_W 0x48091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f -#define MATCH_VFNCVT_F_X_W 0x48099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f -#define MATCH_VFNCVT_F_F_W 0x480a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f -#define MATCH_VFSQRT_V 0x4c001057 -#define MASK_VFSQRT_V 0xfc0ff07f -#define MATCH_VFRSQRTE7_V 0x4c021057 -#define MASK_VFRSQRTE7_V 0xfc0ff07f -#define MATCH_VFRECE7_V 0x4c029057 -#define MASK_VFRECE7_V 0xfc0ff07f -#define MATCH_VFCLASS_V 0x4c081057 -#define MASK_VFCLASS_V 0xfc0ff07f -#define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f -#define MATCH_VFWREDSUM_VS 0xc4001057 -#define MASK_VFWREDSUM_VS 0xfc00707f -#define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f -#define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f -#define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f -#define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f -#define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f -#define MATCH_VFDOT_VV 0xe4001057 -#define MASK_VFDOT_VV 0xfc00707f -#define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f -#define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f -#define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f -#define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f -#define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f -#define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f -#define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f -#define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f -#define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f -#define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f -#define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f -#define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f -#define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f -#define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f -#define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f -#define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f -#define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f -#define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfc00707f -#define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfc00707f -#define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f -#define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f -#define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f -#define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f -#define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f -#define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f -#define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f -#define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f -#define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f -#define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f -#define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f -#define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f -#define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f -#define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f -#define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f -#define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f -#define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f -#define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f -#define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f -#define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f -#define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f -#define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f -#define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f -#define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f -#define MATCH_VQMACCU_VX 0xf0004057 -#define MASK_VQMACCU_VX 0xfc00707f -#define MATCH_VQMACC_VX 0xf4004057 -#define MASK_VQMACC_VX 0xfc00707f -#define MATCH_VQMACCUS_VX 0xf8004057 -#define MASK_VQMACCUS_VX 0xfc00707f -#define MATCH_VQMACCSU_VX 0xfc004057 -#define MASK_VQMACCSU_VX 0xfc00707f -#define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f -#define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f -#define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f -#define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f -#define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f -#define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f -#define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f -#define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f -#define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f -#define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f -#define MATCH_VRGATHEREI16_VV 0x38000057 -#define MASK_VRGATHEREI16_VV 0xfc00707f -#define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfc00707f -#define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfc00707f -#define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f -#define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f -#define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f -#define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f -#define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f -#define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f -#define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f -#define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f -#define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f -#define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f -#define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f -#define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f -#define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f -#define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f -#define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f -#define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f -#define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f -#define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f -#define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f -#define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f -#define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f -#define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f -#define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f -#define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f -#define MATCH_VDOTU_VV 0xe0000057 -#define MASK_VDOTU_VV 0xfc00707f -#define MATCH_VDOT_VV 0xe4000057 -#define MASK_VDOT_VV 0xfc00707f -#define MATCH_VQMACCU_VV 0xf0000057 -#define MASK_VQMACCU_VV 0xfc00707f -#define MATCH_VQMACC_VV 0xf4000057 -#define MASK_VQMACC_VV 0xfc00707f -#define MATCH_VQMACCSU_VV 0xfc000057 -#define MASK_VQMACCSU_VV 0xfc00707f -#define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f -#define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f -#define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f -#define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f -#define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f -#define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f -#define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f -#define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f -#define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f -#define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfc00707f -#define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f -#define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f -#define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f -#define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f -#define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f -#define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f -#define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f -#define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f -#define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f -#define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f -#define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f -#define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f -#define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f -#define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f -#define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f -#define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f -#define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f -#define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f -#define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f -#define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f -#define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f -#define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f -#define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f -#define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f -#define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f -#define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f -#define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f -#define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f -#define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f -#define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f -#define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f -#define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f -#define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f -#define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f -#define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f -#define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f -#define MATCH_VZEXT_VF8 0x48012057 -#define MASK_VZEXT_VF8 0xfc0ff07f -#define MATCH_VSEXT_VF8 0x4801a057 -#define MASK_VSEXT_VF8 0xfc0ff07f -#define MATCH_VZEXT_VF4 0x48022057 -#define MASK_VZEXT_VF4 0xfc0ff07f -#define MATCH_VSEXT_VF4 0x4802a057 -#define MASK_VSEXT_VF4 0xfc0ff07f -#define MATCH_VZEXT_VF2 0x48032057 -#define MASK_VZEXT_VF2 0xfc0ff07f -#define MATCH_VSEXT_VF2 0x4803a057 -#define MASK_VSEXT_VF2 0xfc0ff07f -#define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f -#define MATCH_VMANDNOT_MM 0x60002057 -#define MASK_VMANDNOT_MM 0xfc00707f -#define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f -#define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f -#define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f -#define MATCH_VMORNOT_MM 0x70002057 -#define MASK_VMORNOT_MM 0xfc00707f -#define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f -#define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f -#define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f -#define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f -#define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f -#define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f -#define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f -#define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f -#define MATCH_VPOPC_M 0x40082057 -#define MASK_VPOPC_M 0xfc0ff07f -#define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f -#define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f -#define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f -#define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f -#define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f -#define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f -#define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f -#define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f -#define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f -#define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f -#define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f -#define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f -#define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f -#define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f -#define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f -#define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f -#define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f -#define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f -#define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f -#define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f -#define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f -#define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f -#define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f -#define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f -#define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f -#define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f -#define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f -#define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f -#define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f -#define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f -#define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f -#define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f -#define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f -#define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f -#define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f -#define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f -#define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f -#define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f -#define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f -#define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f -#define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f -#define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f -#define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f -#define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f -#define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f -#define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f -#define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f -#define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f -#define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f -#define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f -#define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f -#define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f -#define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f -#define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f -#define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f -#define MATCH_VAMOSWAPEI8_V 0x800002f -#define MASK_VAMOSWAPEI8_V 0xf800707f -#define MATCH_VAMOADDEI8_V 0x2f -#define MASK_VAMOADDEI8_V 0xf800707f -#define MATCH_VAMOXOREI8_V 0x2000002f -#define MASK_VAMOXOREI8_V 0xf800707f -#define MATCH_VAMOANDEI8_V 0x6000002f -#define MASK_VAMOANDEI8_V 0xf800707f -#define MATCH_VAMOOREI8_V 0x4000002f -#define MASK_VAMOOREI8_V 0xf800707f -#define MATCH_VAMOMINEI8_V 0x8000002f -#define MASK_VAMOMINEI8_V 0xf800707f -#define MATCH_VAMOMAXEI8_V 0xa000002f -#define MASK_VAMOMAXEI8_V 0xf800707f -#define MATCH_VAMOMINUEI8_V 0xc000002f -#define MASK_VAMOMINUEI8_V 0xf800707f -#define MATCH_VAMOMAXUEI8_V 0xe000002f -#define MASK_VAMOMAXUEI8_V 0xf800707f -#define MATCH_VAMOSWAPEI16_V 0x800502f -#define MASK_VAMOSWAPEI16_V 0xf800707f -#define MATCH_VAMOADDEI16_V 0x502f -#define MASK_VAMOADDEI16_V 0xf800707f -#define MATCH_VAMOXOREI16_V 0x2000502f -#define MASK_VAMOXOREI16_V 0xf800707f -#define MATCH_VAMOANDEI16_V 0x6000502f -#define MASK_VAMOANDEI16_V 0xf800707f -#define MATCH_VAMOOREI16_V 0x4000502f -#define MASK_VAMOOREI16_V 0xf800707f -#define MATCH_VAMOMINEI16_V 0x8000502f -#define MASK_VAMOMINEI16_V 0xf800707f -#define MATCH_VAMOMAXEI16_V 0xa000502f -#define MASK_VAMOMAXEI16_V 0xf800707f -#define MATCH_VAMOMINUEI16_V 0xc000502f -#define MASK_VAMOMINUEI16_V 0xf800707f -#define MATCH_VAMOMAXUEI16_V 0xe000502f -#define MASK_VAMOMAXUEI16_V 0xf800707f -#define MATCH_VAMOSWAPEI32_V 0x800602f -#define MASK_VAMOSWAPEI32_V 0xf800707f -#define MATCH_VAMOADDEI32_V 0x602f -#define MASK_VAMOADDEI32_V 0xf800707f -#define MATCH_VAMOXOREI32_V 0x2000602f -#define MASK_VAMOXOREI32_V 0xf800707f -#define MATCH_VAMOANDEI32_V 0x6000602f -#define MASK_VAMOANDEI32_V 0xf800707f -#define MATCH_VAMOOREI32_V 0x4000602f -#define MASK_VAMOOREI32_V 0xf800707f -#define MATCH_VAMOMINEI32_V 0x8000602f -#define MASK_VAMOMINEI32_V 0xf800707f -#define MATCH_VAMOMAXEI32_V 0xa000602f -#define MASK_VAMOMAXEI32_V 0xf800707f -#define MATCH_VAMOMINUEI32_V 0xc000602f -#define MASK_VAMOMINUEI32_V 0xf800707f -#define MATCH_VAMOMAXUEI32_V 0xe000602f -#define MASK_VAMOMAXUEI32_V 0xf800707f -#define MATCH_VAMOSWAPEI64_V 0x800702f -#define MASK_VAMOSWAPEI64_V 0xf800707f -#define MATCH_VAMOADDEI64_V 0x702f -#define MASK_VAMOADDEI64_V 0xf800707f -#define MATCH_VAMOXOREI64_V 0x2000702f -#define MASK_VAMOXOREI64_V 0xf800707f -#define MATCH_VAMOANDEI64_V 0x6000702f -#define MASK_VAMOANDEI64_V 0xf800707f -#define MATCH_VAMOOREI64_V 0x4000702f -#define MASK_VAMOOREI64_V 0xf800707f -#define MATCH_VAMOMINEI64_V 0x8000702f -#define MASK_VAMOMINEI64_V 0xf800707f -#define MATCH_VAMOMAXEI64_V 0xa000702f -#define MASK_VAMOMAXEI64_V 0xf800707f -#define MATCH_VAMOMINUEI64_V 0xc000702f -#define MASK_VAMOMINUEI64_V 0xf800707f -#define MATCH_VAMOMAXUEI64_V 0xe000702f -#define MASK_VAMOMAXUEI64_V 0xf800707f -#define MATCH_VMVNFR_V 0x9e003057 -#define MASK_VMVNFR_V 0xfe00707f -#define MATCH_VL1R_V 0x2800007 -#define MASK_VL1R_V 0xfff0707f -#define MATCH_VL2R_V 0x6805007 -#define MASK_VL2R_V 0xfff0707f -#define MATCH_VL4R_V 0xe806007 -#define MASK_VL4R_V 0xfff0707f -#define MATCH_VL8R_V 0x1e807007 -#define MASK_VL8R_V 0xfff0707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_LP_STARTI 0x7b -#define MASK_LP_STARTI 0xfff7f -#define MATCH_LP_ENDI 0x107b -#define MASK_LP_ENDI 0xfff7f -#define MATCH_LP_COUNT 0x207b -#define MASK_LP_COUNT 0xfff07f7f -#define MATCH_LP_COUNTI 0x307b -#define MASK_LP_COUNTI 0xfff7f -#define MATCH_LP_SETUP 0x407b -#define MASK_LP_SETUP 0x7f7f -#define MATCH_LP_SETUPI 0x507b -#define MASK_LP_SETUPI 0x7f7f -#define MATCH_P_LB_IRPOST 0xb -#define MASK_P_LB_IRPOST 0x707f -#define MATCH_P_LBU_IRPOST 0x400b -#define MASK_P_LBU_IRPOST 0x707f -#define MATCH_P_LH_IRPOST 0x100b -#define MASK_P_LH_IRPOST 0x707f -#define MATCH_P_LHU_IRPOST 0x500b -#define MASK_P_LHU_IRPOST 0x707f -#define MATCH_P_LW_IRPOST 0x200b -#define MASK_P_LW_IRPOST 0x707f -#define MATCH_P_LB_RRPOST 0x700b -#define MASK_P_LB_RRPOST 0xfe00707f -#define MATCH_P_LBU_RRPOST 0x4000700b -#define MASK_P_LBU_RRPOST 0xfe00707f -#define MATCH_P_LH_RRPOST 0x1000700b -#define MASK_P_LH_RRPOST 0xfe00707f -#define MATCH_P_LHU_RRPOST 0x5000700b -#define MASK_P_LHU_RRPOST 0xfe00707f -#define MATCH_P_LW_RRPOST 0x2000700b -#define MASK_P_LW_RRPOST 0xfe00707f -#define MATCH_P_LB_RR 0x7003 -#define MASK_P_LB_RR 0xfe00707f -#define MATCH_P_LBU_RR 0x40007003 -#define MASK_P_LBU_RR 0xfe00707f -#define MATCH_P_LH_RR 0x10007003 -#define MASK_P_LH_RR 0xfe00707f -#define MATCH_P_LHU_RR 0x50007003 -#define MASK_P_LHU_RR 0xfe00707f -#define MATCH_P_LW_RR 0x20007003 -#define MASK_P_LW_RR 0xfe00707f -#define MATCH_P_SB_IRPOST 0x2b -#define MASK_P_SB_IRPOST 0x707f -#define MATCH_P_SH_IRPOST 0x102b -#define MASK_P_SH_IRPOST 0x707f -#define MATCH_P_SW_IRPOST 0x202b -#define MASK_P_SW_IRPOST 0x707f -#define MATCH_P_SB_RRPOST 0x402b -#define MASK_P_SB_RRPOST 0xfe00707f -#define MATCH_P_SH_RRPOST 0x502b -#define MASK_P_SH_RRPOST 0xfe00707f -#define MATCH_P_SW_RRPOST 0x602b -#define MASK_P_SW_RRPOST 0xfe00707f -#define MATCH_P_SB_RR 0x4023 -#define MASK_P_SB_RR 0xfe00707f -#define MATCH_P_SH_RR 0x5023 -#define MASK_P_SH_RR 0xfe00707f -#define MATCH_P_SW_RR 0x6023 -#define MASK_P_SW_RR 0xfe00707f -#define MATCH_P_ABS 0x4000033 -#define MASK_P_ABS 0xfff0707f -#define MATCH_P_SLET 0x4002033 -#define MASK_P_SLET 0xfe00707f -#define MATCH_P_SLETU 0x4003033 -#define MASK_P_SLETU 0xfe00707f -#define MATCH_P_MIN 0x4004033 -#define MASK_P_MIN 0xfe00707f -#define MATCH_P_MINU 0x4005033 -#define MASK_P_MINU 0xfe00707f -#define MATCH_P_MAX 0x4006033 -#define MASK_P_MAX 0xfe00707f -#define MATCH_P_MAXU 0x4007033 -#define MASK_P_MAXU 0xfe00707f -#define MATCH_P_EXTHS 0x10004033 -#define MASK_P_EXTHS 0xfff0707f -#define MATCH_P_EXTHZ 0x10005033 -#define MASK_P_EXTHZ 0xfff0707f -#define MATCH_P_EXTBS 0x10006033 -#define MASK_P_EXTBS 0xfff0707f -#define MATCH_P_EXTBZ 0x10007033 -#define MASK_P_EXTBZ 0xfff0707f -#define MATCH_P_CLIP 0x14001033 -#define MASK_P_CLIP 0xfe00707f -#define MATCH_P_CLIPU 0x14002033 -#define MASK_P_CLIPU 0xfe00707f -#define MATCH_P_CLIPR 0x14005033 -#define MASK_P_CLIPR 0xfe00707f -#define MATCH_P_CLIPUR 0x14006033 -#define MASK_P_CLIPUR 0xfe00707f -#define MATCH_P_BEQIMM 0x2063 -#define MASK_P_BEQIMM 0x707f -#define MATCH_P_BNEIMM 0x3063 -#define MASK_P_BNEIMM 0x707f -#define MATCH_P_MAC 0x42000033 -#define MASK_P_MAC 0xfe00707f -#define MATCH_P_MSU 0x42001033 -#define MASK_P_MSU 0xfe00707f -#define MATCH_PV_ADD_H 0x57 -#define MASK_PV_ADD_H 0xfe00707f -#define MATCH_PV_ADD_SC_H 0x4057 -#define MASK_PV_ADD_SC_H 0xfe00707f -#define MATCH_PV_ADD_SCI_H 0x6057 -#define MASK_PV_ADD_SCI_H 0xfc00707f -#define MATCH_PV_ADD_B 0x1057 -#define MASK_PV_ADD_B 0xfe00707f -#define MATCH_PV_ADD_SC_B 0x5057 -#define MASK_PV_ADD_SC_B 0xfe00707f -#define MATCH_PV_ADD_SCI_B 0x7057 -#define MASK_PV_ADD_SCI_B 0xfc00707f -#define MATCH_PV_SUB_H 0x8000057 -#define MASK_PV_SUB_H 0xfe00707f -#define MATCH_PV_SUB_SC_H 0x8004057 -#define MASK_PV_SUB_SC_H 0xfe00707f -#define MATCH_PV_SUB_SCI_H 0x8006057 -#define MASK_PV_SUB_SCI_H 0xfc00707f -#define MATCH_PV_SUB_B 0x8001057 -#define MASK_PV_SUB_B 0xfe00707f -#define MATCH_PV_SUB_SC_B 0x8005057 -#define MASK_PV_SUB_SC_B 0xfe00707f -#define MATCH_PV_SUB_SCI_B 0x8007057 -#define MASK_PV_SUB_SCI_B 0xfc00707f -#define MATCH_PV_AVG_H 0x10000057 -#define MASK_PV_AVG_H 0xfe00707f -#define MATCH_PV_AVG_SC_H 0x10004057 -#define MASK_PV_AVG_SC_H 0xfe00707f -#define MATCH_PV_AVG_SCI_H 0x10006057 -#define MASK_PV_AVG_SCI_H 0xfc00707f -#define MATCH_PV_AVG_B 0x10001057 -#define MASK_PV_AVG_B 0xfe00707f -#define MATCH_PV_AVG_SC_B 0x10005057 -#define MASK_PV_AVG_SC_B 0xfe00707f -#define MATCH_PV_AVG_SCI_B 0x10007057 -#define MASK_PV_AVG_SCI_B 0xfc00707f -#define MATCH_PV_AVGU_H 0x18000057 -#define MASK_PV_AVGU_H 0xfe00707f -#define MATCH_PV_AVGU_SC_H 0x18004057 -#define MASK_PV_AVGU_SC_H 0xfe00707f -#define MATCH_PV_AVGU_SCI_H 0x18006057 -#define MASK_PV_AVGU_SCI_H 0xfc00707f -#define MATCH_PV_AVGU_B 0x18001057 -#define MASK_PV_AVGU_B 0xfe00707f -#define MATCH_PV_AVGU_SC_B 0x18005057 -#define MASK_PV_AVGU_SC_B 0xfe00707f -#define MATCH_PV_AVGU_SCI_B 0x18007057 -#define MASK_PV_AVGU_SCI_B 0xfc00707f -#define MATCH_PV_MIN_H 0x20000057 -#define MASK_PV_MIN_H 0xfe00707f -#define MATCH_PV_MIN_SC_H 0x20004057 -#define MASK_PV_MIN_SC_H 0xfe00707f -#define MATCH_PV_MIN_SCI_H 0x20006057 -#define MASK_PV_MIN_SCI_H 0xfc00707f -#define MATCH_PV_MIN_B 0x20001057 -#define MASK_PV_MIN_B 0xfe00707f -#define MATCH_PV_MIN_SC_B 0x20005057 -#define MASK_PV_MIN_SC_B 0xfe00707f -#define MATCH_PV_MIN_SCI_B 0x20007057 -#define MASK_PV_MIN_SCI_B 0xfc00707f -#define MATCH_PV_MINU_H 0x28000057 -#define MASK_PV_MINU_H 0xfe00707f -#define MATCH_PV_MINU_SC_H 0x28004057 -#define MASK_PV_MINU_SC_H 0xfe00707f -#define MATCH_PV_MINU_SCI_H 0x28006057 -#define MASK_PV_MINU_SCI_H 0xfc00707f -#define MATCH_PV_MINU_B 0x28001057 -#define MASK_PV_MINU_B 0xfe00707f -#define MATCH_PV_MINU_SC_B 0x28005057 -#define MASK_PV_MINU_SC_B 0xfe00707f -#define MATCH_PV_MINU_SCI_B 0x28007057 -#define MASK_PV_MINU_SCI_B 0xfc00707f -#define MATCH_PV_MAX_H 0x30000057 -#define MASK_PV_MAX_H 0xfe00707f -#define MATCH_PV_MAX_SC_H 0x30004057 -#define MASK_PV_MAX_SC_H 0xfe00707f -#define MATCH_PV_MAX_SCI_H 0x30006057 -#define MASK_PV_MAX_SCI_H 0xfc00707f -#define MATCH_PV_MAX_B 0x30001057 -#define MASK_PV_MAX_B 0xfe00707f -#define MATCH_PV_MAX_SC_B 0x30005057 -#define MASK_PV_MAX_SC_B 0xfe00707f -#define MATCH_PV_MAX_SCI_B 0x30007057 -#define MASK_PV_MAX_SCI_B 0xfc00707f -#define MATCH_PV_MAXU_H 0x38000057 -#define MASK_PV_MAXU_H 0xfe00707f -#define MATCH_PV_MAXU_SC_H 0x38004057 -#define MASK_PV_MAXU_SC_H 0xfe00707f -#define MATCH_PV_MAXU_SCI_H 0x38006057 -#define MASK_PV_MAXU_SCI_H 0xfc00707f -#define MATCH_PV_MAXU_B 0x38001057 -#define MASK_PV_MAXU_B 0xfe00707f -#define MATCH_PV_MAXU_SC_B 0x38005057 -#define MASK_PV_MAXU_SC_B 0xfe00707f -#define MATCH_PV_MAXU_SCI_B 0x38007057 -#define MASK_PV_MAXU_SCI_B 0xfc00707f -#define MATCH_PV_SRL_H 0x40000057 -#define MASK_PV_SRL_H 0xfe00707f -#define MATCH_PV_SRL_SC_H 0x40004057 -#define MASK_PV_SRL_SC_H 0xfe00707f -#define MATCH_PV_SRL_SCI_H 0x40006057 -#define MASK_PV_SRL_SCI_H 0xfc00707f -#define MATCH_PV_SRL_B 0x40001057 -#define MASK_PV_SRL_B 0xfe00707f -#define MATCH_PV_SRL_SC_B 0x40005057 -#define MASK_PV_SRL_SC_B 0xfe00707f -#define MATCH_PV_SRL_SCI_B 0x40007057 -#define MASK_PV_SRL_SCI_B 0xfc00707f -#define MATCH_PV_SRA_H 0x48000057 -#define MASK_PV_SRA_H 0xfe00707f -#define MATCH_PV_SRA_SC_H 0x48004057 -#define MASK_PV_SRA_SC_H 0xfe00707f -#define MATCH_PV_SRA_SCI_H 0x48006057 -#define MASK_PV_SRA_SCI_H 0xfc00707f -#define MATCH_PV_SRA_B 0x48001057 -#define MASK_PV_SRA_B 0xfe00707f -#define MATCH_PV_SRA_SC_B 0x48005057 -#define MASK_PV_SRA_SC_B 0xfe00707f -#define MATCH_PV_SRA_SCI_B 0x48007057 -#define MASK_PV_SRA_SCI_B 0xfc00707f -#define MATCH_PV_SLL_H 0x50000057 -#define MASK_PV_SLL_H 0xfe00707f -#define MATCH_PV_SLL_SC_H 0x50004057 -#define MASK_PV_SLL_SC_H 0xfe00707f -#define MATCH_PV_SLL_SCI_H 0x50006057 -#define MASK_PV_SLL_SCI_H 0xfc00707f -#define MATCH_PV_SLL_B 0x50001057 -#define MASK_PV_SLL_B 0xfe00707f -#define MATCH_PV_SLL_SC_B 0x50005057 -#define MASK_PV_SLL_SC_B 0xfe00707f -#define MATCH_PV_SLL_SCI_B 0x50007057 -#define MASK_PV_SLL_SCI_B 0xfc00707f -#define MATCH_PV_OR_H 0x58000057 -#define MASK_PV_OR_H 0xfe00707f -#define MATCH_PV_OR_SC_H 0x58004057 -#define MASK_PV_OR_SC_H 0xfe00707f -#define MATCH_PV_OR_SCI_H 0x58006057 -#define MASK_PV_OR_SCI_H 0xfc00707f -#define MATCH_PV_OR_B 0x58001057 -#define MASK_PV_OR_B 0xfe00707f -#define MATCH_PV_OR_SC_B 0x58005057 -#define MASK_PV_OR_SC_B 0xfe00707f -#define MATCH_PV_OR_SCI_B 0x58007057 -#define MASK_PV_OR_SCI_B 0xfc00707f -#define MATCH_PV_XOR_H 0x60000057 -#define MASK_PV_XOR_H 0xfe00707f -#define MATCH_PV_XOR_SC_H 0x60004057 -#define MASK_PV_XOR_SC_H 0xfe00707f -#define MATCH_PV_XOR_SCI_H 0x60006057 -#define MASK_PV_XOR_SCI_H 0xfc00707f -#define MATCH_PV_XOR_B 0x60001057 -#define MASK_PV_XOR_B 0xfe00707f -#define MATCH_PV_XOR_SC_B 0x60005057 -#define MASK_PV_XOR_SC_B 0xfe00707f -#define MATCH_PV_XOR_SCI_B 0x60007057 -#define MASK_PV_XOR_SCI_B 0xfc00707f -#define MATCH_PV_AND_H 0x68000057 -#define MASK_PV_AND_H 0xfe00707f -#define MATCH_PV_AND_SC_H 0x68004057 -#define MASK_PV_AND_SC_H 0xfe00707f -#define MATCH_PV_AND_SCI_H 0x68006057 -#define MASK_PV_AND_SCI_H 0xfc00707f -#define MATCH_PV_AND_B 0x68001057 -#define MASK_PV_AND_B 0xfe00707f -#define MATCH_PV_AND_SC_B 0x68005057 -#define MASK_PV_AND_SC_B 0xfe00707f -#define MATCH_PV_AND_SCI_B 0x68007057 -#define MASK_PV_AND_SCI_B 0xfc00707f -#define MATCH_PV_ABS_H 0x70000057 -#define MASK_PV_ABS_H 0xfff0707f -#define MATCH_PV_ABS_B 0x70001057 -#define MASK_PV_ABS_B 0xfff0707f -#define MATCH_PV_EXTRACT_H 0x78006057 -#define MASK_PV_EXTRACT_H 0xfc00707f -#define MATCH_PV_EXTRACT_B 0x78007057 -#define MASK_PV_EXTRACT_B 0xfc00707f -#define MATCH_PV_EXTRACTU_H 0x90006057 -#define MASK_PV_EXTRACTU_H 0xfc00707f -#define MATCH_PV_EXTRACTU_B 0x90007057 -#define MASK_PV_EXTRACTU_B 0xfc00707f -#define MATCH_PV_INSERT_H 0xb0006057 -#define MASK_PV_INSERT_H 0xfc00707f -#define MATCH_PV_INSERT_B 0xb0007057 -#define MASK_PV_INSERT_B 0xfc00707f -#define MATCH_PV_DOTUP_H 0x80000057 -#define MASK_PV_DOTUP_H 0xfe00707f -#define MATCH_PV_DOTUP_SC_H 0x80004057 -#define MASK_PV_DOTUP_SC_H 0xfe00707f -#define MATCH_PV_DOTUP_SCI_H 0x80006057 -#define MASK_PV_DOTUP_SCI_H 0xfc00707f -#define MATCH_PV_DOTUP_B 0x80001057 -#define MASK_PV_DOTUP_B 0xfe00707f -#define MATCH_PV_DOTUP_SC_B 0x80005057 -#define MASK_PV_DOTUP_SC_B 0xfe00707f -#define MATCH_PV_DOTUP_SCI_B 0x80007057 -#define MASK_PV_DOTUP_SCI_B 0xfc00707f -#define MATCH_PV_DOTUSP_H 0x88000057 -#define MASK_PV_DOTUSP_H 0xfe00707f -#define MATCH_PV_DOTUSP_SC_H 0x88004057 -#define MASK_PV_DOTUSP_SC_H 0xfe00707f -#define MATCH_PV_DOTUSP_SCI_H 0x88006057 -#define MASK_PV_DOTUSP_SCI_H 0xfc00707f -#define MATCH_PV_DOTUSP_B 0x88001057 -#define MASK_PV_DOTUSP_B 0xfe00707f -#define MATCH_PV_DOTUSP_SC_B 0x88005057 -#define MASK_PV_DOTUSP_SC_B 0xfe00707f -#define MATCH_PV_DOTUSP_SCI_B 0x88007057 -#define MASK_PV_DOTUSP_SCI_B 0xfc00707f -#define MATCH_PV_DOTSP_H 0x98000057 -#define MASK_PV_DOTSP_H 0xfe00707f -#define MATCH_PV_DOTSP_SC_H 0x98004057 -#define MASK_PV_DOTSP_SC_H 0xfe00707f -#define MATCH_PV_DOTSP_SCI_H 0x98006057 -#define MASK_PV_DOTSP_SCI_H 0xfc00707f -#define MATCH_PV_DOTSP_B 0x98001057 -#define MASK_PV_DOTSP_B 0xfe00707f -#define MATCH_PV_DOTSP_SC_B 0x98005057 -#define MASK_PV_DOTSP_SC_B 0xfe00707f -#define MATCH_PV_DOTSP_SCI_B 0x98007057 -#define MASK_PV_DOTSP_SCI_B 0xfc00707f -#define MATCH_PV_SDOTUP_H 0xa0000057 -#define MASK_PV_SDOTUP_H 0xfe00707f -#define MATCH_PV_SDOTUP_SC_H 0xa0004057 -#define MASK_PV_SDOTUP_SC_H 0xfe00707f -#define MATCH_PV_SDOTUP_SCI_H 0xa0006057 -#define MASK_PV_SDOTUP_SCI_H 0xfc00707f -#define MATCH_PV_SDOTUP_B 0xa0001057 -#define MASK_PV_SDOTUP_B 0xfe00707f -#define MATCH_PV_SDOTUP_SC_B 0xa0005057 -#define MASK_PV_SDOTUP_SC_B 0xfe00707f -#define MATCH_PV_SDOTUP_SCI_B 0xa0007057 -#define MASK_PV_SDOTUP_SCI_B 0xfc00707f -#define MATCH_PV_SDOTUSP_H 0xa8000057 -#define MASK_PV_SDOTUSP_H 0xfe00707f -#define MATCH_PV_SDOTUSP_SC_H 0xa8004057 -#define MASK_PV_SDOTUSP_SC_H 0xfe00707f -#define MATCH_PV_SDOTUSP_SCI_H 0xa8006057 -#define MASK_PV_SDOTUSP_SCI_H 0xfc00707f -#define MATCH_PV_SDOTUSP_B 0xa8001057 -#define MASK_PV_SDOTUSP_B 0xfe00707f -#define MATCH_PV_SDOTUSP_SC_B 0xa8005057 -#define MASK_PV_SDOTUSP_SC_B 0xfe00707f -#define MATCH_PV_SDOTUSP_SCI_B 0xa8007057 -#define MASK_PV_SDOTUSP_SCI_B 0xfc00707f -#define MATCH_PV_SDOTSP_H 0xb8000057 -#define MASK_PV_SDOTSP_H 0xfe00707f -#define MATCH_PV_SDOTSP_SC_H 0xb8004057 -#define MASK_PV_SDOTSP_SC_H 0xfe00707f -#define MATCH_PV_SDOTSP_SCI_H 0xb8006057 -#define MASK_PV_SDOTSP_SCI_H 0xfc00707f -#define MATCH_PV_SDOTSP_B 0xb8001057 -#define MASK_PV_SDOTSP_B 0xfe00707f -#define MATCH_PV_SDOTSP_SC_B 0xb8005057 -#define MASK_PV_SDOTSP_SC_B 0xfe00707f -#define MATCH_PV_SDOTSP_SCI_B 0xb8007057 -#define MASK_PV_SDOTSP_SCI_B 0xfc00707f -#define MATCH_PV_SHUFFLE2_H 0xc8000057 -#define MASK_PV_SHUFFLE2_H 0xfe00707f -#define MATCH_PV_SHUFFLE2_B 0xc8001057 -#define MASK_PV_SHUFFLE2_B 0xfe00707f -#define MATCH_FLAH 0x1007 -#define MASK_FLAH 0x707f -#define MATCH_FSAH 0x1027 -#define MASK_FSAH 0x707f -#define MATCH_FMADD_AH 0x4005043 -#define MASK_FMADD_AH 0x600707f -#define MATCH_FMSUB_AH 0x4005047 -#define MASK_FMSUB_AH 0x600707f -#define MATCH_FNMSUB_AH 0x400504b -#define MASK_FNMSUB_AH 0x600707f -#define MATCH_FNMADD_AH 0x400504f -#define MASK_FNMADD_AH 0x600707f -#define MATCH_FADD_AH 0x4005053 -#define MASK_FADD_AH 0xfe00707f -#define MATCH_FSUB_AH 0xc005053 -#define MASK_FSUB_AH 0xfe00707f -#define MATCH_FMUL_AH 0x14005053 -#define MASK_FMUL_AH 0xfe00707f -#define MATCH_FDIV_AH 0x1c005053 -#define MASK_FDIV_AH 0xfe00707f -#define MATCH_FSQRT_AH 0x5c005053 -#define MASK_FSQRT_AH 0xfff0707f -#define MATCH_FSGNJ_AH 0x24004053 -#define MASK_FSGNJ_AH 0xfe00707f -#define MATCH_FSGNJN_AH 0x24005053 -#define MASK_FSGNJN_AH 0xfe00707f -#define MATCH_FSGNJX_AH 0x24006053 -#define MASK_FSGNJX_AH 0xfe00707f -#define MATCH_FMIN_AH 0x2c004053 -#define MASK_FMIN_AH 0xfe00707f -#define MATCH_FMAX_AH 0x2c005053 -#define MASK_FMAX_AH 0xfe00707f -#define MATCH_FEQ_AH 0xa4006053 -#define MASK_FEQ_AH 0xfe00707f -#define MATCH_FLT_AH 0xa4005053 -#define MASK_FLT_AH 0xfe00707f -#define MATCH_FLE_AH 0xa4004053 -#define MASK_FLE_AH 0xfe00707f -#define MATCH_FCVT_W_AH 0xc4005053 -#define MASK_FCVT_W_AH 0xfff0707f -#define MATCH_FCVT_WU_AH 0xc4105053 -#define MASK_FCVT_WU_AH 0xfff0707f -#define MATCH_FCVT_AH_W 0xd4005053 -#define MASK_FCVT_AH_W 0xfff0707f -#define MATCH_FCVT_AH_WU 0xd4105053 -#define MASK_FCVT_AH_WU 0xfff0707f -#define MATCH_FMV_X_AH 0xe4004053 -#define MASK_FMV_X_AH 0xfff0707f -#define MATCH_FCLASS_AH 0xe4005053 -#define MASK_FCLASS_AH 0xfff0707f -#define MATCH_FMV_AH_X 0xf4004053 -#define MASK_FMV_AH_X 0xfff0707f -#define MATCH_FCVT_L_AH 0xc4205053 -#define MASK_FCVT_L_AH 0xfff0707f -#define MATCH_FCVT_LU_AH 0xc4305053 -#define MASK_FCVT_LU_AH 0xfff0707f -#define MATCH_FCVT_AH_L 0xd4205053 -#define MASK_FCVT_AH_L 0xfff0707f -#define MATCH_FCVT_AH_LU 0xd4305053 -#define MASK_FCVT_AH_LU 0xfff0707f -#define MATCH_FCVT_S_AH 0x40600053 -#define MASK_FCVT_S_AH 0xfff0707f -#define MATCH_FCVT_AH_S 0x44005053 -#define MASK_FCVT_AH_S 0xfff0707f -#define MATCH_FCVT_D_AH 0x42600053 -#define MASK_FCVT_D_AH 0xfff0707f -#define MATCH_FCVT_AH_D 0x44105053 -#define MASK_FCVT_AH_D 0xfff0707f -#define MATCH_FCVT_H_AH 0x44600053 -#define MASK_FCVT_H_AH 0xfff0007f -#define MATCH_FCVT_AH_H 0x44205053 -#define MASK_FCVT_AH_H 0xfff0707f -#define MATCH_FLB 0x7 -#define MASK_FLB 0x707f -#define MATCH_FSB 0x27 -#define MASK_FSB 0x707f -#define MATCH_FMADD_B 0x6000043 -#define MASK_FMADD_B 0x600007f -#define MATCH_FMSUB_B 0x6000047 -#define MASK_FMSUB_B 0x600007f -#define MATCH_FNMSUB_B 0x600004b -#define MASK_FNMSUB_B 0x600007f -#define MATCH_FNMADD_B 0x600004f -#define MASK_FNMADD_B 0x600007f -#define MATCH_FADD_B 0x6000053 -#define MASK_FADD_B 0xfe00007f -#define MATCH_FSUB_B 0xe000053 -#define MASK_FSUB_B 0xfe00007f -#define MATCH_FMUL_B 0x16000053 -#define MASK_FMUL_B 0xfe00007f -#define MATCH_FDIV_B 0x1e000053 -#define MASK_FDIV_B 0xfe00007f -#define MATCH_FSQRT_B 0x5e000053 -#define MASK_FSQRT_B 0xfff0007f -#define MATCH_FSGNJ_B 0x26000053 -#define MASK_FSGNJ_B 0xfe00707f -#define MATCH_FSGNJN_B 0x26001053 -#define MASK_FSGNJN_B 0xfe00707f -#define MATCH_FSGNJX_B 0x26002053 -#define MASK_FSGNJX_B 0xfe00707f -#define MATCH_FMIN_B 0x2e000053 -#define MASK_FMIN_B 0xfe00707f -#define MATCH_FMAX_B 0x2e001053 -#define MASK_FMAX_B 0xfe00707f -#define MATCH_FEQ_B 0xa6002053 -#define MASK_FEQ_B 0xfe00707f -#define MATCH_FLT_B 0xa6001053 -#define MASK_FLT_B 0xfe00707f -#define MATCH_FLE_B 0xa6000053 -#define MASK_FLE_B 0xfe00707f -#define MATCH_FCVT_W_B 0xc6000053 -#define MASK_FCVT_W_B 0xfff0007f -#define MATCH_FCVT_WU_B 0xc6100053 -#define MASK_FCVT_WU_B 0xfff0007f -#define MATCH_FCVT_B_W 0xd6000053 -#define MASK_FCVT_B_W 0xfff0007f -#define MATCH_FCVT_B_WU 0xd6100053 -#define MASK_FCVT_B_WU 0xfff0007f -#define MATCH_FMV_X_B 0xe6000053 -#define MASK_FMV_X_B 0xfff0707f -#define MATCH_FCLASS_B 0xe6001053 -#define MASK_FCLASS_B 0xfff0707f -#define MATCH_FMV_B_X 0xf6000053 -#define MASK_FMV_B_X 0xfff0707f -#define MATCH_FCVT_L_B 0xc6200053 -#define MASK_FCVT_L_B 0xfff0007f -#define MATCH_FCVT_LU_B 0xc6300053 -#define MASK_FCVT_LU_B 0xfff0007f -#define MATCH_FCVT_B_L 0xd6200053 -#define MASK_FCVT_B_L 0xfff0007f -#define MATCH_FCVT_B_LU 0xd6300053 -#define MASK_FCVT_B_LU 0xfff0007f -#define MATCH_FCVT_S_B 0x40300053 -#define MASK_FCVT_S_B 0xfff0707f -#define MATCH_FCVT_B_S 0x46000053 -#define MASK_FCVT_B_S 0xfff0007f -#define MATCH_FCVT_D_B 0x42300053 -#define MASK_FCVT_D_B 0xfff0707f -#define MATCH_FCVT_B_D 0x46100053 -#define MASK_FCVT_B_D 0xfff0007f -#define MATCH_FCVT_H_B 0x44300053 -#define MASK_FCVT_H_B 0xfff0707f -#define MATCH_FCVT_B_H 0x46200053 -#define MASK_FCVT_B_H 0xfff0007f -#define MATCH_FCVT_AH_B 0x44305053 -#define MASK_FCVT_AH_B 0xfff0707f -#define MATCH_FCVT_B_AH 0x46600053 -#define MASK_FCVT_B_AH 0xfff0007f -#define MATCH_VFADD_S 0x82000033 -#define MASK_VFADD_S 0xfe00707f -#define MATCH_VFADD_R_S 0x82004033 -#define MASK_VFADD_R_S 0xfe00707f -#define MATCH_VFSUB_S 0x84000033 -#define MASK_VFSUB_S 0xfe00707f -#define MATCH_VFSUB_R_S 0x84004033 -#define MASK_VFSUB_R_S 0xfe00707f -#define MATCH_VFMUL_S 0x86000033 -#define MASK_VFMUL_S 0xfe00707f -#define MATCH_VFMUL_R_S 0x86004033 -#define MASK_VFMUL_R_S 0xfe00707f -#define MATCH_VFDIV_S 0x88000033 -#define MASK_VFDIV_S 0xfe00707f -#define MATCH_VFDIV_R_S 0x88004033 -#define MASK_VFDIV_R_S 0xfe00707f -#define MATCH_VFMIN_S 0x8a000033 -#define MASK_VFMIN_S 0xfe00707f -#define MATCH_VFMIN_R_S 0x8a004033 -#define MASK_VFMIN_R_S 0xfe00707f -#define MATCH_VFMAX_S 0x8c000033 -#define MASK_VFMAX_S 0xfe00707f -#define MATCH_VFMAX_R_S 0x8c004033 -#define MASK_VFMAX_R_S 0xfe00707f -#define MATCH_VFSQRT_S 0x8e000033 -#define MASK_VFSQRT_S 0xfff0707f -#define MATCH_VFMAC_S 0x90000033 -#define MASK_VFMAC_S 0xfe00707f -#define MATCH_VFMAC_R_S 0x90004033 -#define MASK_VFMAC_R_S 0xfe00707f -#define MATCH_VFMRE_S 0x92000033 -#define MASK_VFMRE_S 0xfe00707f -#define MATCH_VFMRE_R_S 0x92004033 -#define MASK_VFMRE_R_S 0xfe00707f -#define MATCH_VFCLASS_S 0x98100033 -#define MASK_VFCLASS_S 0xfff0707f -#define MATCH_VFSGNJ_S 0x9a000033 -#define MASK_VFSGNJ_S 0xfe00707f -#define MATCH_VFSGNJ_R_S 0x9a004033 -#define MASK_VFSGNJ_R_S 0xfe00707f -#define MATCH_VFSGNJN_S 0x9c000033 -#define MASK_VFSGNJN_S 0xfe00707f -#define MATCH_VFSGNJN_R_S 0x9c004033 -#define MASK_VFSGNJN_R_S 0xfe00707f -#define MATCH_VFSGNJX_S 0x9e000033 -#define MASK_VFSGNJX_S 0xfe00707f -#define MATCH_VFSGNJX_R_S 0x9e004033 -#define MASK_VFSGNJX_R_S 0xfe00707f -#define MATCH_VFEQ_S 0xa0000033 -#define MASK_VFEQ_S 0xfe00707f -#define MATCH_VFEQ_R_S 0xa0004033 -#define MASK_VFEQ_R_S 0xfe00707f -#define MATCH_VFNE_S 0xa2000033 -#define MASK_VFNE_S 0xfe00707f -#define MATCH_VFNE_R_S 0xa2004033 -#define MASK_VFNE_R_S 0xfe00707f -#define MATCH_VFLT_S 0xa4000033 -#define MASK_VFLT_S 0xfe00707f -#define MATCH_VFLT_R_S 0xa4004033 -#define MASK_VFLT_R_S 0xfe00707f -#define MATCH_VFGE_S 0xa6000033 -#define MASK_VFGE_S 0xfe00707f -#define MATCH_VFGE_R_S 0xa6004033 -#define MASK_VFGE_R_S 0xfe00707f -#define MATCH_VFLE_S 0xa8000033 -#define MASK_VFLE_S 0xfe00707f -#define MATCH_VFLE_R_S 0xa8004033 -#define MASK_VFLE_R_S 0xfe00707f -#define MATCH_VFGT_S 0xaa000033 -#define MASK_VFGT_S 0xfe00707f -#define MATCH_VFGT_R_S 0xaa004033 -#define MASK_VFGT_R_S 0xfe00707f -#define MATCH_VFMV_X_S 0x98000033 -#define MASK_VFMV_X_S 0xfff0707f -#define MATCH_VFMV_S_X 0x98004033 -#define MASK_VFMV_S_X 0xfff0707f -#define MATCH_VFCVT_X_S 0x98200033 -#define MASK_VFCVT_X_S 0xfff0707f -#define MATCH_VFCVT_XU_S 0x98204033 -#define MASK_VFCVT_XU_S 0xfff0707f -#define MATCH_VFCVT_S_X 0x98300033 -#define MASK_VFCVT_S_X 0xfff0707f -#define MATCH_VFCVT_S_XU 0x98304033 -#define MASK_VFCVT_S_XU 0xfff0707f -#define MATCH_VFCPKA_S_S 0xb0000033 -#define MASK_VFCPKA_S_S 0xfe00707f -#define MATCH_VFCPKB_S_S 0xb0004033 -#define MASK_VFCPKB_S_S 0xfe00707f -#define MATCH_VFCPKC_S_S 0xb2000033 -#define MASK_VFCPKC_S_S 0xfe00707f -#define MATCH_VFCPKD_S_S 0xb2004033 -#define MASK_VFCPKD_S_S 0xfe00707f -#define MATCH_VFCPKA_S_D 0xb4000033 -#define MASK_VFCPKA_S_D 0xfe00707f -#define MATCH_VFCPKB_S_D 0xb4004033 -#define MASK_VFCPKB_S_D 0xfe00707f -#define MATCH_VFCPKC_S_D 0xb6000033 -#define MASK_VFCPKC_S_D 0xfe00707f -#define MATCH_VFCPKD_S_D 0xb6004033 -#define MASK_VFCPKD_S_D 0xfe00707f -#define MATCH_VFADD_H 0x82002033 -#define MASK_VFADD_H 0xfe00707f -#define MATCH_VFADD_R_H 0x82006033 -#define MASK_VFADD_R_H 0xfe00707f -#define MATCH_VFSUB_H 0x84002033 -#define MASK_VFSUB_H 0xfe00707f -#define MATCH_VFSUB_R_H 0x84006033 -#define MASK_VFSUB_R_H 0xfe00707f -#define MATCH_VFMUL_H 0x86002033 -#define MASK_VFMUL_H 0xfe00707f -#define MATCH_VFMUL_R_H 0x86006033 -#define MASK_VFMUL_R_H 0xfe00707f -#define MATCH_VFDIV_H 0x88002033 -#define MASK_VFDIV_H 0xfe00707f -#define MATCH_VFDIV_R_H 0x88006033 -#define MASK_VFDIV_R_H 0xfe00707f -#define MATCH_VFMIN_H 0x8a002033 -#define MASK_VFMIN_H 0xfe00707f -#define MATCH_VFMIN_R_H 0x8a006033 -#define MASK_VFMIN_R_H 0xfe00707f -#define MATCH_VFMAX_H 0x8c002033 -#define MASK_VFMAX_H 0xfe00707f -#define MATCH_VFMAX_R_H 0x8c006033 -#define MASK_VFMAX_R_H 0xfe00707f -#define MATCH_VFSQRT_H 0x8e002033 -#define MASK_VFSQRT_H 0xfff0707f -#define MATCH_VFMAC_H 0x90002033 -#define MASK_VFMAC_H 0xfe00707f -#define MATCH_VFMAC_R_H 0x90006033 -#define MASK_VFMAC_R_H 0xfe00707f -#define MATCH_VFMRE_H 0x92002033 -#define MASK_VFMRE_H 0xfe00707f -#define MATCH_VFMRE_R_H 0x92006033 -#define MASK_VFMRE_R_H 0xfe00707f -#define MATCH_VFCLASS_H 0x98102033 -#define MASK_VFCLASS_H 0xfff0707f -#define MATCH_VFSGNJ_H 0x9a002033 -#define MASK_VFSGNJ_H 0xfe00707f -#define MATCH_VFSGNJ_R_H 0x9a006033 -#define MASK_VFSGNJ_R_H 0xfe00707f -#define MATCH_VFSGNJN_H 0x9c002033 -#define MASK_VFSGNJN_H 0xfe00707f -#define MATCH_VFSGNJN_R_H 0x9c006033 -#define MASK_VFSGNJN_R_H 0xfe00707f -#define MATCH_VFSGNJX_H 0x9e002033 -#define MASK_VFSGNJX_H 0xfe00707f -#define MATCH_VFSGNJX_R_H 0x9e006033 -#define MASK_VFSGNJX_R_H 0xfe00707f -#define MATCH_VFEQ_H 0xa0002033 -#define MASK_VFEQ_H 0xfe00707f -#define MATCH_VFEQ_R_H 0xa0006033 -#define MASK_VFEQ_R_H 0xfe00707f -#define MATCH_VFNE_H 0xa2002033 -#define MASK_VFNE_H 0xfe00707f -#define MATCH_VFNE_R_H 0xa2006033 -#define MASK_VFNE_R_H 0xfe00707f -#define MATCH_VFLT_H 0xa4002033 -#define MASK_VFLT_H 0xfe00707f -#define MATCH_VFLT_R_H 0xa4006033 -#define MASK_VFLT_R_H 0xfe00707f -#define MATCH_VFGE_H 0xa6002033 -#define MASK_VFGE_H 0xfe00707f -#define MATCH_VFGE_R_H 0xa6006033 -#define MASK_VFGE_R_H 0xfe00707f -#define MATCH_VFLE_H 0xa8002033 -#define MASK_VFLE_H 0xfe00707f -#define MATCH_VFLE_R_H 0xa8006033 -#define MASK_VFLE_R_H 0xfe00707f -#define MATCH_VFGT_H 0xaa002033 -#define MASK_VFGT_H 0xfe00707f -#define MATCH_VFGT_R_H 0xaa006033 -#define MASK_VFGT_R_H 0xfe00707f -#define MATCH_VFMV_X_H 0x98002033 -#define MASK_VFMV_X_H 0xfff0707f -#define MATCH_VFMV_H_X 0x98006033 -#define MASK_VFMV_H_X 0xfff0707f -#define MATCH_VFCVT_X_H 0x98202033 -#define MASK_VFCVT_X_H 0xfff0707f -#define MATCH_VFCVT_XU_H 0x98206033 -#define MASK_VFCVT_XU_H 0xfff0707f -#define MATCH_VFCVT_H_X 0x98302033 -#define MASK_VFCVT_H_X 0xfff0707f -#define MATCH_VFCVT_H_XU 0x98306033 -#define MASK_VFCVT_H_XU 0xfff0707f -#define MATCH_VFCPKA_H_S 0xb0002033 -#define MASK_VFCPKA_H_S 0xfe00707f -#define MATCH_VFCPKB_H_S 0xb0006033 -#define MASK_VFCPKB_H_S 0xfe00707f -#define MATCH_VFCPKC_H_S 0xb2002033 -#define MASK_VFCPKC_H_S 0xfe00707f -#define MATCH_VFCPKD_H_S 0xb2006033 -#define MASK_VFCPKD_H_S 0xfe00707f -#define MATCH_VFCPKA_H_D 0xb4002033 -#define MASK_VFCPKA_H_D 0xfe00707f -#define MATCH_VFCPKB_H_D 0xb4006033 -#define MASK_VFCPKB_H_D 0xfe00707f -#define MATCH_VFCPKC_H_D 0xb6002033 -#define MASK_VFCPKC_H_D 0xfe00707f -#define MATCH_VFCPKD_H_D 0xb6006033 -#define MASK_VFCPKD_H_D 0xfe00707f -#define MATCH_VFCVT_S_H 0x98600033 -#define MASK_VFCVT_S_H 0xfff0707f -#define MATCH_VFCVTU_S_H 0x98604033 -#define MASK_VFCVTU_S_H 0xfff0707f -#define MATCH_VFCVT_H_S 0x98402033 -#define MASK_VFCVT_H_S 0xfff0707f -#define MATCH_VFCVTU_H_S 0x98406033 -#define MASK_VFCVTU_H_S 0xfff0707f -#define MATCH_VFADD_AH 0x82001033 -#define MASK_VFADD_AH 0xfe00707f -#define MATCH_VFADD_R_AH 0x82005033 -#define MASK_VFADD_R_AH 0xfe00707f -#define MATCH_VFSUB_AH 0x84001033 -#define MASK_VFSUB_AH 0xfe00707f -#define MATCH_VFSUB_R_AH 0x84005033 -#define MASK_VFSUB_R_AH 0xfe00707f -#define MATCH_VFMUL_AH 0x86001033 -#define MASK_VFMUL_AH 0xfe00707f -#define MATCH_VFMUL_R_AH 0x86005033 -#define MASK_VFMUL_R_AH 0xfe00707f -#define MATCH_VFDIV_AH 0x88001033 -#define MASK_VFDIV_AH 0xfe00707f -#define MATCH_VFDIV_R_AH 0x88005033 -#define MASK_VFDIV_R_AH 0xfe00707f -#define MATCH_VFMIN_AH 0x8a001033 -#define MASK_VFMIN_AH 0xfe00707f -#define MATCH_VFMIN_R_AH 0x8a005033 -#define MASK_VFMIN_R_AH 0xfe00707f -#define MATCH_VFMAX_AH 0x8c001033 -#define MASK_VFMAX_AH 0xfe00707f -#define MATCH_VFMAX_R_AH 0x8c005033 -#define MASK_VFMAX_R_AH 0xfe00707f -#define MATCH_VFSQRT_AH 0x8e001033 -#define MASK_VFSQRT_AH 0xfff0707f -#define MATCH_VFMAC_AH 0x90001033 -#define MASK_VFMAC_AH 0xfe00707f -#define MATCH_VFMAC_R_AH 0x90005033 -#define MASK_VFMAC_R_AH 0xfe00707f -#define MATCH_VFMRE_AH 0x92001033 -#define MASK_VFMRE_AH 0xfe00707f -#define MATCH_VFMRE_R_AH 0x92005033 -#define MASK_VFMRE_R_AH 0xfe00707f -#define MATCH_VFCLASS_AH 0x98101033 -#define MASK_VFCLASS_AH 0xfff0707f -#define MATCH_VFSGNJ_AH 0x9a001033 -#define MASK_VFSGNJ_AH 0xfe00707f -#define MATCH_VFSGNJ_R_AH 0x9a005033 -#define MASK_VFSGNJ_R_AH 0xfe00707f -#define MATCH_VFSGNJN_AH 0x9c001033 -#define MASK_VFSGNJN_AH 0xfe00707f -#define MATCH_VFSGNJN_R_AH 0x9c005033 -#define MASK_VFSGNJN_R_AH 0xfe00707f -#define MATCH_VFSGNJX_AH 0x9e001033 -#define MASK_VFSGNJX_AH 0xfe00707f -#define MATCH_VFSGNJX_R_AH 0x9e005033 -#define MASK_VFSGNJX_R_AH 0xfe00707f -#define MATCH_VFEQ_AH 0xa0001033 -#define MASK_VFEQ_AH 0xfe00707f -#define MATCH_VFEQ_R_AH 0xa0005033 -#define MASK_VFEQ_R_AH 0xfe00707f -#define MATCH_VFNE_AH 0xa2001033 -#define MASK_VFNE_AH 0xfe00707f -#define MATCH_VFNE_R_AH 0xa2005033 -#define MASK_VFNE_R_AH 0xfe00707f -#define MATCH_VFLT_AH 0xa4001033 -#define MASK_VFLT_AH 0xfe00707f -#define MATCH_VFLT_R_AH 0xa4005033 -#define MASK_VFLT_R_AH 0xfe00707f -#define MATCH_VFGE_AH 0xa6001033 -#define MASK_VFGE_AH 0xfe00707f -#define MATCH_VFGE_R_AH 0xa6005033 -#define MASK_VFGE_R_AH 0xfe00707f -#define MATCH_VFLE_AH 0xa8001033 -#define MASK_VFLE_AH 0xfe00707f -#define MATCH_VFLE_R_AH 0xa8005033 -#define MASK_VFLE_R_AH 0xfe00707f -#define MATCH_VFGT_AH 0xaa001033 -#define MASK_VFGT_AH 0xfe00707f -#define MATCH_VFGT_R_AH 0xaa005033 -#define MASK_VFGT_R_AH 0xfe00707f -#define MATCH_VFMV_X_AH 0x98001033 -#define MASK_VFMV_X_AH 0xfff0707f -#define MATCH_VFMV_AH_X 0x98005033 -#define MASK_VFMV_AH_X 0xfff0707f -#define MATCH_VFCVT_X_AH 0x98201033 -#define MASK_VFCVT_X_AH 0xfff0707f -#define MATCH_VFCVT_XU_AH 0x98205033 -#define MASK_VFCVT_XU_AH 0xfff0707f -#define MATCH_VFCVT_AH_X 0x98301033 -#define MASK_VFCVT_AH_X 0xfff0707f -#define MATCH_VFCVT_AH_XU 0x98305033 -#define MASK_VFCVT_AH_XU 0xfff0707f -#define MATCH_VFCPKA_AH_S 0xb0001033 -#define MASK_VFCPKA_AH_S 0xfe00707f -#define MATCH_VFCPKB_AH_S 0xb0005033 -#define MASK_VFCPKB_AH_S 0xfe00707f -#define MATCH_VFCPKC_AH_S 0xb2001033 -#define MASK_VFCPKC_AH_S 0xfe00707f -#define MATCH_VFCPKD_AH_S 0xb2005033 -#define MASK_VFCPKD_AH_S 0xfe00707f -#define MATCH_VFCPKA_AH_D 0xb4001033 -#define MASK_VFCPKA_AH_D 0xfe00707f -#define MATCH_VFCPKB_AH_D 0xb4005033 -#define MASK_VFCPKB_AH_D 0xfe00707f -#define MATCH_VFCPKC_AH_D 0xb6001033 -#define MASK_VFCPKC_AH_D 0xfe00707f -#define MATCH_VFCPKD_AH_D 0xb6005033 -#define MASK_VFCPKD_AH_D 0xfe00707f -#define MATCH_VFCVT_S_AH 0x98500033 -#define MASK_VFCVT_S_AH 0xfff0707f -#define MATCH_VFCVTU_S_AH 0x98504033 -#define MASK_VFCVTU_S_AH 0xfff0707f -#define MATCH_VFCVT_AH_S 0x98401033 -#define MASK_VFCVT_AH_S 0xfff0707f -#define MATCH_VFCVTU_AH_S 0x98405033 -#define MASK_VFCVTU_AH_S 0xfff0707f -#define MATCH_VFCVT_H_AH 0x98502033 -#define MASK_VFCVT_H_AH 0xfff0707f -#define MATCH_VFCVTU_H_AH 0x98506033 -#define MASK_VFCVTU_H_AH 0xfff0707f -#define MATCH_VFCVT_AH_H 0x98601033 -#define MASK_VFCVT_AH_H 0xfff0707f -#define MATCH_VFCVTU_AH_H 0x98605033 -#define MASK_VFCVTU_AH_H 0xfff0707f -#define MATCH_VFADD_B 0x82003033 -#define MASK_VFADD_B 0xfe00707f -#define MATCH_VFADD_R_B 0x82007033 -#define MASK_VFADD_R_B 0xfe00707f -#define MATCH_VFSUB_B 0x84003033 -#define MASK_VFSUB_B 0xfe00707f -#define MATCH_VFSUB_R_B 0x84007033 -#define MASK_VFSUB_R_B 0xfe00707f -#define MATCH_VFMUL_B 0x86003033 -#define MASK_VFMUL_B 0xfe00707f -#define MATCH_VFMUL_R_B 0x86007033 -#define MASK_VFMUL_R_B 0xfe00707f -#define MATCH_VFDIV_B 0x88003033 -#define MASK_VFDIV_B 0xfe00707f -#define MATCH_VFDIV_R_B 0x88007033 -#define MASK_VFDIV_R_B 0xfe00707f -#define MATCH_VFMIN_B 0x8a003033 -#define MASK_VFMIN_B 0xfe00707f -#define MATCH_VFMIN_R_B 0x8a007033 -#define MASK_VFMIN_R_B 0xfe00707f -#define MATCH_VFMAX_B 0x8c003033 -#define MASK_VFMAX_B 0xfe00707f -#define MATCH_VFMAX_R_B 0x8c007033 -#define MASK_VFMAX_R_B 0xfe00707f -#define MATCH_VFSQRT_B 0x8e003033 -#define MASK_VFSQRT_B 0xfff0707f -#define MATCH_VFMAC_B 0x90003033 -#define MASK_VFMAC_B 0xfe00707f -#define MATCH_VFMAC_R_B 0x90007033 -#define MASK_VFMAC_R_B 0xfe00707f -#define MATCH_VFMRE_B 0x92003033 -#define MASK_VFMRE_B 0xfe00707f -#define MATCH_VFMRE_R_B 0x92007033 -#define MASK_VFMRE_R_B 0xfe00707f -#define MATCH_VFSGNJ_B 0x9a003033 -#define MASK_VFSGNJ_B 0xfe00707f -#define MATCH_VFSGNJ_R_B 0x9a007033 -#define MASK_VFSGNJ_R_B 0xfe00707f -#define MATCH_VFSGNJN_B 0x9c003033 -#define MASK_VFSGNJN_B 0xfe00707f -#define MATCH_VFSGNJN_R_B 0x9c007033 -#define MASK_VFSGNJN_R_B 0xfe00707f -#define MATCH_VFSGNJX_B 0x9e003033 -#define MASK_VFSGNJX_B 0xfe00707f -#define MATCH_VFSGNJX_R_B 0x9e007033 -#define MASK_VFSGNJX_R_B 0xfe00707f -#define MATCH_VFEQ_B 0xa0003033 -#define MASK_VFEQ_B 0xfe00707f -#define MATCH_VFEQ_R_B 0xa0007033 -#define MASK_VFEQ_R_B 0xfe00707f -#define MATCH_VFNE_B 0xa2003033 -#define MASK_VFNE_B 0xfe00707f -#define MATCH_VFNE_R_B 0xa2007033 -#define MASK_VFNE_R_B 0xfe00707f -#define MATCH_VFLT_B 0xa4003033 -#define MASK_VFLT_B 0xfe00707f -#define MATCH_VFLT_R_B 0xa4007033 -#define MASK_VFLT_R_B 0xfe00707f -#define MATCH_VFGE_B 0xa6003033 -#define MASK_VFGE_B 0xfe00707f -#define MATCH_VFGE_R_B 0xa6007033 -#define MASK_VFGE_R_B 0xfe00707f -#define MATCH_VFLE_B 0xa8003033 -#define MASK_VFLE_B 0xfe00707f -#define MATCH_VFLE_R_B 0xa8007033 -#define MASK_VFLE_R_B 0xfe00707f -#define MATCH_VFGT_B 0xaa003033 -#define MASK_VFGT_B 0xfe00707f -#define MATCH_VFGT_R_B 0xaa007033 -#define MASK_VFGT_R_B 0xfe00707f -#define MATCH_VFMV_X_B 0x98003033 -#define MASK_VFMV_X_B 0xfff0707f -#define MATCH_VFMV_B_X 0x98007033 -#define MASK_VFMV_B_X 0xfff0707f -#define MATCH_VFCLASS_B 0x98103033 -#define MASK_VFCLASS_B 0xfff0707f -#define MATCH_VFCVT_X_B 0x98203033 -#define MASK_VFCVT_X_B 0xfff0707f -#define MATCH_VFCVT_XU_B 0x98207033 -#define MASK_VFCVT_XU_B 0xfff0707f -#define MATCH_VFCVT_B_X 0x98303033 -#define MASK_VFCVT_B_X 0xfff0707f -#define MATCH_VFCVT_B_XU 0x98307033 -#define MASK_VFCVT_B_XU 0xfff0707f -#define MATCH_VFCPKA_B_S 0xb0003033 -#define MASK_VFCPKA_B_S 0xfe00707f -#define MATCH_VFCPKB_B_S 0xb0007033 -#define MASK_VFCPKB_B_S 0xfe00707f -#define MATCH_VFCPKC_B_S 0xb2003033 -#define MASK_VFCPKC_B_S 0xfe00707f -#define MATCH_VFCPKD_B_S 0xb2007033 -#define MASK_VFCPKD_B_S 0xfe00707f -#define MATCH_VFCPKA_B_D 0xb4003033 -#define MASK_VFCPKA_B_D 0xfe00707f -#define MATCH_VFCPKB_B_D 0xb4007033 -#define MASK_VFCPKB_B_D 0xfe00707f -#define MATCH_VFCPKC_B_D 0xb6003033 -#define MASK_VFCPKC_B_D 0xfe00707f -#define MATCH_VFCPKD_B_D 0xb6007033 -#define MASK_VFCPKD_B_D 0xfe00707f -#define MATCH_VFCVT_S_B 0x98700033 -#define MASK_VFCVT_S_B 0xfff0707f -#define MATCH_VFCVTU_S_B 0x98704033 -#define MASK_VFCVTU_S_B 0xfff0707f -#define MATCH_VFCVT_B_S 0x98403033 -#define MASK_VFCVT_B_S 0xfff0707f -#define MATCH_VFCVTU_B_S 0x98407033 -#define MASK_VFCVTU_B_S 0xfff0707f -#define MATCH_VFCVT_H_B 0x98702033 -#define MASK_VFCVT_H_B 0xfff0707f -#define MATCH_VFCVTU_H_B 0x98706033 -#define MASK_VFCVTU_H_B 0xfff0707f -#define MATCH_VFCVT_B_H 0x98603033 -#define MASK_VFCVT_B_H 0xfff0707f -#define MATCH_VFCVTU_B_H 0x98607033 -#define MASK_VFCVTU_B_H 0xfff0707f -#define MATCH_VFCVT_AH_B 0x98701033 -#define MASK_VFCVT_AH_B 0xfff0707f -#define MATCH_VFCVTU_AH_B 0x98705033 -#define MASK_VFCVTU_AH_B 0xfff0707f -#define MATCH_VFCVT_B_AH 0x98503033 -#define MASK_VFCVT_B_AH 0xfff0707f -#define MATCH_VFCVTU_B_AH 0x98507033 -#define MASK_VFCVTU_B_AH 0xfff0707f -#define MATCH_VFDOTP_S 0x94000033 -#define MASK_VFDOTP_S 0xfe00707f -#define MATCH_VFDOTP_R_S 0x94004033 -#define MASK_VFDOTP_R_S 0xfe00707f -#define MATCH_VFAVG_S 0xac000033 -#define MASK_VFAVG_S 0xfe00707f -#define MATCH_VFAVG_R_S 0xac004033 -#define MASK_VFAVG_R_S 0xfe00707f -#define MATCH_FMULEX_S_H 0x4c000053 -#define MASK_FMULEX_S_H 0xfe00007f -#define MATCH_FMACEX_S_H 0x54000053 -#define MASK_FMACEX_S_H 0xfe00007f -#define MATCH_VFDOTP_H 0x94002033 -#define MASK_VFDOTP_H 0xfe00707f -#define MATCH_VFDOTP_R_H 0x94006033 -#define MASK_VFDOTP_R_H 0xfe00707f -#define MATCH_VFDOTPEX_S_H 0x96002033 -#define MASK_VFDOTPEX_S_H 0xfe00707f -#define MATCH_VFDOTPEX_S_R_H 0x96006033 -#define MASK_VFDOTPEX_S_R_H 0xfe00707f -#define MATCH_VFAVG_H 0xac002033 -#define MASK_VFAVG_H 0xfe00707f -#define MATCH_VFAVG_R_H 0xac006033 -#define MASK_VFAVG_R_H 0xfe00707f -#define MATCH_FMULEX_S_AH 0x4c005053 -#define MASK_FMULEX_S_AH 0xfe00707f -#define MATCH_FMACEX_S_AH 0x54005053 -#define MASK_FMACEX_S_AH 0xfe00707f -#define MATCH_VFDOTP_AH 0x94001033 -#define MASK_VFDOTP_AH 0xfe00707f -#define MATCH_VFDOTP_R_AH 0x94005033 -#define MASK_VFDOTP_R_AH 0xfe00707f -#define MATCH_VFDOTPEX_S_AH 0x96001033 -#define MASK_VFDOTPEX_S_AH 0xfe00707f -#define MATCH_VFDOTPEX_S_R_AH 0x96005033 -#define MASK_VFDOTPEX_S_R_AH 0xfe00707f -#define MATCH_VFAVG_AH 0xac001033 -#define MASK_VFAVG_AH 0xfe00707f -#define MATCH_VFAVG_R_AH 0xac005033 -#define MASK_VFAVG_R_AH 0xfe00707f -#define MATCH_FMULEX_S_B 0x4e000053 -#define MASK_FMULEX_S_B 0xfe00007f -#define MATCH_FMACEX_S_B 0x56000053 -#define MASK_FMACEX_S_B 0xfe00007f -#define MATCH_VFDOTP_B 0x94003033 -#define MASK_VFDOTP_B 0xfe00707f -#define MATCH_VFDOTP_R_B 0x94007033 -#define MASK_VFDOTP_R_B 0xfe00707f -#define MATCH_VFDOTPEX_S_B 0x96003033 -#define MASK_VFDOTPEX_S_B 0xfe00707f -#define MATCH_VFDOTPEX_S_R_B 0x96007033 -#define MASK_VFDOTPEX_S_R_B 0xfe00707f -#define MATCH_VFAVG_B 0xac003033 -#define MASK_VFAVG_B 0xfe00707f -#define MATCH_VFAVG_R_B 0xac007033 -#define MASK_VFAVG_R_B 0xfe00707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_USTATUS 0x0 -#define CSR_UIE 0x4 -#define CSR_UTVEC 0x5 -#define CSR_VSTART 0x8 -#define CSR_VXSAT 0x9 -#define CSR_VXRM 0xa -#define CSR_VCSR 0xf -#define CSR_USCRATCH 0x40 -#define CSR_UEPC 0x41 -#define CSR_UCAUSE 0x42 -#define CSR_UTVAL 0x43 -#define CSR_UIP 0x44 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_VL 0xc20 -#define CSR_VTYPE 0xc21 -#define CSR_VLENB 0xc22 -#define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 -#define CSR_SATP 0x180 -#define CSR_VSSTATUS 0x200 -#define CSR_VSIE 0x204 -#define CSR_VSTVEC 0x205 -#define CSR_VSSCRATCH 0x240 -#define CSR_VSEPC 0x241 -#define CSR_VSCAUSE 0x242 -#define CSR_VSTVAL 0x243 -#define CSR_VSIP 0x244 -#define CSR_VSATP 0x280 -#define CSR_HSTATUS 0x600 -#define CSR_HEDELEG 0x602 -#define CSR_HIDELEG 0x603 -#define CSR_HIE 0x604 -#define CSR_HTIMEDELTA 0x605 -#define CSR_HCOUNTEREN 0x606 -#define CSR_HGEIE 0x607 -#define CSR_HTVAL 0x643 -#define CSR_HIP 0x644 -#define CSR_HVIP 0x645 -#define CSR_HTINST 0x64a -#define CSR_HGATP 0x680 -#define CSR_HGEIP 0xe12 -#define CSR_UTVT 0x7 -#define CSR_UNXTI 0x45 -#define CSR_UINTSTATUS 0x46 -#define CSR_USCRATCHCSW 0x48 -#define CSR_USCRATCHCSWL 0x49 -#define CSR_STVT 0x107 -#define CSR_SNXTI 0x145 -#define CSR_SINTSTATUS 0x146 -#define CSR_SSCRATCHCSW 0x148 -#define CSR_SSCRATCHCSWL 0x149 -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 -#define CSR_MINTSTATUS 0x346 -#define CSR_MSCRATCHCSW 0x348 -#define CSR_MSCRATCHCSWL 0x349 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MCOUNTINHIBIT 0x320 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MTINST 0x34a -#define CSR_MTVAL2 0x34b -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH0 0x7b2 -#define CSR_DSCRATCH1 0x7b3 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_TRACE 0x7d0 -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_HTIMEDELTAH 0x615 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MSTATUSH 0x310 -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 -#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 -#define CAUSE_VIRTUAL_INSTRUCTION 0x16 -#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) -DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) -DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) -DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) -DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) -DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) -DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) -DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) -DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) -DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) -DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) -DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) -DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) -DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) -DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) -DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32) -DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32) -DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) -DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) -DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) -DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) -DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) -DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) -DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) -DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) -DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) -DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) -DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) -DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) -DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) -DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) -DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) -DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) -DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) -DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) -DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) -DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) -DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) -DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) -DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) -DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) -DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) -DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) -DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) -DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) -DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) -DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) -DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) -DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) -DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) -DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) -DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) -DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) -DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) -DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) -DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) -DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) -DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) -DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) -DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) -DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) -DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) -DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) -DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) -DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) -DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) -DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) -DECLARE_INSN(vlxei8_v, MATCH_VLXEI8_V, MASK_VLXEI8_V) -DECLARE_INSN(vlxei16_v, MATCH_VLXEI16_V, MASK_VLXEI16_V) -DECLARE_INSN(vlxei32_v, MATCH_VLXEI32_V, MASK_VLXEI32_V) -DECLARE_INSN(vlxei64_v, MATCH_VLXEI64_V, MASK_VLXEI64_V) -DECLARE_INSN(vlxei128_v, MATCH_VLXEI128_V, MASK_VLXEI128_V) -DECLARE_INSN(vlxei256_v, MATCH_VLXEI256_V, MASK_VLXEI256_V) -DECLARE_INSN(vlxei512_v, MATCH_VLXEI512_V, MASK_VLXEI512_V) -DECLARE_INSN(vlxei1024_v, MATCH_VLXEI1024_V, MASK_VLXEI1024_V) -DECLARE_INSN(vsxei8_v, MATCH_VSXEI8_V, MASK_VSXEI8_V) -DECLARE_INSN(vsxei16_v, MATCH_VSXEI16_V, MASK_VSXEI16_V) -DECLARE_INSN(vsxei32_v, MATCH_VSXEI32_V, MASK_VSXEI32_V) -DECLARE_INSN(vsxei64_v, MATCH_VSXEI64_V, MASK_VSXEI64_V) -DECLARE_INSN(vsxei128_v, MATCH_VSXEI128_V, MASK_VSXEI128_V) -DECLARE_INSN(vsxei256_v, MATCH_VSXEI256_V, MASK_VSXEI256_V) -DECLARE_INSN(vsxei512_v, MATCH_VSXEI512_V, MASK_VSXEI512_V) -DECLARE_INSN(vsxei1024_v, MATCH_VSXEI1024_V, MASK_VSXEI1024_V) -DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) -DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) -DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) -DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) -DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) -DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) -DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) -DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) -DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) -DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) -DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) -DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) -DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) -DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) -DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) -DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) -DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) -DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) -DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) -DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) -DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) -DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) -DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) -DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) -DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) -DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) -DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) -DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) -DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) -DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) -DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) -DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) -DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) -DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) -DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) -DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) -DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) -DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) -DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) -DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) -DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) -DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) -DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) -DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) -DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) -DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) -DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) -DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) -DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) -DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) -DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) -DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) -DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) -DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) -DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) -DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) -DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) -DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) -DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) -DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) -DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) -DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) -DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) -DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) -DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) -DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) -DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) -DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) -DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) -DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) -DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) -DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) -DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) -DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) -DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) -DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) -DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS) -DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) -DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) -DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) -DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) -DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) -DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) -DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) -DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) -DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) -DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) -DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) -DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) -DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) -DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) -DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) -DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) -DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) -DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) -DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) -DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) -DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) -DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) -DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) -DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) -DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) -DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) -DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) -DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) -DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) -DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) -DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) -DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) -DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) -DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) -DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) -DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) -DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) -DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) -DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) -DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) -DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) -DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) -DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) -DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) -DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) -DECLARE_INSN(vfrsqrte7_v, MATCH_VFRSQRTE7_V, MASK_VFRSQRTE7_V) -DECLARE_INSN(vfrece7_v, MATCH_VFRECE7_V, MASK_VFRECE7_V) -DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) -DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) -DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) -DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) -DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) -DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) -DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) -DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) -DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV) -DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) -DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) -DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) -DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) -DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) -DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) -DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) -DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) -DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) -DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) -DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) -DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) -DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) -DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) -DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) -DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) -DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) -DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) -DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) -DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) -DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) -DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) -DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) -DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) -DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) -DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) -DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) -DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) -DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) -DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) -DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) -DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) -DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) -DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) -DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) -DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) -DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) -DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) -DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) -DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) -DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) -DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) -DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) -DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX) -DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX) -DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX) -DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX) -DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) -DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) -DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) -DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) -DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) -DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) -DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) -DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) -DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) -DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) -DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) -DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) -DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) -DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) -DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) -DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) -DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) -DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) -DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) -DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) -DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) -DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) -DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) -DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) -DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) -DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) -DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) -DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) -DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) -DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) -DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) -DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) -DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) -DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) -DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) -DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) -DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) -DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) -DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV) -DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV) -DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV) -DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV) -DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) -DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) -DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) -DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) -DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) -DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) -DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) -DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) -DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) -DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) -DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) -DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) -DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) -DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) -DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) -DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) -DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) -DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) -DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) -DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) -DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) -DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) -DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) -DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) -DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) -DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) -DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) -DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) -DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) -DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) -DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) -DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) -DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) -DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) -DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) -DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) -DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) -DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) -DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) -DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) -DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) -DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) -DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) -DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) -DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) -DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) -DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) -DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) -DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) -DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) -DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) -DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) -DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) -DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM) -DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) -DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) -DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) -DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM) -DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) -DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) -DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) -DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) -DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) -DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) -DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) -DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) -DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M) -DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) -DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) -DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) -DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) -DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) -DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) -DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) -DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) -DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) -DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) -DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) -DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) -DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) -DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) -DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) -DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) -DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) -DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) -DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) -DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) -DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) -DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) -DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) -DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) -DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) -DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) -DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) -DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) -DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) -DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) -DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) -DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) -DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) -DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) -DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) -DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) -DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) -DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) -DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) -DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) -DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) -DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) -DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) -DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) -DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) -DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) -DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) -DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) -DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) -DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) -DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) -DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) -DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) -DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) -DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) -DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) -DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) -DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) -DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) -DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) -DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) -DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) -DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) -DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) -DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) -DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) -DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) -DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) -DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) -DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) -DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) -DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) -DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) -DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) -DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) -DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) -DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) -DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) -DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) -DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) -DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) -DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) -DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) -DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) -DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) -DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) -DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) -DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) -DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) -DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) -DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) -DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) -DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V) -DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V) -DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V) -DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(lp_starti, MATCH_LP_STARTI, MASK_LP_STARTI) -DECLARE_INSN(lp_endi, MATCH_LP_ENDI, MASK_LP_ENDI) -DECLARE_INSN(lp_count, MATCH_LP_COUNT, MASK_LP_COUNT) -DECLARE_INSN(lp_counti, MATCH_LP_COUNTI, MASK_LP_COUNTI) -DECLARE_INSN(lp_setup, MATCH_LP_SETUP, MASK_LP_SETUP) -DECLARE_INSN(lp_setupi, MATCH_LP_SETUPI, MASK_LP_SETUPI) -DECLARE_INSN(p_lb_irpost, MATCH_P_LB_IRPOST, MASK_P_LB_IRPOST) -DECLARE_INSN(p_lbu_irpost, MATCH_P_LBU_IRPOST, MASK_P_LBU_IRPOST) -DECLARE_INSN(p_lh_irpost, MATCH_P_LH_IRPOST, MASK_P_LH_IRPOST) -DECLARE_INSN(p_lhu_irpost, MATCH_P_LHU_IRPOST, MASK_P_LHU_IRPOST) -DECLARE_INSN(p_lw_irpost, MATCH_P_LW_IRPOST, MASK_P_LW_IRPOST) -DECLARE_INSN(p_lb_rrpost, MATCH_P_LB_RRPOST, MASK_P_LB_RRPOST) -DECLARE_INSN(p_lbu_rrpost, MATCH_P_LBU_RRPOST, MASK_P_LBU_RRPOST) -DECLARE_INSN(p_lh_rrpost, MATCH_P_LH_RRPOST, MASK_P_LH_RRPOST) -DECLARE_INSN(p_lhu_rrpost, MATCH_P_LHU_RRPOST, MASK_P_LHU_RRPOST) -DECLARE_INSN(p_lw_rrpost, MATCH_P_LW_RRPOST, MASK_P_LW_RRPOST) -DECLARE_INSN(p_lb_rr, MATCH_P_LB_RR, MASK_P_LB_RR) -DECLARE_INSN(p_lbu_rr, MATCH_P_LBU_RR, MASK_P_LBU_RR) -DECLARE_INSN(p_lh_rr, MATCH_P_LH_RR, MASK_P_LH_RR) -DECLARE_INSN(p_lhu_rr, MATCH_P_LHU_RR, MASK_P_LHU_RR) -DECLARE_INSN(p_lw_rr, MATCH_P_LW_RR, MASK_P_LW_RR) -DECLARE_INSN(p_sb_irpost, MATCH_P_SB_IRPOST, MASK_P_SB_IRPOST) -DECLARE_INSN(p_sh_irpost, MATCH_P_SH_IRPOST, MASK_P_SH_IRPOST) -DECLARE_INSN(p_sw_irpost, MATCH_P_SW_IRPOST, MASK_P_SW_IRPOST) -DECLARE_INSN(p_sb_rrpost, MATCH_P_SB_RRPOST, MASK_P_SB_RRPOST) -DECLARE_INSN(p_sh_rrpost, MATCH_P_SH_RRPOST, MASK_P_SH_RRPOST) -DECLARE_INSN(p_sw_rrpost, MATCH_P_SW_RRPOST, MASK_P_SW_RRPOST) -DECLARE_INSN(p_sb_rr, MATCH_P_SB_RR, MASK_P_SB_RR) -DECLARE_INSN(p_sh_rr, MATCH_P_SH_RR, MASK_P_SH_RR) -DECLARE_INSN(p_sw_rr, MATCH_P_SW_RR, MASK_P_SW_RR) -DECLARE_INSN(p_abs, MATCH_P_ABS, MASK_P_ABS) -DECLARE_INSN(p_slet, MATCH_P_SLET, MASK_P_SLET) -DECLARE_INSN(p_sletu, MATCH_P_SLETU, MASK_P_SLETU) -DECLARE_INSN(p_min, MATCH_P_MIN, MASK_P_MIN) -DECLARE_INSN(p_minu, MATCH_P_MINU, MASK_P_MINU) -DECLARE_INSN(p_max, MATCH_P_MAX, MASK_P_MAX) -DECLARE_INSN(p_maxu, MATCH_P_MAXU, MASK_P_MAXU) -DECLARE_INSN(p_exths, MATCH_P_EXTHS, MASK_P_EXTHS) -DECLARE_INSN(p_exthz, MATCH_P_EXTHZ, MASK_P_EXTHZ) -DECLARE_INSN(p_extbs, MATCH_P_EXTBS, MASK_P_EXTBS) -DECLARE_INSN(p_extbz, MATCH_P_EXTBZ, MASK_P_EXTBZ) -DECLARE_INSN(p_clip, MATCH_P_CLIP, MASK_P_CLIP) -DECLARE_INSN(p_clipu, MATCH_P_CLIPU, MASK_P_CLIPU) -DECLARE_INSN(p_clipr, MATCH_P_CLIPR, MASK_P_CLIPR) -DECLARE_INSN(p_clipur, MATCH_P_CLIPUR, MASK_P_CLIPUR) -DECLARE_INSN(p_beqimm, MATCH_P_BEQIMM, MASK_P_BEQIMM) -DECLARE_INSN(p_bneimm, MATCH_P_BNEIMM, MASK_P_BNEIMM) -DECLARE_INSN(p_mac, MATCH_P_MAC, MASK_P_MAC) -DECLARE_INSN(p_msu, MATCH_P_MSU, MASK_P_MSU) -DECLARE_INSN(pv_add_h, MATCH_PV_ADD_H, MASK_PV_ADD_H) -DECLARE_INSN(pv_add_sc_h, MATCH_PV_ADD_SC_H, MASK_PV_ADD_SC_H) -DECLARE_INSN(pv_add_sci_h, MATCH_PV_ADD_SCI_H, MASK_PV_ADD_SCI_H) -DECLARE_INSN(pv_add_b, MATCH_PV_ADD_B, MASK_PV_ADD_B) -DECLARE_INSN(pv_add_sc_b, MATCH_PV_ADD_SC_B, MASK_PV_ADD_SC_B) -DECLARE_INSN(pv_add_sci_b, MATCH_PV_ADD_SCI_B, MASK_PV_ADD_SCI_B) -DECLARE_INSN(pv_sub_h, MATCH_PV_SUB_H, MASK_PV_SUB_H) -DECLARE_INSN(pv_sub_sc_h, MATCH_PV_SUB_SC_H, MASK_PV_SUB_SC_H) -DECLARE_INSN(pv_sub_sci_h, MATCH_PV_SUB_SCI_H, MASK_PV_SUB_SCI_H) -DECLARE_INSN(pv_sub_b, MATCH_PV_SUB_B, MASK_PV_SUB_B) -DECLARE_INSN(pv_sub_sc_b, MATCH_PV_SUB_SC_B, MASK_PV_SUB_SC_B) -DECLARE_INSN(pv_sub_sci_b, MATCH_PV_SUB_SCI_B, MASK_PV_SUB_SCI_B) -DECLARE_INSN(pv_avg_h, MATCH_PV_AVG_H, MASK_PV_AVG_H) -DECLARE_INSN(pv_avg_sc_h, MATCH_PV_AVG_SC_H, MASK_PV_AVG_SC_H) -DECLARE_INSN(pv_avg_sci_h, MATCH_PV_AVG_SCI_H, MASK_PV_AVG_SCI_H) -DECLARE_INSN(pv_avg_b, MATCH_PV_AVG_B, MASK_PV_AVG_B) -DECLARE_INSN(pv_avg_sc_b, MATCH_PV_AVG_SC_B, MASK_PV_AVG_SC_B) -DECLARE_INSN(pv_avg_sci_b, MATCH_PV_AVG_SCI_B, MASK_PV_AVG_SCI_B) -DECLARE_INSN(pv_avgu_h, MATCH_PV_AVGU_H, MASK_PV_AVGU_H) -DECLARE_INSN(pv_avgu_sc_h, MATCH_PV_AVGU_SC_H, MASK_PV_AVGU_SC_H) -DECLARE_INSN(pv_avgu_sci_h, MATCH_PV_AVGU_SCI_H, MASK_PV_AVGU_SCI_H) -DECLARE_INSN(pv_avgu_b, MATCH_PV_AVGU_B, MASK_PV_AVGU_B) -DECLARE_INSN(pv_avgu_sc_b, MATCH_PV_AVGU_SC_B, MASK_PV_AVGU_SC_B) -DECLARE_INSN(pv_avgu_sci_b, MATCH_PV_AVGU_SCI_B, MASK_PV_AVGU_SCI_B) -DECLARE_INSN(pv_min_h, MATCH_PV_MIN_H, MASK_PV_MIN_H) -DECLARE_INSN(pv_min_sc_h, MATCH_PV_MIN_SC_H, MASK_PV_MIN_SC_H) -DECLARE_INSN(pv_min_sci_h, MATCH_PV_MIN_SCI_H, MASK_PV_MIN_SCI_H) -DECLARE_INSN(pv_min_b, MATCH_PV_MIN_B, MASK_PV_MIN_B) -DECLARE_INSN(pv_min_sc_b, MATCH_PV_MIN_SC_B, MASK_PV_MIN_SC_B) -DECLARE_INSN(pv_min_sci_b, MATCH_PV_MIN_SCI_B, MASK_PV_MIN_SCI_B) -DECLARE_INSN(pv_minu_h, MATCH_PV_MINU_H, MASK_PV_MINU_H) -DECLARE_INSN(pv_minu_sc_h, MATCH_PV_MINU_SC_H, MASK_PV_MINU_SC_H) -DECLARE_INSN(pv_minu_sci_h, MATCH_PV_MINU_SCI_H, MASK_PV_MINU_SCI_H) -DECLARE_INSN(pv_minu_b, MATCH_PV_MINU_B, MASK_PV_MINU_B) -DECLARE_INSN(pv_minu_sc_b, MATCH_PV_MINU_SC_B, MASK_PV_MINU_SC_B) -DECLARE_INSN(pv_minu_sci_b, MATCH_PV_MINU_SCI_B, MASK_PV_MINU_SCI_B) -DECLARE_INSN(pv_max_h, MATCH_PV_MAX_H, MASK_PV_MAX_H) -DECLARE_INSN(pv_max_sc_h, MATCH_PV_MAX_SC_H, MASK_PV_MAX_SC_H) -DECLARE_INSN(pv_max_sci_h, MATCH_PV_MAX_SCI_H, MASK_PV_MAX_SCI_H) -DECLARE_INSN(pv_max_b, MATCH_PV_MAX_B, MASK_PV_MAX_B) -DECLARE_INSN(pv_max_sc_b, MATCH_PV_MAX_SC_B, MASK_PV_MAX_SC_B) -DECLARE_INSN(pv_max_sci_b, MATCH_PV_MAX_SCI_B, MASK_PV_MAX_SCI_B) -DECLARE_INSN(pv_maxu_h, MATCH_PV_MAXU_H, MASK_PV_MAXU_H) -DECLARE_INSN(pv_maxu_sc_h, MATCH_PV_MAXU_SC_H, MASK_PV_MAXU_SC_H) -DECLARE_INSN(pv_maxu_sci_h, MATCH_PV_MAXU_SCI_H, MASK_PV_MAXU_SCI_H) -DECLARE_INSN(pv_maxu_b, MATCH_PV_MAXU_B, MASK_PV_MAXU_B) -DECLARE_INSN(pv_maxu_sc_b, MATCH_PV_MAXU_SC_B, MASK_PV_MAXU_SC_B) -DECLARE_INSN(pv_maxu_sci_b, MATCH_PV_MAXU_SCI_B, MASK_PV_MAXU_SCI_B) -DECLARE_INSN(pv_srl_h, MATCH_PV_SRL_H, MASK_PV_SRL_H) -DECLARE_INSN(pv_srl_sc_h, MATCH_PV_SRL_SC_H, MASK_PV_SRL_SC_H) -DECLARE_INSN(pv_srl_sci_h, MATCH_PV_SRL_SCI_H, MASK_PV_SRL_SCI_H) -DECLARE_INSN(pv_srl_b, MATCH_PV_SRL_B, MASK_PV_SRL_B) -DECLARE_INSN(pv_srl_sc_b, MATCH_PV_SRL_SC_B, MASK_PV_SRL_SC_B) -DECLARE_INSN(pv_srl_sci_b, MATCH_PV_SRL_SCI_B, MASK_PV_SRL_SCI_B) -DECLARE_INSN(pv_sra_h, MATCH_PV_SRA_H, MASK_PV_SRA_H) -DECLARE_INSN(pv_sra_sc_h, MATCH_PV_SRA_SC_H, MASK_PV_SRA_SC_H) -DECLARE_INSN(pv_sra_sci_h, MATCH_PV_SRA_SCI_H, MASK_PV_SRA_SCI_H) -DECLARE_INSN(pv_sra_b, MATCH_PV_SRA_B, MASK_PV_SRA_B) -DECLARE_INSN(pv_sra_sc_b, MATCH_PV_SRA_SC_B, MASK_PV_SRA_SC_B) -DECLARE_INSN(pv_sra_sci_b, MATCH_PV_SRA_SCI_B, MASK_PV_SRA_SCI_B) -DECLARE_INSN(pv_sll_h, MATCH_PV_SLL_H, MASK_PV_SLL_H) -DECLARE_INSN(pv_sll_sc_h, MATCH_PV_SLL_SC_H, MASK_PV_SLL_SC_H) -DECLARE_INSN(pv_sll_sci_h, MATCH_PV_SLL_SCI_H, MASK_PV_SLL_SCI_H) -DECLARE_INSN(pv_sll_b, MATCH_PV_SLL_B, MASK_PV_SLL_B) -DECLARE_INSN(pv_sll_sc_b, MATCH_PV_SLL_SC_B, MASK_PV_SLL_SC_B) -DECLARE_INSN(pv_sll_sci_b, MATCH_PV_SLL_SCI_B, MASK_PV_SLL_SCI_B) -DECLARE_INSN(pv_or_h, MATCH_PV_OR_H, MASK_PV_OR_H) -DECLARE_INSN(pv_or_sc_h, MATCH_PV_OR_SC_H, MASK_PV_OR_SC_H) -DECLARE_INSN(pv_or_sci_h, MATCH_PV_OR_SCI_H, MASK_PV_OR_SCI_H) -DECLARE_INSN(pv_or_b, MATCH_PV_OR_B, MASK_PV_OR_B) -DECLARE_INSN(pv_or_sc_b, MATCH_PV_OR_SC_B, MASK_PV_OR_SC_B) -DECLARE_INSN(pv_or_sci_b, MATCH_PV_OR_SCI_B, MASK_PV_OR_SCI_B) -DECLARE_INSN(pv_xor_h, MATCH_PV_XOR_H, MASK_PV_XOR_H) -DECLARE_INSN(pv_xor_sc_h, MATCH_PV_XOR_SC_H, MASK_PV_XOR_SC_H) -DECLARE_INSN(pv_xor_sci_h, MATCH_PV_XOR_SCI_H, MASK_PV_XOR_SCI_H) -DECLARE_INSN(pv_xor_b, MATCH_PV_XOR_B, MASK_PV_XOR_B) -DECLARE_INSN(pv_xor_sc_b, MATCH_PV_XOR_SC_B, MASK_PV_XOR_SC_B) -DECLARE_INSN(pv_xor_sci_b, MATCH_PV_XOR_SCI_B, MASK_PV_XOR_SCI_B) -DECLARE_INSN(pv_and_h, MATCH_PV_AND_H, MASK_PV_AND_H) -DECLARE_INSN(pv_and_sc_h, MATCH_PV_AND_SC_H, MASK_PV_AND_SC_H) -DECLARE_INSN(pv_and_sci_h, MATCH_PV_AND_SCI_H, MASK_PV_AND_SCI_H) -DECLARE_INSN(pv_and_b, MATCH_PV_AND_B, MASK_PV_AND_B) -DECLARE_INSN(pv_and_sc_b, MATCH_PV_AND_SC_B, MASK_PV_AND_SC_B) -DECLARE_INSN(pv_and_sci_b, MATCH_PV_AND_SCI_B, MASK_PV_AND_SCI_B) -DECLARE_INSN(pv_abs_h, MATCH_PV_ABS_H, MASK_PV_ABS_H) -DECLARE_INSN(pv_abs_b, MATCH_PV_ABS_B, MASK_PV_ABS_B) -DECLARE_INSN(pv_extract_h, MATCH_PV_EXTRACT_H, MASK_PV_EXTRACT_H) -DECLARE_INSN(pv_extract_b, MATCH_PV_EXTRACT_B, MASK_PV_EXTRACT_B) -DECLARE_INSN(pv_extractu_h, MATCH_PV_EXTRACTU_H, MASK_PV_EXTRACTU_H) -DECLARE_INSN(pv_extractu_b, MATCH_PV_EXTRACTU_B, MASK_PV_EXTRACTU_B) -DECLARE_INSN(pv_insert_h, MATCH_PV_INSERT_H, MASK_PV_INSERT_H) -DECLARE_INSN(pv_insert_b, MATCH_PV_INSERT_B, MASK_PV_INSERT_B) -DECLARE_INSN(pv_dotup_h, MATCH_PV_DOTUP_H, MASK_PV_DOTUP_H) -DECLARE_INSN(pv_dotup_sc_h, MATCH_PV_DOTUP_SC_H, MASK_PV_DOTUP_SC_H) -DECLARE_INSN(pv_dotup_sci_h, MATCH_PV_DOTUP_SCI_H, MASK_PV_DOTUP_SCI_H) -DECLARE_INSN(pv_dotup_b, MATCH_PV_DOTUP_B, MASK_PV_DOTUP_B) -DECLARE_INSN(pv_dotup_sc_b, MATCH_PV_DOTUP_SC_B, MASK_PV_DOTUP_SC_B) -DECLARE_INSN(pv_dotup_sci_b, MATCH_PV_DOTUP_SCI_B, MASK_PV_DOTUP_SCI_B) -DECLARE_INSN(pv_dotusp_h, MATCH_PV_DOTUSP_H, MASK_PV_DOTUSP_H) -DECLARE_INSN(pv_dotusp_sc_h, MATCH_PV_DOTUSP_SC_H, MASK_PV_DOTUSP_SC_H) -DECLARE_INSN(pv_dotusp_sci_h, MATCH_PV_DOTUSP_SCI_H, MASK_PV_DOTUSP_SCI_H) -DECLARE_INSN(pv_dotusp_b, MATCH_PV_DOTUSP_B, MASK_PV_DOTUSP_B) -DECLARE_INSN(pv_dotusp_sc_b, MATCH_PV_DOTUSP_SC_B, MASK_PV_DOTUSP_SC_B) -DECLARE_INSN(pv_dotusp_sci_b, MATCH_PV_DOTUSP_SCI_B, MASK_PV_DOTUSP_SCI_B) -DECLARE_INSN(pv_dotsp_h, MATCH_PV_DOTSP_H, MASK_PV_DOTSP_H) -DECLARE_INSN(pv_dotsp_sc_h, MATCH_PV_DOTSP_SC_H, MASK_PV_DOTSP_SC_H) -DECLARE_INSN(pv_dotsp_sci_h, MATCH_PV_DOTSP_SCI_H, MASK_PV_DOTSP_SCI_H) -DECLARE_INSN(pv_dotsp_b, MATCH_PV_DOTSP_B, MASK_PV_DOTSP_B) -DECLARE_INSN(pv_dotsp_sc_b, MATCH_PV_DOTSP_SC_B, MASK_PV_DOTSP_SC_B) -DECLARE_INSN(pv_dotsp_sci_b, MATCH_PV_DOTSP_SCI_B, MASK_PV_DOTSP_SCI_B) -DECLARE_INSN(pv_sdotup_h, MATCH_PV_SDOTUP_H, MASK_PV_SDOTUP_H) -DECLARE_INSN(pv_sdotup_sc_h, MATCH_PV_SDOTUP_SC_H, MASK_PV_SDOTUP_SC_H) -DECLARE_INSN(pv_sdotup_sci_h, MATCH_PV_SDOTUP_SCI_H, MASK_PV_SDOTUP_SCI_H) -DECLARE_INSN(pv_sdotup_b, MATCH_PV_SDOTUP_B, MASK_PV_SDOTUP_B) -DECLARE_INSN(pv_sdotup_sc_b, MATCH_PV_SDOTUP_SC_B, MASK_PV_SDOTUP_SC_B) -DECLARE_INSN(pv_sdotup_sci_b, MATCH_PV_SDOTUP_SCI_B, MASK_PV_SDOTUP_SCI_B) -DECLARE_INSN(pv_sdotusp_h, MATCH_PV_SDOTUSP_H, MASK_PV_SDOTUSP_H) -DECLARE_INSN(pv_sdotusp_sc_h, MATCH_PV_SDOTUSP_SC_H, MASK_PV_SDOTUSP_SC_H) -DECLARE_INSN(pv_sdotusp_sci_h, MATCH_PV_SDOTUSP_SCI_H, MASK_PV_SDOTUSP_SCI_H) -DECLARE_INSN(pv_sdotusp_b, MATCH_PV_SDOTUSP_B, MASK_PV_SDOTUSP_B) -DECLARE_INSN(pv_sdotusp_sc_b, MATCH_PV_SDOTUSP_SC_B, MASK_PV_SDOTUSP_SC_B) -DECLARE_INSN(pv_sdotusp_sci_b, MATCH_PV_SDOTUSP_SCI_B, MASK_PV_SDOTUSP_SCI_B) -DECLARE_INSN(pv_sdotsp_h, MATCH_PV_SDOTSP_H, MASK_PV_SDOTSP_H) -DECLARE_INSN(pv_sdotsp_sc_h, MATCH_PV_SDOTSP_SC_H, MASK_PV_SDOTSP_SC_H) -DECLARE_INSN(pv_sdotsp_sci_h, MATCH_PV_SDOTSP_SCI_H, MASK_PV_SDOTSP_SCI_H) -DECLARE_INSN(pv_sdotsp_b, MATCH_PV_SDOTSP_B, MASK_PV_SDOTSP_B) -DECLARE_INSN(pv_sdotsp_sc_b, MATCH_PV_SDOTSP_SC_B, MASK_PV_SDOTSP_SC_B) -DECLARE_INSN(pv_sdotsp_sci_b, MATCH_PV_SDOTSP_SCI_B, MASK_PV_SDOTSP_SCI_B) -DECLARE_INSN(pv_shuffle2_h, MATCH_PV_SHUFFLE2_H, MASK_PV_SHUFFLE2_H) -DECLARE_INSN(pv_shuffle2_b, MATCH_PV_SHUFFLE2_B, MASK_PV_SHUFFLE2_B) -DECLARE_INSN(flah, MATCH_FLAH, MASK_FLAH) -DECLARE_INSN(fsah, MATCH_FSAH, MASK_FSAH) -DECLARE_INSN(fmadd_ah, MATCH_FMADD_AH, MASK_FMADD_AH) -DECLARE_INSN(fmsub_ah, MATCH_FMSUB_AH, MASK_FMSUB_AH) -DECLARE_INSN(fnmsub_ah, MATCH_FNMSUB_AH, MASK_FNMSUB_AH) -DECLARE_INSN(fnmadd_ah, MATCH_FNMADD_AH, MASK_FNMADD_AH) -DECLARE_INSN(fadd_ah, MATCH_FADD_AH, MASK_FADD_AH) -DECLARE_INSN(fsub_ah, MATCH_FSUB_AH, MASK_FSUB_AH) -DECLARE_INSN(fmul_ah, MATCH_FMUL_AH, MASK_FMUL_AH) -DECLARE_INSN(fdiv_ah, MATCH_FDIV_AH, MASK_FDIV_AH) -DECLARE_INSN(fsqrt_ah, MATCH_FSQRT_AH, MASK_FSQRT_AH) -DECLARE_INSN(fsgnj_ah, MATCH_FSGNJ_AH, MASK_FSGNJ_AH) -DECLARE_INSN(fsgnjn_ah, MATCH_FSGNJN_AH, MASK_FSGNJN_AH) -DECLARE_INSN(fsgnjx_ah, MATCH_FSGNJX_AH, MASK_FSGNJX_AH) -DECLARE_INSN(fmin_ah, MATCH_FMIN_AH, MASK_FMIN_AH) -DECLARE_INSN(fmax_ah, MATCH_FMAX_AH, MASK_FMAX_AH) -DECLARE_INSN(feq_ah, MATCH_FEQ_AH, MASK_FEQ_AH) -DECLARE_INSN(flt_ah, MATCH_FLT_AH, MASK_FLT_AH) -DECLARE_INSN(fle_ah, MATCH_FLE_AH, MASK_FLE_AH) -DECLARE_INSN(fcvt_w_ah, MATCH_FCVT_W_AH, MASK_FCVT_W_AH) -DECLARE_INSN(fcvt_wu_ah, MATCH_FCVT_WU_AH, MASK_FCVT_WU_AH) -DECLARE_INSN(fcvt_ah_w, MATCH_FCVT_AH_W, MASK_FCVT_AH_W) -DECLARE_INSN(fcvt_ah_wu, MATCH_FCVT_AH_WU, MASK_FCVT_AH_WU) -DECLARE_INSN(fmv_x_ah, MATCH_FMV_X_AH, MASK_FMV_X_AH) -DECLARE_INSN(fclass_ah, MATCH_FCLASS_AH, MASK_FCLASS_AH) -DECLARE_INSN(fmv_ah_x, MATCH_FMV_AH_X, MASK_FMV_AH_X) -DECLARE_INSN(fcvt_l_ah, MATCH_FCVT_L_AH, MASK_FCVT_L_AH) -DECLARE_INSN(fcvt_lu_ah, MATCH_FCVT_LU_AH, MASK_FCVT_LU_AH) -DECLARE_INSN(fcvt_ah_l, MATCH_FCVT_AH_L, MASK_FCVT_AH_L) -DECLARE_INSN(fcvt_ah_lu, MATCH_FCVT_AH_LU, MASK_FCVT_AH_LU) -DECLARE_INSN(fcvt_s_ah, MATCH_FCVT_S_AH, MASK_FCVT_S_AH) -DECLARE_INSN(fcvt_ah_s, MATCH_FCVT_AH_S, MASK_FCVT_AH_S) -DECLARE_INSN(fcvt_d_ah, MATCH_FCVT_D_AH, MASK_FCVT_D_AH) -DECLARE_INSN(fcvt_ah_d, MATCH_FCVT_AH_D, MASK_FCVT_AH_D) -DECLARE_INSN(fcvt_h_ah, MATCH_FCVT_H_AH, MASK_FCVT_H_AH) -DECLARE_INSN(fcvt_ah_h, MATCH_FCVT_AH_H, MASK_FCVT_AH_H) -DECLARE_INSN(flb, MATCH_FLB, MASK_FLB) -DECLARE_INSN(fsb, MATCH_FSB, MASK_FSB) -DECLARE_INSN(fmadd_b, MATCH_FMADD_B, MASK_FMADD_B) -DECLARE_INSN(fmsub_b, MATCH_FMSUB_B, MASK_FMSUB_B) -DECLARE_INSN(fnmsub_b, MATCH_FNMSUB_B, MASK_FNMSUB_B) -DECLARE_INSN(fnmadd_b, MATCH_FNMADD_B, MASK_FNMADD_B) -DECLARE_INSN(fadd_b, MATCH_FADD_B, MASK_FADD_B) -DECLARE_INSN(fsub_b, MATCH_FSUB_B, MASK_FSUB_B) -DECLARE_INSN(fmul_b, MATCH_FMUL_B, MASK_FMUL_B) -DECLARE_INSN(fdiv_b, MATCH_FDIV_B, MASK_FDIV_B) -DECLARE_INSN(fsqrt_b, MATCH_FSQRT_B, MASK_FSQRT_B) -DECLARE_INSN(fsgnj_b, MATCH_FSGNJ_B, MASK_FSGNJ_B) -DECLARE_INSN(fsgnjn_b, MATCH_FSGNJN_B, MASK_FSGNJN_B) -DECLARE_INSN(fsgnjx_b, MATCH_FSGNJX_B, MASK_FSGNJX_B) -DECLARE_INSN(fmin_b, MATCH_FMIN_B, MASK_FMIN_B) -DECLARE_INSN(fmax_b, MATCH_FMAX_B, MASK_FMAX_B) -DECLARE_INSN(feq_b, MATCH_FEQ_B, MASK_FEQ_B) -DECLARE_INSN(flt_b, MATCH_FLT_B, MASK_FLT_B) -DECLARE_INSN(fle_b, MATCH_FLE_B, MASK_FLE_B) -DECLARE_INSN(fcvt_w_b, MATCH_FCVT_W_B, MASK_FCVT_W_B) -DECLARE_INSN(fcvt_wu_b, MATCH_FCVT_WU_B, MASK_FCVT_WU_B) -DECLARE_INSN(fcvt_b_w, MATCH_FCVT_B_W, MASK_FCVT_B_W) -DECLARE_INSN(fcvt_b_wu, MATCH_FCVT_B_WU, MASK_FCVT_B_WU) -DECLARE_INSN(fmv_x_b, MATCH_FMV_X_B, MASK_FMV_X_B) -DECLARE_INSN(fclass_b, MATCH_FCLASS_B, MASK_FCLASS_B) -DECLARE_INSN(fmv_b_x, MATCH_FMV_B_X, MASK_FMV_B_X) -DECLARE_INSN(fcvt_l_b, MATCH_FCVT_L_B, MASK_FCVT_L_B) -DECLARE_INSN(fcvt_lu_b, MATCH_FCVT_LU_B, MASK_FCVT_LU_B) -DECLARE_INSN(fcvt_b_l, MATCH_FCVT_B_L, MASK_FCVT_B_L) -DECLARE_INSN(fcvt_b_lu, MATCH_FCVT_B_LU, MASK_FCVT_B_LU) -DECLARE_INSN(fcvt_s_b, MATCH_FCVT_S_B, MASK_FCVT_S_B) -DECLARE_INSN(fcvt_b_s, MATCH_FCVT_B_S, MASK_FCVT_B_S) -DECLARE_INSN(fcvt_d_b, MATCH_FCVT_D_B, MASK_FCVT_D_B) -DECLARE_INSN(fcvt_b_d, MATCH_FCVT_B_D, MASK_FCVT_B_D) -DECLARE_INSN(fcvt_h_b, MATCH_FCVT_H_B, MASK_FCVT_H_B) -DECLARE_INSN(fcvt_b_h, MATCH_FCVT_B_H, MASK_FCVT_B_H) -DECLARE_INSN(fcvt_ah_b, MATCH_FCVT_AH_B, MASK_FCVT_AH_B) -DECLARE_INSN(fcvt_b_ah, MATCH_FCVT_B_AH, MASK_FCVT_B_AH) -DECLARE_INSN(vfadd_s, MATCH_VFADD_S, MASK_VFADD_S) -DECLARE_INSN(vfadd_r_s, MATCH_VFADD_R_S, MASK_VFADD_R_S) -DECLARE_INSN(vfsub_s, MATCH_VFSUB_S, MASK_VFSUB_S) -DECLARE_INSN(vfsub_r_s, MATCH_VFSUB_R_S, MASK_VFSUB_R_S) -DECLARE_INSN(vfmul_s, MATCH_VFMUL_S, MASK_VFMUL_S) -DECLARE_INSN(vfmul_r_s, MATCH_VFMUL_R_S, MASK_VFMUL_R_S) -DECLARE_INSN(vfdiv_s, MATCH_VFDIV_S, MASK_VFDIV_S) -DECLARE_INSN(vfdiv_r_s, MATCH_VFDIV_R_S, MASK_VFDIV_R_S) -DECLARE_INSN(vfmin_s, MATCH_VFMIN_S, MASK_VFMIN_S) -DECLARE_INSN(vfmin_r_s, MATCH_VFMIN_R_S, MASK_VFMIN_R_S) -DECLARE_INSN(vfmax_s, MATCH_VFMAX_S, MASK_VFMAX_S) -DECLARE_INSN(vfmax_r_s, MATCH_VFMAX_R_S, MASK_VFMAX_R_S) -DECLARE_INSN(vfsqrt_s, MATCH_VFSQRT_S, MASK_VFSQRT_S) -DECLARE_INSN(vfmac_s, MATCH_VFMAC_S, MASK_VFMAC_S) -DECLARE_INSN(vfmac_r_s, MATCH_VFMAC_R_S, MASK_VFMAC_R_S) -DECLARE_INSN(vfmre_s, MATCH_VFMRE_S, MASK_VFMRE_S) -DECLARE_INSN(vfmre_r_s, MATCH_VFMRE_R_S, MASK_VFMRE_R_S) -DECLARE_INSN(vfclass_s, MATCH_VFCLASS_S, MASK_VFCLASS_S) -DECLARE_INSN(vfsgnj_s, MATCH_VFSGNJ_S, MASK_VFSGNJ_S) -DECLARE_INSN(vfsgnj_r_s, MATCH_VFSGNJ_R_S, MASK_VFSGNJ_R_S) -DECLARE_INSN(vfsgnjn_s, MATCH_VFSGNJN_S, MASK_VFSGNJN_S) -DECLARE_INSN(vfsgnjn_r_s, MATCH_VFSGNJN_R_S, MASK_VFSGNJN_R_S) -DECLARE_INSN(vfsgnjx_s, MATCH_VFSGNJX_S, MASK_VFSGNJX_S) -DECLARE_INSN(vfsgnjx_r_s, MATCH_VFSGNJX_R_S, MASK_VFSGNJX_R_S) -DECLARE_INSN(vfeq_s, MATCH_VFEQ_S, MASK_VFEQ_S) -DECLARE_INSN(vfeq_r_s, MATCH_VFEQ_R_S, MASK_VFEQ_R_S) -DECLARE_INSN(vfne_s, MATCH_VFNE_S, MASK_VFNE_S) -DECLARE_INSN(vfne_r_s, MATCH_VFNE_R_S, MASK_VFNE_R_S) -DECLARE_INSN(vflt_s, MATCH_VFLT_S, MASK_VFLT_S) -DECLARE_INSN(vflt_r_s, MATCH_VFLT_R_S, MASK_VFLT_R_S) -DECLARE_INSN(vfge_s, MATCH_VFGE_S, MASK_VFGE_S) -DECLARE_INSN(vfge_r_s, MATCH_VFGE_R_S, MASK_VFGE_R_S) -DECLARE_INSN(vfle_s, MATCH_VFLE_S, MASK_VFLE_S) -DECLARE_INSN(vfle_r_s, MATCH_VFLE_R_S, MASK_VFLE_R_S) -DECLARE_INSN(vfgt_s, MATCH_VFGT_S, MASK_VFGT_S) -DECLARE_INSN(vfgt_r_s, MATCH_VFGT_R_S, MASK_VFGT_R_S) -DECLARE_INSN(vfmv_x_s, MATCH_VFMV_X_S, MASK_VFMV_X_S) -DECLARE_INSN(vfmv_s_x, MATCH_VFMV_S_X, MASK_VFMV_S_X) -DECLARE_INSN(vfcvt_x_s, MATCH_VFCVT_X_S, MASK_VFCVT_X_S) -DECLARE_INSN(vfcvt_xu_s, MATCH_VFCVT_XU_S, MASK_VFCVT_XU_S) -DECLARE_INSN(vfcvt_s_x, MATCH_VFCVT_S_X, MASK_VFCVT_S_X) -DECLARE_INSN(vfcvt_s_xu, MATCH_VFCVT_S_XU, MASK_VFCVT_S_XU) -DECLARE_INSN(vfcpka_s_s, MATCH_VFCPKA_S_S, MASK_VFCPKA_S_S) -DECLARE_INSN(vfcpkb_s_s, MATCH_VFCPKB_S_S, MASK_VFCPKB_S_S) -DECLARE_INSN(vfcpkc_s_s, MATCH_VFCPKC_S_S, MASK_VFCPKC_S_S) -DECLARE_INSN(vfcpkd_s_s, MATCH_VFCPKD_S_S, MASK_VFCPKD_S_S) -DECLARE_INSN(vfcpka_s_d, MATCH_VFCPKA_S_D, MASK_VFCPKA_S_D) -DECLARE_INSN(vfcpkb_s_d, MATCH_VFCPKB_S_D, MASK_VFCPKB_S_D) -DECLARE_INSN(vfcpkc_s_d, MATCH_VFCPKC_S_D, MASK_VFCPKC_S_D) -DECLARE_INSN(vfcpkd_s_d, MATCH_VFCPKD_S_D, MASK_VFCPKD_S_D) -DECLARE_INSN(vfadd_h, MATCH_VFADD_H, MASK_VFADD_H) -DECLARE_INSN(vfadd_r_h, MATCH_VFADD_R_H, MASK_VFADD_R_H) -DECLARE_INSN(vfsub_h, MATCH_VFSUB_H, MASK_VFSUB_H) -DECLARE_INSN(vfsub_r_h, MATCH_VFSUB_R_H, MASK_VFSUB_R_H) -DECLARE_INSN(vfmul_h, MATCH_VFMUL_H, MASK_VFMUL_H) -DECLARE_INSN(vfmul_r_h, MATCH_VFMUL_R_H, MASK_VFMUL_R_H) -DECLARE_INSN(vfdiv_h, MATCH_VFDIV_H, MASK_VFDIV_H) -DECLARE_INSN(vfdiv_r_h, MATCH_VFDIV_R_H, MASK_VFDIV_R_H) -DECLARE_INSN(vfmin_h, MATCH_VFMIN_H, MASK_VFMIN_H) -DECLARE_INSN(vfmin_r_h, MATCH_VFMIN_R_H, MASK_VFMIN_R_H) -DECLARE_INSN(vfmax_h, MATCH_VFMAX_H, MASK_VFMAX_H) -DECLARE_INSN(vfmax_r_h, MATCH_VFMAX_R_H, MASK_VFMAX_R_H) -DECLARE_INSN(vfsqrt_h, MATCH_VFSQRT_H, MASK_VFSQRT_H) -DECLARE_INSN(vfmac_h, MATCH_VFMAC_H, MASK_VFMAC_H) -DECLARE_INSN(vfmac_r_h, MATCH_VFMAC_R_H, MASK_VFMAC_R_H) -DECLARE_INSN(vfmre_h, MATCH_VFMRE_H, MASK_VFMRE_H) -DECLARE_INSN(vfmre_r_h, MATCH_VFMRE_R_H, MASK_VFMRE_R_H) -DECLARE_INSN(vfclass_h, MATCH_VFCLASS_H, MASK_VFCLASS_H) -DECLARE_INSN(vfsgnj_h, MATCH_VFSGNJ_H, MASK_VFSGNJ_H) -DECLARE_INSN(vfsgnj_r_h, MATCH_VFSGNJ_R_H, MASK_VFSGNJ_R_H) -DECLARE_INSN(vfsgnjn_h, MATCH_VFSGNJN_H, MASK_VFSGNJN_H) -DECLARE_INSN(vfsgnjn_r_h, MATCH_VFSGNJN_R_H, MASK_VFSGNJN_R_H) -DECLARE_INSN(vfsgnjx_h, MATCH_VFSGNJX_H, MASK_VFSGNJX_H) -DECLARE_INSN(vfsgnjx_r_h, MATCH_VFSGNJX_R_H, MASK_VFSGNJX_R_H) -DECLARE_INSN(vfeq_h, MATCH_VFEQ_H, MASK_VFEQ_H) -DECLARE_INSN(vfeq_r_h, MATCH_VFEQ_R_H, MASK_VFEQ_R_H) -DECLARE_INSN(vfne_h, MATCH_VFNE_H, MASK_VFNE_H) -DECLARE_INSN(vfne_r_h, MATCH_VFNE_R_H, MASK_VFNE_R_H) -DECLARE_INSN(vflt_h, MATCH_VFLT_H, MASK_VFLT_H) -DECLARE_INSN(vflt_r_h, MATCH_VFLT_R_H, MASK_VFLT_R_H) -DECLARE_INSN(vfge_h, MATCH_VFGE_H, MASK_VFGE_H) -DECLARE_INSN(vfge_r_h, MATCH_VFGE_R_H, MASK_VFGE_R_H) -DECLARE_INSN(vfle_h, MATCH_VFLE_H, MASK_VFLE_H) -DECLARE_INSN(vfle_r_h, MATCH_VFLE_R_H, MASK_VFLE_R_H) -DECLARE_INSN(vfgt_h, MATCH_VFGT_H, MASK_VFGT_H) -DECLARE_INSN(vfgt_r_h, MATCH_VFGT_R_H, MASK_VFGT_R_H) -DECLARE_INSN(vfmv_x_h, MATCH_VFMV_X_H, MASK_VFMV_X_H) -DECLARE_INSN(vfmv_h_x, MATCH_VFMV_H_X, MASK_VFMV_H_X) -DECLARE_INSN(vfcvt_x_h, MATCH_VFCVT_X_H, MASK_VFCVT_X_H) -DECLARE_INSN(vfcvt_xu_h, MATCH_VFCVT_XU_H, MASK_VFCVT_XU_H) -DECLARE_INSN(vfcvt_h_x, MATCH_VFCVT_H_X, MASK_VFCVT_H_X) -DECLARE_INSN(vfcvt_h_xu, MATCH_VFCVT_H_XU, MASK_VFCVT_H_XU) -DECLARE_INSN(vfcpka_h_s, MATCH_VFCPKA_H_S, MASK_VFCPKA_H_S) -DECLARE_INSN(vfcpkb_h_s, MATCH_VFCPKB_H_S, MASK_VFCPKB_H_S) -DECLARE_INSN(vfcpkc_h_s, MATCH_VFCPKC_H_S, MASK_VFCPKC_H_S) -DECLARE_INSN(vfcpkd_h_s, MATCH_VFCPKD_H_S, MASK_VFCPKD_H_S) -DECLARE_INSN(vfcpka_h_d, MATCH_VFCPKA_H_D, MASK_VFCPKA_H_D) -DECLARE_INSN(vfcpkb_h_d, MATCH_VFCPKB_H_D, MASK_VFCPKB_H_D) -DECLARE_INSN(vfcpkc_h_d, MATCH_VFCPKC_H_D, MASK_VFCPKC_H_D) -DECLARE_INSN(vfcpkd_h_d, MATCH_VFCPKD_H_D, MASK_VFCPKD_H_D) -DECLARE_INSN(vfcvt_s_h, MATCH_VFCVT_S_H, MASK_VFCVT_S_H) -DECLARE_INSN(vfcvtu_s_h, MATCH_VFCVTU_S_H, MASK_VFCVTU_S_H) -DECLARE_INSN(vfcvt_h_s, MATCH_VFCVT_H_S, MASK_VFCVT_H_S) -DECLARE_INSN(vfcvtu_h_s, MATCH_VFCVTU_H_S, MASK_VFCVTU_H_S) -DECLARE_INSN(vfadd_ah, MATCH_VFADD_AH, MASK_VFADD_AH) -DECLARE_INSN(vfadd_r_ah, MATCH_VFADD_R_AH, MASK_VFADD_R_AH) -DECLARE_INSN(vfsub_ah, MATCH_VFSUB_AH, MASK_VFSUB_AH) -DECLARE_INSN(vfsub_r_ah, MATCH_VFSUB_R_AH, MASK_VFSUB_R_AH) -DECLARE_INSN(vfmul_ah, MATCH_VFMUL_AH, MASK_VFMUL_AH) -DECLARE_INSN(vfmul_r_ah, MATCH_VFMUL_R_AH, MASK_VFMUL_R_AH) -DECLARE_INSN(vfdiv_ah, MATCH_VFDIV_AH, MASK_VFDIV_AH) -DECLARE_INSN(vfdiv_r_ah, MATCH_VFDIV_R_AH, MASK_VFDIV_R_AH) -DECLARE_INSN(vfmin_ah, MATCH_VFMIN_AH, MASK_VFMIN_AH) -DECLARE_INSN(vfmin_r_ah, MATCH_VFMIN_R_AH, MASK_VFMIN_R_AH) -DECLARE_INSN(vfmax_ah, MATCH_VFMAX_AH, MASK_VFMAX_AH) -DECLARE_INSN(vfmax_r_ah, MATCH_VFMAX_R_AH, MASK_VFMAX_R_AH) -DECLARE_INSN(vfsqrt_ah, MATCH_VFSQRT_AH, MASK_VFSQRT_AH) -DECLARE_INSN(vfmac_ah, MATCH_VFMAC_AH, MASK_VFMAC_AH) -DECLARE_INSN(vfmac_r_ah, MATCH_VFMAC_R_AH, MASK_VFMAC_R_AH) -DECLARE_INSN(vfmre_ah, MATCH_VFMRE_AH, MASK_VFMRE_AH) -DECLARE_INSN(vfmre_r_ah, MATCH_VFMRE_R_AH, MASK_VFMRE_R_AH) -DECLARE_INSN(vfclass_ah, MATCH_VFCLASS_AH, MASK_VFCLASS_AH) -DECLARE_INSN(vfsgnj_ah, MATCH_VFSGNJ_AH, MASK_VFSGNJ_AH) -DECLARE_INSN(vfsgnj_r_ah, MATCH_VFSGNJ_R_AH, MASK_VFSGNJ_R_AH) -DECLARE_INSN(vfsgnjn_ah, MATCH_VFSGNJN_AH, MASK_VFSGNJN_AH) -DECLARE_INSN(vfsgnjn_r_ah, MATCH_VFSGNJN_R_AH, MASK_VFSGNJN_R_AH) -DECLARE_INSN(vfsgnjx_ah, MATCH_VFSGNJX_AH, MASK_VFSGNJX_AH) -DECLARE_INSN(vfsgnjx_r_ah, MATCH_VFSGNJX_R_AH, MASK_VFSGNJX_R_AH) -DECLARE_INSN(vfeq_ah, MATCH_VFEQ_AH, MASK_VFEQ_AH) -DECLARE_INSN(vfeq_r_ah, MATCH_VFEQ_R_AH, MASK_VFEQ_R_AH) -DECLARE_INSN(vfne_ah, MATCH_VFNE_AH, MASK_VFNE_AH) -DECLARE_INSN(vfne_r_ah, MATCH_VFNE_R_AH, MASK_VFNE_R_AH) -DECLARE_INSN(vflt_ah, MATCH_VFLT_AH, MASK_VFLT_AH) -DECLARE_INSN(vflt_r_ah, MATCH_VFLT_R_AH, MASK_VFLT_R_AH) -DECLARE_INSN(vfge_ah, MATCH_VFGE_AH, MASK_VFGE_AH) -DECLARE_INSN(vfge_r_ah, MATCH_VFGE_R_AH, MASK_VFGE_R_AH) -DECLARE_INSN(vfle_ah, MATCH_VFLE_AH, MASK_VFLE_AH) -DECLARE_INSN(vfle_r_ah, MATCH_VFLE_R_AH, MASK_VFLE_R_AH) -DECLARE_INSN(vfgt_ah, MATCH_VFGT_AH, MASK_VFGT_AH) -DECLARE_INSN(vfgt_r_ah, MATCH_VFGT_R_AH, MASK_VFGT_R_AH) -DECLARE_INSN(vfmv_x_ah, MATCH_VFMV_X_AH, MASK_VFMV_X_AH) -DECLARE_INSN(vfmv_ah_x, MATCH_VFMV_AH_X, MASK_VFMV_AH_X) -DECLARE_INSN(vfcvt_x_ah, MATCH_VFCVT_X_AH, MASK_VFCVT_X_AH) -DECLARE_INSN(vfcvt_xu_ah, MATCH_VFCVT_XU_AH, MASK_VFCVT_XU_AH) -DECLARE_INSN(vfcvt_ah_x, MATCH_VFCVT_AH_X, MASK_VFCVT_AH_X) -DECLARE_INSN(vfcvt_ah_xu, MATCH_VFCVT_AH_XU, MASK_VFCVT_AH_XU) -DECLARE_INSN(vfcpka_ah_s, MATCH_VFCPKA_AH_S, MASK_VFCPKA_AH_S) -DECLARE_INSN(vfcpkb_ah_s, MATCH_VFCPKB_AH_S, MASK_VFCPKB_AH_S) -DECLARE_INSN(vfcpkc_ah_s, MATCH_VFCPKC_AH_S, MASK_VFCPKC_AH_S) -DECLARE_INSN(vfcpkd_ah_s, MATCH_VFCPKD_AH_S, MASK_VFCPKD_AH_S) -DECLARE_INSN(vfcpka_ah_d, MATCH_VFCPKA_AH_D, MASK_VFCPKA_AH_D) -DECLARE_INSN(vfcpkb_ah_d, MATCH_VFCPKB_AH_D, MASK_VFCPKB_AH_D) -DECLARE_INSN(vfcpkc_ah_d, MATCH_VFCPKC_AH_D, MASK_VFCPKC_AH_D) -DECLARE_INSN(vfcpkd_ah_d, MATCH_VFCPKD_AH_D, MASK_VFCPKD_AH_D) -DECLARE_INSN(vfcvt_s_ah, MATCH_VFCVT_S_AH, MASK_VFCVT_S_AH) -DECLARE_INSN(vfcvtu_s_ah, MATCH_VFCVTU_S_AH, MASK_VFCVTU_S_AH) -DECLARE_INSN(vfcvt_ah_s, MATCH_VFCVT_AH_S, MASK_VFCVT_AH_S) -DECLARE_INSN(vfcvtu_ah_s, MATCH_VFCVTU_AH_S, MASK_VFCVTU_AH_S) -DECLARE_INSN(vfcvt_h_ah, MATCH_VFCVT_H_AH, MASK_VFCVT_H_AH) -DECLARE_INSN(vfcvtu_h_ah, MATCH_VFCVTU_H_AH, MASK_VFCVTU_H_AH) -DECLARE_INSN(vfcvt_ah_h, MATCH_VFCVT_AH_H, MASK_VFCVT_AH_H) -DECLARE_INSN(vfcvtu_ah_h, MATCH_VFCVTU_AH_H, MASK_VFCVTU_AH_H) -DECLARE_INSN(vfadd_b, MATCH_VFADD_B, MASK_VFADD_B) -DECLARE_INSN(vfadd_r_b, MATCH_VFADD_R_B, MASK_VFADD_R_B) -DECLARE_INSN(vfsub_b, MATCH_VFSUB_B, MASK_VFSUB_B) -DECLARE_INSN(vfsub_r_b, MATCH_VFSUB_R_B, MASK_VFSUB_R_B) -DECLARE_INSN(vfmul_b, MATCH_VFMUL_B, MASK_VFMUL_B) -DECLARE_INSN(vfmul_r_b, MATCH_VFMUL_R_B, MASK_VFMUL_R_B) -DECLARE_INSN(vfdiv_b, MATCH_VFDIV_B, MASK_VFDIV_B) -DECLARE_INSN(vfdiv_r_b, MATCH_VFDIV_R_B, MASK_VFDIV_R_B) -DECLARE_INSN(vfmin_b, MATCH_VFMIN_B, MASK_VFMIN_B) -DECLARE_INSN(vfmin_r_b, MATCH_VFMIN_R_B, MASK_VFMIN_R_B) -DECLARE_INSN(vfmax_b, MATCH_VFMAX_B, MASK_VFMAX_B) -DECLARE_INSN(vfmax_r_b, MATCH_VFMAX_R_B, MASK_VFMAX_R_B) -DECLARE_INSN(vfsqrt_b, MATCH_VFSQRT_B, MASK_VFSQRT_B) -DECLARE_INSN(vfmac_b, MATCH_VFMAC_B, MASK_VFMAC_B) -DECLARE_INSN(vfmac_r_b, MATCH_VFMAC_R_B, MASK_VFMAC_R_B) -DECLARE_INSN(vfmre_b, MATCH_VFMRE_B, MASK_VFMRE_B) -DECLARE_INSN(vfmre_r_b, MATCH_VFMRE_R_B, MASK_VFMRE_R_B) -DECLARE_INSN(vfsgnj_b, MATCH_VFSGNJ_B, MASK_VFSGNJ_B) -DECLARE_INSN(vfsgnj_r_b, MATCH_VFSGNJ_R_B, MASK_VFSGNJ_R_B) -DECLARE_INSN(vfsgnjn_b, MATCH_VFSGNJN_B, MASK_VFSGNJN_B) -DECLARE_INSN(vfsgnjn_r_b, MATCH_VFSGNJN_R_B, MASK_VFSGNJN_R_B) -DECLARE_INSN(vfsgnjx_b, MATCH_VFSGNJX_B, MASK_VFSGNJX_B) -DECLARE_INSN(vfsgnjx_r_b, MATCH_VFSGNJX_R_B, MASK_VFSGNJX_R_B) -DECLARE_INSN(vfeq_b, MATCH_VFEQ_B, MASK_VFEQ_B) -DECLARE_INSN(vfeq_r_b, MATCH_VFEQ_R_B, MASK_VFEQ_R_B) -DECLARE_INSN(vfne_b, MATCH_VFNE_B, MASK_VFNE_B) -DECLARE_INSN(vfne_r_b, MATCH_VFNE_R_B, MASK_VFNE_R_B) -DECLARE_INSN(vflt_b, MATCH_VFLT_B, MASK_VFLT_B) -DECLARE_INSN(vflt_r_b, MATCH_VFLT_R_B, MASK_VFLT_R_B) -DECLARE_INSN(vfge_b, MATCH_VFGE_B, MASK_VFGE_B) -DECLARE_INSN(vfge_r_b, MATCH_VFGE_R_B, MASK_VFGE_R_B) -DECLARE_INSN(vfle_b, MATCH_VFLE_B, MASK_VFLE_B) -DECLARE_INSN(vfle_r_b, MATCH_VFLE_R_B, MASK_VFLE_R_B) -DECLARE_INSN(vfgt_b, MATCH_VFGT_B, MASK_VFGT_B) -DECLARE_INSN(vfgt_r_b, MATCH_VFGT_R_B, MASK_VFGT_R_B) -DECLARE_INSN(vfmv_x_b, MATCH_VFMV_X_B, MASK_VFMV_X_B) -DECLARE_INSN(vfmv_b_x, MATCH_VFMV_B_X, MASK_VFMV_B_X) -DECLARE_INSN(vfclass_b, MATCH_VFCLASS_B, MASK_VFCLASS_B) -DECLARE_INSN(vfcvt_x_b, MATCH_VFCVT_X_B, MASK_VFCVT_X_B) -DECLARE_INSN(vfcvt_xu_b, MATCH_VFCVT_XU_B, MASK_VFCVT_XU_B) -DECLARE_INSN(vfcvt_b_x, MATCH_VFCVT_B_X, MASK_VFCVT_B_X) -DECLARE_INSN(vfcvt_b_xu, MATCH_VFCVT_B_XU, MASK_VFCVT_B_XU) -DECLARE_INSN(vfcpka_b_s, MATCH_VFCPKA_B_S, MASK_VFCPKA_B_S) -DECLARE_INSN(vfcpkb_b_s, MATCH_VFCPKB_B_S, MASK_VFCPKB_B_S) -DECLARE_INSN(vfcpkc_b_s, MATCH_VFCPKC_B_S, MASK_VFCPKC_B_S) -DECLARE_INSN(vfcpkd_b_s, MATCH_VFCPKD_B_S, MASK_VFCPKD_B_S) -DECLARE_INSN(vfcpka_b_d, MATCH_VFCPKA_B_D, MASK_VFCPKA_B_D) -DECLARE_INSN(vfcpkb_b_d, MATCH_VFCPKB_B_D, MASK_VFCPKB_B_D) -DECLARE_INSN(vfcpkc_b_d, MATCH_VFCPKC_B_D, MASK_VFCPKC_B_D) -DECLARE_INSN(vfcpkd_b_d, MATCH_VFCPKD_B_D, MASK_VFCPKD_B_D) -DECLARE_INSN(vfcvt_s_b, MATCH_VFCVT_S_B, MASK_VFCVT_S_B) -DECLARE_INSN(vfcvtu_s_b, MATCH_VFCVTU_S_B, MASK_VFCVTU_S_B) -DECLARE_INSN(vfcvt_b_s, MATCH_VFCVT_B_S, MASK_VFCVT_B_S) -DECLARE_INSN(vfcvtu_b_s, MATCH_VFCVTU_B_S, MASK_VFCVTU_B_S) -DECLARE_INSN(vfcvt_h_b, MATCH_VFCVT_H_B, MASK_VFCVT_H_B) -DECLARE_INSN(vfcvtu_h_b, MATCH_VFCVTU_H_B, MASK_VFCVTU_H_B) -DECLARE_INSN(vfcvt_b_h, MATCH_VFCVT_B_H, MASK_VFCVT_B_H) -DECLARE_INSN(vfcvtu_b_h, MATCH_VFCVTU_B_H, MASK_VFCVTU_B_H) -DECLARE_INSN(vfcvt_ah_b, MATCH_VFCVT_AH_B, MASK_VFCVT_AH_B) -DECLARE_INSN(vfcvtu_ah_b, MATCH_VFCVTU_AH_B, MASK_VFCVTU_AH_B) -DECLARE_INSN(vfcvt_b_ah, MATCH_VFCVT_B_AH, MASK_VFCVT_B_AH) -DECLARE_INSN(vfcvtu_b_ah, MATCH_VFCVTU_B_AH, MASK_VFCVTU_B_AH) -DECLARE_INSN(vfdotp_s, MATCH_VFDOTP_S, MASK_VFDOTP_S) -DECLARE_INSN(vfdotp_r_s, MATCH_VFDOTP_R_S, MASK_VFDOTP_R_S) -DECLARE_INSN(vfavg_s, MATCH_VFAVG_S, MASK_VFAVG_S) -DECLARE_INSN(vfavg_r_s, MATCH_VFAVG_R_S, MASK_VFAVG_R_S) -DECLARE_INSN(fmulex_s_h, MATCH_FMULEX_S_H, MASK_FMULEX_S_H) -DECLARE_INSN(fmacex_s_h, MATCH_FMACEX_S_H, MASK_FMACEX_S_H) -DECLARE_INSN(vfdotp_h, MATCH_VFDOTP_H, MASK_VFDOTP_H) -DECLARE_INSN(vfdotp_r_h, MATCH_VFDOTP_R_H, MASK_VFDOTP_R_H) -DECLARE_INSN(vfdotpex_s_h, MATCH_VFDOTPEX_S_H, MASK_VFDOTPEX_S_H) -DECLARE_INSN(vfdotpex_s_r_h, MATCH_VFDOTPEX_S_R_H, MASK_VFDOTPEX_S_R_H) -DECLARE_INSN(vfavg_h, MATCH_VFAVG_H, MASK_VFAVG_H) -DECLARE_INSN(vfavg_r_h, MATCH_VFAVG_R_H, MASK_VFAVG_R_H) -DECLARE_INSN(fmulex_s_ah, MATCH_FMULEX_S_AH, MASK_FMULEX_S_AH) -DECLARE_INSN(fmacex_s_ah, MATCH_FMACEX_S_AH, MASK_FMACEX_S_AH) -DECLARE_INSN(vfdotp_ah, MATCH_VFDOTP_AH, MASK_VFDOTP_AH) -DECLARE_INSN(vfdotp_r_ah, MATCH_VFDOTP_R_AH, MASK_VFDOTP_R_AH) -DECLARE_INSN(vfdotpex_s_ah, MATCH_VFDOTPEX_S_AH, MASK_VFDOTPEX_S_AH) -DECLARE_INSN(vfdotpex_s_r_ah, MATCH_VFDOTPEX_S_R_AH, MASK_VFDOTPEX_S_R_AH) -DECLARE_INSN(vfavg_ah, MATCH_VFAVG_AH, MASK_VFAVG_AH) -DECLARE_INSN(vfavg_r_ah, MATCH_VFAVG_R_AH, MASK_VFAVG_R_AH) -DECLARE_INSN(fmulex_s_b, MATCH_FMULEX_S_B, MASK_FMULEX_S_B) -DECLARE_INSN(fmacex_s_b, MATCH_FMACEX_S_B, MASK_FMACEX_S_B) -DECLARE_INSN(vfdotp_b, MATCH_VFDOTP_B, MASK_VFDOTP_B) -DECLARE_INSN(vfdotp_r_b, MATCH_VFDOTP_R_B, MASK_VFDOTP_R_B) -DECLARE_INSN(vfdotpex_s_b, MATCH_VFDOTPEX_S_B, MASK_VFDOTPEX_S_B) -DECLARE_INSN(vfdotpex_s_r_b, MATCH_VFDOTPEX_S_R_B, MASK_VFDOTPEX_S_R_B) -DECLARE_INSN(vfavg_b, MATCH_VFAVG_B, MASK_VFAVG_B) -DECLARE_INSN(vfavg_r_b, MATCH_VFAVG_R_B, MASK_VFAVG_R_B) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(ustatus, CSR_USTATUS) -DECLARE_CSR(uie, CSR_UIE) -DECLARE_CSR(utvec, CSR_UTVEC) -DECLARE_CSR(vstart, CSR_VSTART) -DECLARE_CSR(vxsat, CSR_VXSAT) -DECLARE_CSR(vxrm, CSR_VXRM) -DECLARE_CSR(vcsr, CSR_VCSR) -DECLARE_CSR(uscratch, CSR_USCRATCH) -DECLARE_CSR(uepc, CSR_UEPC) -DECLARE_CSR(ucause, CSR_UCAUSE) -DECLARE_CSR(utval, CSR_UTVAL) -DECLARE_CSR(uip, CSR_UIP) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(vl, CSR_VL) -DECLARE_CSR(vtype, CSR_VTYPE) -DECLARE_CSR(vlenb, CSR_VLENB) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sedeleg, CSR_SEDELEG) -DECLARE_CSR(sideleg, CSR_SIDELEG) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(stval, CSR_STVAL) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(satp, CSR_SATP) -DECLARE_CSR(vsstatus, CSR_VSSTATUS) -DECLARE_CSR(vsie, CSR_VSIE) -DECLARE_CSR(vstvec, CSR_VSTVEC) -DECLARE_CSR(vsscratch, CSR_VSSCRATCH) -DECLARE_CSR(vsepc, CSR_VSEPC) -DECLARE_CSR(vscause, CSR_VSCAUSE) -DECLARE_CSR(vstval, CSR_VSTVAL) -DECLARE_CSR(vsip, CSR_VSIP) -DECLARE_CSR(vsatp, CSR_VSATP) -DECLARE_CSR(hstatus, CSR_HSTATUS) -DECLARE_CSR(hedeleg, CSR_HEDELEG) -DECLARE_CSR(hideleg, CSR_HIDELEG) -DECLARE_CSR(hie, CSR_HIE) -DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) -DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) -DECLARE_CSR(hgeie, CSR_HGEIE) -DECLARE_CSR(htval, CSR_HTVAL) -DECLARE_CSR(hip, CSR_HIP) -DECLARE_CSR(hvip, CSR_HVIP) -DECLARE_CSR(htinst, CSR_HTINST) -DECLARE_CSR(hgatp, CSR_HGATP) -DECLARE_CSR(hgeip, CSR_HGEIP) -DECLARE_CSR(utvt, CSR_UTVT) -DECLARE_CSR(unxti, CSR_UNXTI) -DECLARE_CSR(uintstatus, CSR_UINTSTATUS) -DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) -DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) -DECLARE_CSR(stvt, CSR_STVT) -DECLARE_CSR(snxti, CSR_SNXTI) -DECLARE_CSR(sintstatus, CSR_SINTSTATUS) -DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) -DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) -DECLARE_CSR(mtvt, CSR_MTVT) -DECLARE_CSR(mnxti, CSR_MNXTI) -DECLARE_CSR(mintstatus, CSR_MINTSTATUS) -DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) -DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mtval, CSR_MTVAL) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(mtinst, CSR_MTINST) -DECLARE_CSR(mtval2, CSR_MTVAL2) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch0, CSR_DSCRATCH0) -DECLARE_CSR(dscratch1, CSR_DSCRATCH1) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(trace, CSR_TRACE) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mstatush, CSR_MSTATUSH) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) -DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) -DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) -DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) -#endif diff --git a/inst.sverilog b/inst.sverilog deleted file mode 100644 index dd6dff07..00000000 --- a/inst.sverilog +++ /dev/null @@ -1,1552 +0,0 @@ -/* Automatically generated by parse_opcodes */ -package riscv_instr; - localparam [31:0] CUSTOM0 = 32'b?????????????????000?????0001011; - localparam [31:0] CUSTOM0_RS1 = 32'b?????????????????010?????0001011; - localparam [31:0] CUSTOM0_RS1_RS2 = 32'b?????????????????011?????0001011; - localparam [31:0] CUSTOM0_RD = 32'b?????????????????100?????0001011; - localparam [31:0] CUSTOM0_RD_RS1 = 32'b?????????????????110?????0001011; - localparam [31:0] CUSTOM0_RD_RS1_RS2 = 32'b?????????????????111?????0001011; - localparam [31:0] CUSTOM1 = 32'b?????????????????000?????0101011; - localparam [31:0] CUSTOM1_RS1 = 32'b?????????????????010?????0101011; - localparam [31:0] CUSTOM1_RS1_RS2 = 32'b?????????????????011?????0101011; - localparam [31:0] CUSTOM1_RD = 32'b?????????????????100?????0101011; - localparam [31:0] CUSTOM1_RD_RS1 = 32'b?????????????????110?????0101011; - localparam [31:0] CUSTOM1_RD_RS1_RS2 = 32'b?????????????????111?????0101011; - localparam [31:0] CUSTOM2 = 32'b?????????????????000?????1011011; - localparam [31:0] CUSTOM2_RS1 = 32'b?????????????????010?????1011011; - localparam [31:0] CUSTOM2_RS1_RS2 = 32'b?????????????????011?????1011011; - localparam [31:0] CUSTOM2_RD = 32'b?????????????????100?????1011011; - localparam [31:0] CUSTOM2_RD_RS1 = 32'b?????????????????110?????1011011; - localparam [31:0] CUSTOM2_RD_RS1_RS2 = 32'b?????????????????111?????1011011; - localparam [31:0] CUSTOM3 = 32'b?????????????????000?????1111011; - localparam [31:0] CUSTOM3_RS1 = 32'b?????????????????010?????1111011; - localparam [31:0] CUSTOM3_RS1_RS2 = 32'b?????????????????011?????1111011; - localparam [31:0] CUSTOM3_RD = 32'b?????????????????100?????1111011; - localparam [31:0] CUSTOM3_RD_RS1 = 32'b?????????????????110?????1111011; - localparam [31:0] CUSTOM3_RD_RS1_RS2 = 32'b?????????????????111?????1111011; - localparam [31:0] SLLI_RV32 = 32'b0000000??????????001?????0010011; - localparam [31:0] SRLI_RV32 = 32'b0000000??????????101?????0010011; - localparam [31:0] SRAI_RV32 = 32'b0100000??????????101?????0010011; - localparam [31:0] FRFLAGS = 32'b00000000000100000010?????1110011; - localparam [31:0] FSFLAGS = 32'b000000000001?????001?????1110011; - localparam [31:0] FSFLAGSI = 32'b000000000001?????101?????1110011; - localparam [31:0] FRRM = 32'b00000000001000000010?????1110011; - localparam [31:0] FSRM = 32'b000000000010?????001?????1110011; - localparam [31:0] FSRMI = 32'b000000000010?????101?????1110011; - localparam [31:0] FSCSR = 32'b000000000011?????001?????1110011; - localparam [31:0] FRCSR = 32'b00000000001100000010?????1110011; - localparam [31:0] RDCYCLE = 32'b11000000000000000010?????1110011; - localparam [31:0] RDTIME = 32'b11000000000100000010?????1110011; - localparam [31:0] RDINSTRET = 32'b11000000001000000010?????1110011; - localparam [31:0] RDCYCLEH = 32'b11001000000000000010?????1110011; - localparam [31:0] RDTIMEH = 32'b11001000000100000010?????1110011; - localparam [31:0] RDINSTRETH = 32'b11001000001000000010?????1110011; - localparam [31:0] SCALL = 32'b00000000000000000000000001110011; - localparam [31:0] SBREAK = 32'b00000000000100000000000001110011; - localparam [31:0] FMV_X_S = 32'b111000000000?????000?????1010011; - localparam [31:0] FMV_S_X = 32'b111100000000?????000?????1010011; - localparam [31:0] FENCE_TSO = 32'b100000110011?????000?????0001111; - localparam [31:0] PAUSE = 32'b00000001000000000000000000001111; - localparam [31:0] AMOADD_W = 32'b00000????????????010?????0101111; - localparam [31:0] AMOXOR_W = 32'b00100????????????010?????0101111; - localparam [31:0] AMOOR_W = 32'b01000????????????010?????0101111; - localparam [31:0] AMOAND_W = 32'b01100????????????010?????0101111; - localparam [31:0] AMOMIN_W = 32'b10000????????????010?????0101111; - localparam [31:0] AMOMAX_W = 32'b10100????????????010?????0101111; - localparam [31:0] AMOMINU_W = 32'b11000????????????010?????0101111; - localparam [31:0] AMOMAXU_W = 32'b11100????????????010?????0101111; - localparam [31:0] AMOSWAP_W = 32'b00001????????????010?????0101111; - localparam [31:0] LR_W = 32'b00010??00000?????010?????0101111; - localparam [31:0] SC_W = 32'b00011????????????010?????0101111; - localparam [31:0] C_SRLI_RV32 = 32'b????????????????100000????????01; - localparam [31:0] C_SRAI_RV32 = 32'b????????????????100001????????01; - localparam [31:0] C_SLLI_RV32 = 32'b????????????????0000??????????10; - localparam [31:0] FADD_D = 32'b0000001??????????????????1010011; - localparam [31:0] FSUB_D = 32'b0000101??????????????????1010011; - localparam [31:0] FMUL_D = 32'b0001001??????????????????1010011; - localparam [31:0] FDIV_D = 32'b0001101??????????????????1010011; - localparam [31:0] FSGNJ_D = 32'b0010001??????????000?????1010011; - localparam [31:0] FSGNJN_D = 32'b0010001??????????001?????1010011; - localparam [31:0] FSGNJX_D = 32'b0010001??????????010?????1010011; - localparam [31:0] FMIN_D = 32'b0010101??????????000?????1010011; - localparam [31:0] FMAX_D = 32'b0010101??????????001?????1010011; - localparam [31:0] FCVT_S_D = 32'b010000000001?????????????1010011; - localparam [31:0] FCVT_D_S = 32'b010000100000?????????????1010011; - localparam [31:0] FSQRT_D = 32'b010110100000?????????????1010011; - localparam [31:0] FLE_D = 32'b1010001??????????000?????1010011; - localparam [31:0] FLT_D = 32'b1010001??????????001?????1010011; - localparam [31:0] FEQ_D = 32'b1010001??????????010?????1010011; - localparam [31:0] FCVT_W_D = 32'b110000100000?????????????1010011; - localparam [31:0] FCVT_WU_D = 32'b110000100001?????????????1010011; - localparam [31:0] FCLASS_D = 32'b111000100000?????001?????1010011; - localparam [31:0] FCVT_D_W = 32'b110100100000?????????????1010011; - localparam [31:0] FCVT_D_WU = 32'b110100100001?????????????1010011; - localparam [31:0] FLD = 32'b?????????????????011?????0000111; - localparam [31:0] FSD = 32'b?????????????????011?????0100111; - localparam [31:0] FMADD_D = 32'b?????01??????????????????1000011; - localparam [31:0] FMSUB_D = 32'b?????01??????????????????1000111; - localparam [31:0] FNMSUB_D = 32'b?????01??????????????????1001011; - localparam [31:0] FNMADD_D = 32'b?????01??????????????????1001111; - localparam [31:0] FCVT_H_D = 32'b010001000001?????????????1010011; - localparam [31:0] FCVT_D_H = 32'b010000100010?????????????1010011; - localparam [31:0] FADD_S = 32'b0000000??????????????????1010011; - localparam [31:0] FSUB_S = 32'b0000100??????????????????1010011; - localparam [31:0] FMUL_S = 32'b0001000??????????????????1010011; - localparam [31:0] FDIV_S = 32'b0001100??????????????????1010011; - localparam [31:0] FSGNJ_S = 32'b0010000??????????000?????1010011; - localparam [31:0] FSGNJN_S = 32'b0010000??????????001?????1010011; - localparam [31:0] FSGNJX_S = 32'b0010000??????????010?????1010011; - localparam [31:0] FMIN_S = 32'b0010100??????????000?????1010011; - localparam [31:0] FMAX_S = 32'b0010100??????????001?????1010011; - localparam [31:0] FSQRT_S = 32'b010110000000?????????????1010011; - localparam [31:0] FLE_S = 32'b1010000??????????000?????1010011; - localparam [31:0] FLT_S = 32'b1010000??????????001?????1010011; - localparam [31:0] FEQ_S = 32'b1010000??????????010?????1010011; - localparam [31:0] FCVT_W_S = 32'b110000000000?????????????1010011; - localparam [31:0] FCVT_WU_S = 32'b110000000001?????????????1010011; - localparam [31:0] FMV_X_W = 32'b111000000000?????000?????1010011; - localparam [31:0] FCLASS_S = 32'b111000000000?????001?????1010011; - localparam [31:0] FCVT_S_W = 32'b110100000000?????????????1010011; - localparam [31:0] FCVT_S_WU = 32'b110100000001?????????????1010011; - localparam [31:0] FMV_W_X = 32'b111100000000?????000?????1010011; - localparam [31:0] FLW = 32'b?????????????????010?????0000111; - localparam [31:0] FSW = 32'b?????????????????010?????0100111; - localparam [31:0] FMADD_S = 32'b?????00??????????????????1000011; - localparam [31:0] FMSUB_S = 32'b?????00??????????????????1000111; - localparam [31:0] FNMSUB_S = 32'b?????00??????????????????1001011; - localparam [31:0] FNMADD_S = 32'b?????00??????????????????1001111; - localparam [31:0] HFENCE_VVMA = 32'b0010001??????????000000001110011; - localparam [31:0] HFENCE_GVMA = 32'b0110001??????????000000001110011; - localparam [31:0] HLV_B = 32'b011000000000?????100?????1110011; - localparam [31:0] HLV_BU = 32'b011000000001?????100?????1110011; - localparam [31:0] HLV_H = 32'b011001000000?????100?????1110011; - localparam [31:0] HLV_HU = 32'b011001000001?????100?????1110011; - localparam [31:0] HLVX_HU = 32'b011001000011?????100?????1110011; - localparam [31:0] HLV_W = 32'b011010000000?????100?????1110011; - localparam [31:0] HLVX_WU = 32'b011010000011?????100?????1110011; - localparam [31:0] HSV_B = 32'b0110001??????????100000001110011; - localparam [31:0] HSV_H = 32'b0110011??????????100000001110011; - localparam [31:0] HSV_W = 32'b0110101??????????100000001110011; - localparam [31:0] BEQ = 32'b?????????????????000?????1100011; - localparam [31:0] BNE = 32'b?????????????????001?????1100011; - localparam [31:0] BLT = 32'b?????????????????100?????1100011; - localparam [31:0] BGE = 32'b?????????????????101?????1100011; - localparam [31:0] BLTU = 32'b?????????????????110?????1100011; - localparam [31:0] BGEU = 32'b?????????????????111?????1100011; - localparam [31:0] JALR = 32'b?????????????????000?????1100111; - localparam [31:0] JAL = 32'b?????????????????????????1101111; - localparam [31:0] LUI = 32'b?????????????????????????0110111; - localparam [31:0] AUIPC = 32'b?????????????????????????0010111; - localparam [31:0] ADDI = 32'b?????????????????000?????0010011; - localparam [31:0] SLLI = 32'b000000???????????001?????0010011; - localparam [31:0] SLTI = 32'b?????????????????010?????0010011; - localparam [31:0] SLTIU = 32'b?????????????????011?????0010011; - localparam [31:0] XORI = 32'b?????????????????100?????0010011; - localparam [31:0] SRLI = 32'b000000???????????101?????0010011; - localparam [31:0] SRAI = 32'b010000???????????101?????0010011; - localparam [31:0] ORI = 32'b?????????????????110?????0010011; - localparam [31:0] ANDI = 32'b?????????????????111?????0010011; - localparam [31:0] ADD = 32'b0000000??????????000?????0110011; - localparam [31:0] SUB = 32'b0100000??????????000?????0110011; - localparam [31:0] SLL = 32'b0000000??????????001?????0110011; - localparam [31:0] SLT = 32'b0000000??????????010?????0110011; - localparam [31:0] SLTU = 32'b0000000??????????011?????0110011; - localparam [31:0] XOR = 32'b0000000??????????100?????0110011; - localparam [31:0] SRL = 32'b0000000??????????101?????0110011; - localparam [31:0] SRA = 32'b0100000??????????101?????0110011; - localparam [31:0] OR = 32'b0000000??????????110?????0110011; - localparam [31:0] AND = 32'b0000000??????????111?????0110011; - localparam [31:0] LB = 32'b?????????????????000?????0000011; - localparam [31:0] LH = 32'b?????????????????001?????0000011; - localparam [31:0] LW = 32'b?????????????????010?????0000011; - localparam [31:0] LBU = 32'b?????????????????100?????0000011; - localparam [31:0] LHU = 32'b?????????????????101?????0000011; - localparam [31:0] SB = 32'b?????????????????000?????0100011; - localparam [31:0] SH = 32'b?????????????????001?????0100011; - localparam [31:0] SW = 32'b?????????????????010?????0100011; - localparam [31:0] FENCE = 32'b?????????????????000?????0001111; - localparam [31:0] FENCE_I = 32'b?????????????????001?????0001111; - localparam [31:0] MUL = 32'b0000001??????????000?????0110011; - localparam [31:0] MULH = 32'b0000001??????????001?????0110011; - localparam [31:0] MULHSU = 32'b0000001??????????010?????0110011; - localparam [31:0] MULHU = 32'b0000001??????????011?????0110011; - localparam [31:0] DIV = 32'b0000001??????????100?????0110011; - localparam [31:0] DIVU = 32'b0000001??????????101?????0110011; - localparam [31:0] REM = 32'b0000001??????????110?????0110011; - localparam [31:0] REMU = 32'b0000001??????????111?????0110011; - localparam [31:0] FADD_Q = 32'b0000011??????????????????1010011; - localparam [31:0] FSUB_Q = 32'b0000111??????????????????1010011; - localparam [31:0] FMUL_Q = 32'b0001011??????????????????1010011; - localparam [31:0] FDIV_Q = 32'b0001111??????????????????1010011; - localparam [31:0] FSGNJ_Q = 32'b0010011??????????000?????1010011; - localparam [31:0] FSGNJN_Q = 32'b0010011??????????001?????1010011; - localparam [31:0] FSGNJX_Q = 32'b0010011??????????010?????1010011; - localparam [31:0] FMIN_Q = 32'b0010111??????????000?????1010011; - localparam [31:0] FMAX_Q = 32'b0010111??????????001?????1010011; - localparam [31:0] FCVT_S_Q = 32'b010000000011?????????????1010011; - localparam [31:0] FCVT_Q_S = 32'b010001100000?????????????1010011; - localparam [31:0] FCVT_D_Q = 32'b010000100011?????????????1010011; - localparam [31:0] FCVT_Q_D = 32'b010001100001?????????????1010011; - localparam [31:0] FSQRT_Q = 32'b010111100000?????????????1010011; - localparam [31:0] FLE_Q = 32'b1010011??????????000?????1010011; - localparam [31:0] FLT_Q = 32'b1010011??????????001?????1010011; - localparam [31:0] FEQ_Q = 32'b1010011??????????010?????1010011; - localparam [31:0] FCVT_W_Q = 32'b110001100000?????????????1010011; - localparam [31:0] FCVT_WU_Q = 32'b110001100001?????????????1010011; - localparam [31:0] FCLASS_Q = 32'b111001100000?????001?????1010011; - localparam [31:0] FCVT_Q_W = 32'b110101100000?????????????1010011; - localparam [31:0] FCVT_Q_WU = 32'b110101100001?????????????1010011; - localparam [31:0] FLQ = 32'b?????????????????100?????0000111; - localparam [31:0] FSQ = 32'b?????????????????100?????0100111; - localparam [31:0] FMADD_Q = 32'b?????11??????????????????1000011; - localparam [31:0] FMSUB_Q = 32'b?????11??????????????????1000111; - localparam [31:0] FNMSUB_Q = 32'b?????11??????????????????1001011; - localparam [31:0] FNMADD_Q = 32'b?????11??????????????????1001111; - localparam [31:0] FCVT_H_Q = 32'b010001000011?????????????1010011; - localparam [31:0] FCVT_Q_H = 32'b010001100010?????????????1010011; - localparam [31:0] FADD_H = 32'b0000010??????????????????1010011; - localparam [31:0] FSUB_H = 32'b0000110??????????????????1010011; - localparam [31:0] FMUL_H = 32'b0001010??????????????????1010011; - localparam [31:0] FDIV_H = 32'b0001110??????????????????1010011; - localparam [31:0] FSGNJ_H = 32'b0010010??????????000?????1010011; - localparam [31:0] FSGNJN_H = 32'b0010010??????????001?????1010011; - localparam [31:0] FSGNJX_H = 32'b0010010??????????010?????1010011; - localparam [31:0] FMIN_H = 32'b0010110??????????000?????1010011; - localparam [31:0] FMAX_H = 32'b0010110??????????001?????1010011; - localparam [31:0] FCVT_H_S = 32'b010001000000?????????????1010011; - localparam [31:0] FCVT_S_H = 32'b010000000010?????????????1010011; - localparam [31:0] FSQRT_H = 32'b010111000000?????????????1010011; - localparam [31:0] FLE_H = 32'b1010010??????????000?????1010011; - localparam [31:0] FLT_H = 32'b1010010??????????001?????1010011; - localparam [31:0] FEQ_H = 32'b1010010??????????010?????1010011; - localparam [31:0] FCVT_W_H = 32'b110001000000?????????????1010011; - localparam [31:0] FCVT_WU_H = 32'b110001000001?????????????1010011; - localparam [31:0] FMV_X_H = 32'b111001000000?????000?????1010011; - localparam [31:0] FCLASS_H = 32'b111001000000?????001?????1010011; - localparam [31:0] FCVT_H_W = 32'b110101000000?????????????1010011; - localparam [31:0] FCVT_H_WU = 32'b110101000001?????????????1010011; - localparam [31:0] FMV_H_X = 32'b111101000000?????000?????1010011; - localparam [31:0] FLH = 32'b?????????????????001?????0000111; - localparam [31:0] FSH = 32'b?????????????????001?????0100111; - localparam [31:0] FMADD_H = 32'b?????10??????????????????1000011; - localparam [31:0] FMSUB_H = 32'b?????10??????????????????1000111; - localparam [31:0] FNMSUB_H = 32'b?????10??????????????????1001011; - localparam [31:0] FNMADD_H = 32'b?????10??????????????????1001111; - localparam [31:0] AMOADD_D = 32'b00000????????????011?????0101111; - localparam [31:0] AMOXOR_D = 32'b00100????????????011?????0101111; - localparam [31:0] AMOOR_D = 32'b01000????????????011?????0101111; - localparam [31:0] AMOAND_D = 32'b01100????????????011?????0101111; - localparam [31:0] AMOMIN_D = 32'b10000????????????011?????0101111; - localparam [31:0] AMOMAX_D = 32'b10100????????????011?????0101111; - localparam [31:0] AMOMINU_D = 32'b11000????????????011?????0101111; - localparam [31:0] AMOMAXU_D = 32'b11100????????????011?????0101111; - localparam [31:0] AMOSWAP_D = 32'b00001????????????011?????0101111; - localparam [31:0] LR_D = 32'b00010??00000?????011?????0101111; - localparam [31:0] SC_D = 32'b00011????????????011?????0101111; - localparam [31:0] C_LD = 32'b????????????????011???????????00; - localparam [31:0] C_SD = 32'b????????????????111???????????00; - localparam [31:0] C_SUBW = 32'b????????????????100111???00???01; - localparam [31:0] C_ADDW = 32'b????????????????100111???01???01; - localparam [31:0] C_ADDIW = 32'b????????????????001???????????01; - localparam [31:0] C_LDSP = 32'b????????????????011???????????10; - localparam [31:0] C_SDSP = 32'b????????????????111???????????10; - localparam [31:0] FCVT_L_D = 32'b110000100010?????????????1010011; - localparam [31:0] FCVT_LU_D = 32'b110000100011?????????????1010011; - localparam [31:0] FMV_X_D = 32'b111000100000?????000?????1010011; - localparam [31:0] FCVT_D_L = 32'b110100100010?????????????1010011; - localparam [31:0] FCVT_D_LU = 32'b110100100011?????????????1010011; - localparam [31:0] FMV_D_X = 32'b111100100000?????000?????1010011; - localparam [31:0] FCVT_L_S = 32'b110000000010?????????????1010011; - localparam [31:0] FCVT_LU_S = 32'b110000000011?????????????1010011; - localparam [31:0] FCVT_S_L = 32'b110100000010?????????????1010011; - localparam [31:0] FCVT_S_LU = 32'b110100000011?????????????1010011; - localparam [31:0] HLV_WU = 32'b011010000001?????100?????1110011; - localparam [31:0] HLV_D = 32'b011011000000?????100?????1110011; - localparam [31:0] HSV_D = 32'b0110111??????????100000001110011; - localparam [31:0] ADDIW = 32'b?????????????????000?????0011011; - localparam [31:0] SLLIW = 32'b0000000??????????001?????0011011; - localparam [31:0] SRLIW = 32'b0000000??????????101?????0011011; - localparam [31:0] SRAIW = 32'b0100000??????????101?????0011011; - localparam [31:0] ADDW = 32'b0000000??????????000?????0111011; - localparam [31:0] SUBW = 32'b0100000??????????000?????0111011; - localparam [31:0] SLLW = 32'b0000000??????????001?????0111011; - localparam [31:0] SRLW = 32'b0000000??????????101?????0111011; - localparam [31:0] SRAW = 32'b0100000??????????101?????0111011; - localparam [31:0] LD = 32'b?????????????????011?????0000011; - localparam [31:0] LWU = 32'b?????????????????110?????0000011; - localparam [31:0] SD = 32'b?????????????????011?????0100011; - localparam [31:0] MULW = 32'b0000001??????????000?????0111011; - localparam [31:0] DIVW = 32'b0000001??????????100?????0111011; - localparam [31:0] DIVUW = 32'b0000001??????????101?????0111011; - localparam [31:0] REMW = 32'b0000001??????????110?????0111011; - localparam [31:0] REMUW = 32'b0000001??????????111?????0111011; - localparam [31:0] FCVT_L_Q = 32'b110001100010?????????????1010011; - localparam [31:0] FCVT_LU_Q = 32'b110001100011?????????????1010011; - localparam [31:0] FCVT_Q_L = 32'b110101100010?????????????1010011; - localparam [31:0] FCVT_Q_LU = 32'b110101100011?????????????1010011; - localparam [31:0] FCVT_L_H = 32'b110001000010?????????????1010011; - localparam [31:0] FCVT_LU_H = 32'b110001000011?????????????1010011; - localparam [31:0] FCVT_H_L = 32'b110101000010?????????????1010011; - localparam [31:0] FCVT_H_LU = 32'b110101000011?????????????1010011; - localparam [31:0] C_NOP = 32'b????????????????0000000000000001; - localparam [31:0] C_ADDI16SP = 32'b????????????????011?00010?????01; - localparam [31:0] C_JR = 32'b????????????????1000?????0000010; - localparam [31:0] C_JALR = 32'b????????????????1001?????0000010; - localparam [31:0] C_EBREAK = 32'b????????????????1001000000000010; - localparam [31:0] C_ADDI4SPN = 32'b????????????????000???????????00; - localparam [31:0] C_FLD = 32'b????????????????001???????????00; - localparam [31:0] C_LW = 32'b????????????????010???????????00; - localparam [31:0] C_FLW = 32'b????????????????011???????????00; - localparam [31:0] C_FSD = 32'b????????????????101???????????00; - localparam [31:0] C_SW = 32'b????????????????110???????????00; - localparam [31:0] C_FSW = 32'b????????????????111???????????00; - localparam [31:0] C_ADDI = 32'b????????????????000???????????01; - localparam [31:0] C_JAL = 32'b????????????????001???????????01; - localparam [31:0] C_LI = 32'b????????????????010???????????01; - localparam [31:0] C_LUI = 32'b????????????????011???????????01; - localparam [31:0] C_SRLI = 32'b????????????????100?00????????01; - localparam [31:0] C_SRAI = 32'b????????????????100?01????????01; - localparam [31:0] C_ANDI = 32'b????????????????100?10????????01; - localparam [31:0] C_SUB = 32'b????????????????100011???00???01; - localparam [31:0] C_XOR = 32'b????????????????100011???01???01; - localparam [31:0] C_OR = 32'b????????????????100011???10???01; - localparam [31:0] C_AND = 32'b????????????????100011???11???01; - localparam [31:0] C_J = 32'b????????????????101???????????01; - localparam [31:0] C_BEQZ = 32'b????????????????110???????????01; - localparam [31:0] C_BNEZ = 32'b????????????????111???????????01; - localparam [31:0] C_SLLI = 32'b????????????????000???????????10; - localparam [31:0] C_FLDSP = 32'b????????????????001???????????10; - localparam [31:0] C_LWSP = 32'b????????????????010???????????10; - localparam [31:0] C_FLWSP = 32'b????????????????011???????????10; - localparam [31:0] C_MV = 32'b????????????????1000??????????10; - localparam [31:0] C_ADD = 32'b????????????????1001??????????10; - localparam [31:0] C_FSDSP = 32'b????????????????101???????????10; - localparam [31:0] C_SWSP = 32'b????????????????110???????????10; - localparam [31:0] C_FSWSP = 32'b????????????????111???????????10; - localparam [31:0] VSETVLI = 32'b0????????????????111?????1010111; - localparam [31:0] VLE8_V = 32'b???000?00000?????000?????0000111; - localparam [31:0] VLE16_V = 32'b???000?00000?????101?????0000111; - localparam [31:0] VLE32_V = 32'b???000?00000?????110?????0000111; - localparam [31:0] VLE64_V = 32'b???000?00000?????111?????0000111; - localparam [31:0] VLE128_V = 32'b???100?00000?????000?????0000111; - localparam [31:0] VLE256_V = 32'b???100?00000?????101?????0000111; - localparam [31:0] VLE512_V = 32'b???100?00000?????110?????0000111; - localparam [31:0] VLE1024_V = 32'b???100?00000?????111?????0000111; - localparam [31:0] VSE8_V = 32'b???000?00000?????000?????0100111; - localparam [31:0] VSE16_V = 32'b???000?00000?????101?????0100111; - localparam [31:0] VSE32_V = 32'b???000?00000?????110?????0100111; - localparam [31:0] VSE64_V = 32'b???000?00000?????111?????0100111; - localparam [31:0] VSE128_V = 32'b???100?00000?????000?????0100111; - localparam [31:0] VSE256_V = 32'b???100?00000?????101?????0100111; - localparam [31:0] VSE512_V = 32'b???100?00000?????110?????0100111; - localparam [31:0] VSE1024_V = 32'b???100?00000?????111?????0100111; - localparam [31:0] VLSE8_V = 32'b???010???????????000?????0000111; - localparam [31:0] VLSE16_V = 32'b???010???????????101?????0000111; - localparam [31:0] VLSE32_V = 32'b???010???????????110?????0000111; - localparam [31:0] VLSE64_V = 32'b???010???????????111?????0000111; - localparam [31:0] VLSE128_V = 32'b???110???????????000?????0000111; - localparam [31:0] VLSE256_V = 32'b???110???????????101?????0000111; - localparam [31:0] VLSE512_V = 32'b???110???????????110?????0000111; - localparam [31:0] VLSE1024_V = 32'b???110???????????111?????0000111; - localparam [31:0] VSSE8_V = 32'b???010???????????000?????0100111; - localparam [31:0] VSSE16_V = 32'b???010???????????101?????0100111; - localparam [31:0] VSSE32_V = 32'b???010???????????110?????0100111; - localparam [31:0] VSSE64_V = 32'b???010???????????111?????0100111; - localparam [31:0] VSSE128_V = 32'b???110???????????000?????0100111; - localparam [31:0] VSSE256_V = 32'b???110???????????101?????0100111; - localparam [31:0] VSSE512_V = 32'b???110???????????110?????0100111; - localparam [31:0] VSSE1024_V = 32'b???110???????????111?????0100111; - localparam [31:0] VLXEI8_V = 32'b???011???????????000?????0000111; - localparam [31:0] VLXEI16_V = 32'b???011???????????101?????0000111; - localparam [31:0] VLXEI32_V = 32'b???011???????????110?????0000111; - localparam [31:0] VLXEI64_V = 32'b???011???????????111?????0000111; - localparam [31:0] VLXEI128_V = 32'b???111???????????000?????0000111; - localparam [31:0] VLXEI256_V = 32'b???111???????????101?????0000111; - localparam [31:0] VLXEI512_V = 32'b???111???????????110?????0000111; - localparam [31:0] VLXEI1024_V = 32'b???111???????????111?????0000111; - localparam [31:0] VSXEI8_V = 32'b???011???????????000?????0100111; - localparam [31:0] VSXEI16_V = 32'b???011???????????101?????0100111; - localparam [31:0] VSXEI32_V = 32'b???011???????????110?????0100111; - localparam [31:0] VSXEI64_V = 32'b???011???????????111?????0100111; - localparam [31:0] VSXEI128_V = 32'b???111???????????000?????0100111; - localparam [31:0] VSXEI256_V = 32'b???111???????????101?????0100111; - localparam [31:0] VSXEI512_V = 32'b???111???????????110?????0100111; - localparam [31:0] VSXEI1024_V = 32'b???111???????????111?????0100111; - localparam [31:0] VSUXEI8_V = 32'b???001???????????000?????0100111; - localparam [31:0] VSUXEI16_V = 32'b???001???????????101?????0100111; - localparam [31:0] VSUXEI32_V = 32'b???001???????????110?????0100111; - localparam [31:0] VSUXEI64_V = 32'b???001???????????111?????0100111; - localparam [31:0] VSUXEI128_V = 32'b???101???????????000?????0100111; - localparam [31:0] VSUXEI256_V = 32'b???101???????????101?????0100111; - localparam [31:0] VSUXEI512_V = 32'b???101???????????110?????0100111; - localparam [31:0] VSUXEI1024_V = 32'b???101???????????111?????0100111; - localparam [31:0] VLE8FF_V = 32'b???000?10000?????000?????0000111; - localparam [31:0] VLE16FF_V = 32'b???000?10000?????101?????0000111; - localparam [31:0] VLE32FF_V = 32'b???000?10000?????110?????0000111; - localparam [31:0] VLE64FF_V = 32'b???000?10000?????111?????0000111; - localparam [31:0] VLE128FF_V = 32'b???100?10000?????000?????0000111; - localparam [31:0] VLE256FF_V = 32'b???100?10000?????101?????0000111; - localparam [31:0] VLE512FF_V = 32'b???100?10000?????110?????0000111; - localparam [31:0] VLE1024FF_V = 32'b???100?10000?????111?????0000111; - localparam [31:0] VL1RE8_V = 32'b000000101000?????000?????0000111; - localparam [31:0] VL1RE16_V = 32'b000000101000?????101?????0000111; - localparam [31:0] VL1RE32_V = 32'b000000101000?????110?????0000111; - localparam [31:0] VL1RE64_V = 32'b000000101000?????111?????0000111; - localparam [31:0] VL2RE8_V = 32'b001000101000?????000?????0000111; - localparam [31:0] VL2RE16_V = 32'b001000101000?????101?????0000111; - localparam [31:0] VL2RE32_V = 32'b001000101000?????110?????0000111; - localparam [31:0] VL2RE64_V = 32'b001000101000?????111?????0000111; - localparam [31:0] VL4RE8_V = 32'b011000101000?????000?????0000111; - localparam [31:0] VL4RE16_V = 32'b011000101000?????101?????0000111; - localparam [31:0] VL4RE32_V = 32'b011000101000?????110?????0000111; - localparam [31:0] VL4RE64_V = 32'b011000101000?????111?????0000111; - localparam [31:0] VL8RE8_V = 32'b111000101000?????000?????0000111; - localparam [31:0] VL8RE16_V = 32'b111000101000?????101?????0000111; - localparam [31:0] VL8RE32_V = 32'b111000101000?????110?????0000111; - localparam [31:0] VL8RE64_V = 32'b111000101000?????111?????0000111; - localparam [31:0] VS1R_V = 32'b000000101000?????000?????0100111; - localparam [31:0] VS2R_V = 32'b001000101000?????000?????0100111; - localparam [31:0] VS4R_V = 32'b011000101000?????000?????0100111; - localparam [31:0] VS8R_V = 32'b111000101000?????000?????0100111; - localparam [31:0] VFADD_VF = 32'b000000???????????101?????1010111; - localparam [31:0] VFSUB_VF = 32'b000010???????????101?????1010111; - localparam [31:0] VFMIN_VF = 32'b000100???????????101?????1010111; - localparam [31:0] VFMAX_VF = 32'b000110???????????101?????1010111; - localparam [31:0] VFSGNJ_VF = 32'b001000???????????101?????1010111; - localparam [31:0] VFSGNJN_VF = 32'b001001???????????101?????1010111; - localparam [31:0] VFSGNJX_VF = 32'b001010???????????101?????1010111; - localparam [31:0] VFSLIDE1UP_VF = 32'b001110???????????101?????1010111; - localparam [31:0] VFSLIDE1DOWN_VF = 32'b001111???????????101?????1010111; - localparam [31:0] VFMV_S_F = 32'b010000100000?????101?????1010111; - localparam [31:0] VFMERGE_VFM = 32'b0101110??????????101?????1010111; - localparam [31:0] VFMV_V_F = 32'b010111100000?????101?????1010111; - localparam [31:0] VMFEQ_VF = 32'b011000???????????101?????1010111; - localparam [31:0] VMFLE_VF = 32'b011001???????????101?????1010111; - localparam [31:0] VMFLT_VF = 32'b011011???????????101?????1010111; - localparam [31:0] VMFNE_VF = 32'b011100???????????101?????1010111; - localparam [31:0] VMFGT_VF = 32'b011101???????????101?????1010111; - localparam [31:0] VMFGE_VF = 32'b011111???????????101?????1010111; - localparam [31:0] VFDIV_VF = 32'b100000???????????101?????1010111; - localparam [31:0] VFRDIV_VF = 32'b100001???????????101?????1010111; - localparam [31:0] VFMUL_VF = 32'b100100???????????101?????1010111; - localparam [31:0] VFRSUB_VF = 32'b100111???????????101?????1010111; - localparam [31:0] VFMADD_VF = 32'b101000???????????101?????1010111; - localparam [31:0] VFNMADD_VF = 32'b101001???????????101?????1010111; - localparam [31:0] VFMSUB_VF = 32'b101010???????????101?????1010111; - localparam [31:0] VFNMSUB_VF = 32'b101011???????????101?????1010111; - localparam [31:0] VFMACC_VF = 32'b101100???????????101?????1010111; - localparam [31:0] VFNMACC_VF = 32'b101101???????????101?????1010111; - localparam [31:0] VFMSAC_VF = 32'b101110???????????101?????1010111; - localparam [31:0] VFNMSAC_VF = 32'b101111???????????101?????1010111; - localparam [31:0] VFWADD_VF = 32'b110000???????????101?????1010111; - localparam [31:0] VFWSUB_VF = 32'b110010???????????101?????1010111; - localparam [31:0] VFWADD_WF = 32'b110100???????????101?????1010111; - localparam [31:0] VFWSUB_WF = 32'b110110???????????101?????1010111; - localparam [31:0] VFWMUL_VF = 32'b111000???????????101?????1010111; - localparam [31:0] VFWMACC_VF = 32'b111100???????????101?????1010111; - localparam [31:0] VFWNMACC_VF = 32'b111101???????????101?????1010111; - localparam [31:0] VFWMSAC_VF = 32'b111110???????????101?????1010111; - localparam [31:0] VFWNMSAC_VF = 32'b111111???????????101?????1010111; - localparam [31:0] VFADD_VV = 32'b000000???????????001?????1010111; - localparam [31:0] VFREDSUM_VS = 32'b000001???????????001?????1010111; - localparam [31:0] VFSUB_VV = 32'b000010???????????001?????1010111; - localparam [31:0] VFREDOSUM_VS = 32'b000011???????????001?????1010111; - localparam [31:0] VFMIN_VV = 32'b000100???????????001?????1010111; - localparam [31:0] VFREDMIN_VS = 32'b000101???????????001?????1010111; - localparam [31:0] VFMAX_VV = 32'b000110???????????001?????1010111; - localparam [31:0] VFREDMAX_VS = 32'b000111???????????001?????1010111; - localparam [31:0] VFSGNJ_VV = 32'b001000???????????001?????1010111; - localparam [31:0] VFSGNJN_VV = 32'b001001???????????001?????1010111; - localparam [31:0] VFSGNJX_VV = 32'b001010???????????001?????1010111; - localparam [31:0] VFMV_F_S = 32'b0100001?????00000001?????1010111; - localparam [31:0] VMFEQ_VV = 32'b011000???????????001?????1010111; - localparam [31:0] VMFLE_VV = 32'b011001???????????001?????1010111; - localparam [31:0] VMFLT_VV = 32'b011011???????????001?????1010111; - localparam [31:0] VMFNE_VV = 32'b011100???????????001?????1010111; - localparam [31:0] VFDIV_VV = 32'b100000???????????001?????1010111; - localparam [31:0] VFMUL_VV = 32'b100100???????????001?????1010111; - localparam [31:0] VFMADD_VV = 32'b101000???????????001?????1010111; - localparam [31:0] VFNMADD_VV = 32'b101001???????????001?????1010111; - localparam [31:0] VFMSUB_VV = 32'b101010???????????001?????1010111; - localparam [31:0] VFNMSUB_VV = 32'b101011???????????001?????1010111; - localparam [31:0] VFMACC_VV = 32'b101100???????????001?????1010111; - localparam [31:0] VFNMACC_VV = 32'b101101???????????001?????1010111; - localparam [31:0] VFMSAC_VV = 32'b101110???????????001?????1010111; - localparam [31:0] VFNMSAC_VV = 32'b101111???????????001?????1010111; - localparam [31:0] VFCVT_XU_F_V = 32'b010010??????00000001?????1010111; - localparam [31:0] VFCVT_F_XU_V = 32'b010010??????00010001?????1010111; - localparam [31:0] VFCVT_F_X_V = 32'b010010??????00011001?????1010111; - localparam [31:0] VFCVT_RTZ_XU_F_V = 32'b010010??????00110001?????1010111; - localparam [31:0] VFCVT_RTZ_X_F_V = 32'b010010??????00111001?????1010111; - localparam [31:0] VFWCVT_XU_F_V = 32'b010010??????01000001?????1010111; - localparam [31:0] VFWCVT_X_F_V = 32'b010010??????01001001?????1010111; - localparam [31:0] VFWCVT_F_XU_V = 32'b010010??????01010001?????1010111; - localparam [31:0] VFWCVT_F_X_V = 32'b010010??????01011001?????1010111; - localparam [31:0] VFWCVT_F_F_V = 32'b010010??????01100001?????1010111; - localparam [31:0] VFWCVT_RTZ_XU_F_V = 32'b010010??????01110001?????1010111; - localparam [31:0] VFWCVT_RTZ_X_F_V = 32'b010010??????01111001?????1010111; - localparam [31:0] VFNCVT_XU_F_W = 32'b010010??????10000001?????1010111; - localparam [31:0] VFNCVT_X_F_W = 32'b010010??????10001001?????1010111; - localparam [31:0] VFNCVT_F_XU_W = 32'b010010??????10010001?????1010111; - localparam [31:0] VFNCVT_F_X_W = 32'b010010??????10011001?????1010111; - localparam [31:0] VFNCVT_F_F_W = 32'b010010??????10100001?????1010111; - localparam [31:0] VFNCVT_ROD_F_F_W = 32'b010010??????10101001?????1010111; - localparam [31:0] VFNCVT_RTZ_XU_F_W = 32'b010010??????10110001?????1010111; - localparam [31:0] VFNCVT_RTZ_X_F_W = 32'b010010??????10111001?????1010111; - localparam [31:0] VFSQRT_V = 32'b010011??????00000001?????1010111; - localparam [31:0] VFRSQRTE7_V = 32'b010011??????00100001?????1010111; - localparam [31:0] VFRECE7_V = 32'b010011??????00101001?????1010111; - localparam [31:0] VFCLASS_V = 32'b010011??????10000001?????1010111; - localparam [31:0] VFWADD_VV = 32'b110000???????????001?????1010111; - localparam [31:0] VFWREDSUM_VS = 32'b110001???????????001?????1010111; - localparam [31:0] VFWSUB_VV = 32'b110010???????????001?????1010111; - localparam [31:0] VFWREDOSUM_VS = 32'b110011???????????001?????1010111; - localparam [31:0] VFWADD_WV = 32'b110100???????????001?????1010111; - localparam [31:0] VFWSUB_WV = 32'b110110???????????001?????1010111; - localparam [31:0] VFWMUL_VV = 32'b111000???????????001?????1010111; - localparam [31:0] VFDOT_VV = 32'b111001???????????001?????1010111; - localparam [31:0] VFWMACC_VV = 32'b111100???????????001?????1010111; - localparam [31:0] VFWNMACC_VV = 32'b111101???????????001?????1010111; - localparam [31:0] VFWMSAC_VV = 32'b111110???????????001?????1010111; - localparam [31:0] VFWNMSAC_VV = 32'b111111???????????001?????1010111; - localparam [31:0] VADD_VX = 32'b000000???????????100?????1010111; - localparam [31:0] VSUB_VX = 32'b000010???????????100?????1010111; - localparam [31:0] VRSUB_VX = 32'b000011???????????100?????1010111; - localparam [31:0] VMINU_VX = 32'b000100???????????100?????1010111; - localparam [31:0] VMIN_VX = 32'b000101???????????100?????1010111; - localparam [31:0] VMAXU_VX = 32'b000110???????????100?????1010111; - localparam [31:0] VMAX_VX = 32'b000111???????????100?????1010111; - localparam [31:0] VAND_VX = 32'b001001???????????100?????1010111; - localparam [31:0] VOR_VX = 32'b001010???????????100?????1010111; - localparam [31:0] VXOR_VX = 32'b001011???????????100?????1010111; - localparam [31:0] VRGATHER_VX = 32'b001100???????????100?????1010111; - localparam [31:0] VSLIDEUP_VX = 32'b001110???????????100?????1010111; - localparam [31:0] VSLIDEDOWN_VX = 32'b001111???????????100?????1010111; - localparam [31:0] VMADC_VXM = 32'b010001???????????100?????1010111; - localparam [31:0] VMSBC_VXM = 32'b010011???????????100?????1010111; - localparam [31:0] VMERGE_VXM = 32'b0101110??????????100?????1010111; - localparam [31:0] VMV_V_X = 32'b010111100000?????100?????1010111; - localparam [31:0] VMSEQ_VX = 32'b011000???????????100?????1010111; - localparam [31:0] VMSNE_VX = 32'b011001???????????100?????1010111; - localparam [31:0] VMSLTU_VX = 32'b011010???????????100?????1010111; - localparam [31:0] VMSLT_VX = 32'b011011???????????100?????1010111; - localparam [31:0] VMSLEU_VX = 32'b011100???????????100?????1010111; - localparam [31:0] VMSLE_VX = 32'b011101???????????100?????1010111; - localparam [31:0] VMSGTU_VX = 32'b011110???????????100?????1010111; - localparam [31:0] VMSGT_VX = 32'b011111???????????100?????1010111; - localparam [31:0] VSADDU_VX = 32'b100000???????????100?????1010111; - localparam [31:0] VSADD_VX = 32'b100001???????????100?????1010111; - localparam [31:0] VSSUBU_VX = 32'b100010???????????100?????1010111; - localparam [31:0] VSSUB_VX = 32'b100011???????????100?????1010111; - localparam [31:0] VSLL_VX = 32'b100101???????????100?????1010111; - localparam [31:0] VSMUL_VX = 32'b100111???????????100?????1010111; - localparam [31:0] VSRL_VX = 32'b101000???????????100?????1010111; - localparam [31:0] VSRA_VX = 32'b101001???????????100?????1010111; - localparam [31:0] VSSRL_VX = 32'b101010???????????100?????1010111; - localparam [31:0] VSSRA_VX = 32'b101011???????????100?????1010111; - localparam [31:0] VNSRL_WX = 32'b101100???????????100?????1010111; - localparam [31:0] VNSRA_WX = 32'b101101???????????100?????1010111; - localparam [31:0] VNCLIPU_WX = 32'b101110???????????100?????1010111; - localparam [31:0] VNCLIP_WX = 32'b101111???????????100?????1010111; - localparam [31:0] VQMACCU_VX = 32'b111100???????????100?????1010111; - localparam [31:0] VQMACC_VX = 32'b111101???????????100?????1010111; - localparam [31:0] VQMACCUS_VX = 32'b111110???????????100?????1010111; - localparam [31:0] VQMACCSU_VX = 32'b111111???????????100?????1010111; - localparam [31:0] VADD_VV = 32'b000000???????????000?????1010111; - localparam [31:0] VSUB_VV = 32'b000010???????????000?????1010111; - localparam [31:0] VMINU_VV = 32'b000100???????????000?????1010111; - localparam [31:0] VMIN_VV = 32'b000101???????????000?????1010111; - localparam [31:0] VMAXU_VV = 32'b000110???????????000?????1010111; - localparam [31:0] VMAX_VV = 32'b000111???????????000?????1010111; - localparam [31:0] VAND_VV = 32'b001001???????????000?????1010111; - localparam [31:0] VOR_VV = 32'b001010???????????000?????1010111; - localparam [31:0] VXOR_VV = 32'b001011???????????000?????1010111; - localparam [31:0] VRGATHER_VV = 32'b001100???????????000?????1010111; - localparam [31:0] VRGATHEREI16_VV = 32'b001110???????????000?????1010111; - localparam [31:0] VMADC_VVM = 32'b010001???????????000?????1010111; - localparam [31:0] VMSBC_VVM = 32'b010011???????????000?????1010111; - localparam [31:0] VMERGE_VVM = 32'b0101110??????????000?????1010111; - localparam [31:0] VMV_V_V = 32'b010111100000?????000?????1010111; - localparam [31:0] VMSEQ_VV = 32'b011000???????????000?????1010111; - localparam [31:0] VMSNE_VV = 32'b011001???????????000?????1010111; - localparam [31:0] VMSLTU_VV = 32'b011010???????????000?????1010111; - localparam [31:0] VMSLT_VV = 32'b011011???????????000?????1010111; - localparam [31:0] VMSLEU_VV = 32'b011100???????????000?????1010111; - localparam [31:0] VMSLE_VV = 32'b011101???????????000?????1010111; - localparam [31:0] VSADDU_VV = 32'b100000???????????000?????1010111; - localparam [31:0] VSADD_VV = 32'b100001???????????000?????1010111; - localparam [31:0] VSSUBU_VV = 32'b100010???????????000?????1010111; - localparam [31:0] VSSUB_VV = 32'b100011???????????000?????1010111; - localparam [31:0] VSLL_VV = 32'b100101???????????000?????1010111; - localparam [31:0] VSMUL_VV = 32'b100111???????????000?????1010111; - localparam [31:0] VSRL_VV = 32'b101000???????????000?????1010111; - localparam [31:0] VSRA_VV = 32'b101001???????????000?????1010111; - localparam [31:0] VSSRL_VV = 32'b101010???????????000?????1010111; - localparam [31:0] VSSRA_VV = 32'b101011???????????000?????1010111; - localparam [31:0] VNSRL_WV = 32'b101100???????????000?????1010111; - localparam [31:0] VNSRA_WV = 32'b101101???????????000?????1010111; - localparam [31:0] VNCLIPU_WV = 32'b101110???????????000?????1010111; - localparam [31:0] VNCLIP_WV = 32'b101111???????????000?????1010111; - localparam [31:0] VWREDSUMU_VS = 32'b110000???????????000?????1010111; - localparam [31:0] VWREDSUM_VS = 32'b110001???????????000?????1010111; - localparam [31:0] VDOTU_VV = 32'b111000???????????000?????1010111; - localparam [31:0] VDOT_VV = 32'b111001???????????000?????1010111; - localparam [31:0] VQMACCU_VV = 32'b111100???????????000?????1010111; - localparam [31:0] VQMACC_VV = 32'b111101???????????000?????1010111; - localparam [31:0] VQMACCSU_VV = 32'b111111???????????000?????1010111; - localparam [31:0] VADD_VI = 32'b000000???????????011?????1010111; - localparam [31:0] VRSUB_VI = 32'b000011???????????011?????1010111; - localparam [31:0] VAND_VI = 32'b001001???????????011?????1010111; - localparam [31:0] VOR_VI = 32'b001010???????????011?????1010111; - localparam [31:0] VXOR_VI = 32'b001011???????????011?????1010111; - localparam [31:0] VRGATHER_VI = 32'b001100???????????011?????1010111; - localparam [31:0] VSLIDEUP_VI = 32'b001110???????????011?????1010111; - localparam [31:0] VSLIDEDOWN_VI = 32'b001111???????????011?????1010111; - localparam [31:0] VADC_VIM = 32'b0100000??????????011?????1010111; - localparam [31:0] VMADC_VIM = 32'b010001???????????011?????1010111; - localparam [31:0] VMERGE_VIM = 32'b0101110??????????011?????1010111; - localparam [31:0] VMV_V_I = 32'b010111100000?????011?????1010111; - localparam [31:0] VMSEQ_VI = 32'b011000???????????011?????1010111; - localparam [31:0] VMSNE_VI = 32'b011001???????????011?????1010111; - localparam [31:0] VMSLEU_VI = 32'b011100???????????011?????1010111; - localparam [31:0] VMSLE_VI = 32'b011101???????????011?????1010111; - localparam [31:0] VMSGTU_VI = 32'b011110???????????011?????1010111; - localparam [31:0] VMSGT_VI = 32'b011111???????????011?????1010111; - localparam [31:0] VSADDU_VI = 32'b100000???????????011?????1010111; - localparam [31:0] VSADD_VI = 32'b100001???????????011?????1010111; - localparam [31:0] VSLL_VI = 32'b100101???????????011?????1010111; - localparam [31:0] VMV1R_V = 32'b1001111?????00000011?????1010111; - localparam [31:0] VMV2R_V = 32'b1001111?????00001011?????1010111; - localparam [31:0] VMV4R_V = 32'b1001111?????00011011?????1010111; - localparam [31:0] VMV8R_V = 32'b1001111?????00111011?????1010111; - localparam [31:0] VSRL_VI = 32'b101000???????????011?????1010111; - localparam [31:0] VSRA_VI = 32'b101001???????????011?????1010111; - localparam [31:0] VSSRL_VI = 32'b101010???????????011?????1010111; - localparam [31:0] VSSRA_VI = 32'b101011???????????011?????1010111; - localparam [31:0] VNSRL_WI = 32'b101100???????????011?????1010111; - localparam [31:0] VNSRA_WI = 32'b101101???????????011?????1010111; - localparam [31:0] VNCLIPU_WI = 32'b101110???????????011?????1010111; - localparam [31:0] VNCLIP_WI = 32'b101111???????????011?????1010111; - localparam [31:0] VREDSUM_VS = 32'b000000???????????010?????1010111; - localparam [31:0] VREDAND_VS = 32'b000001???????????010?????1010111; - localparam [31:0] VREDOR_VS = 32'b000010???????????010?????1010111; - localparam [31:0] VREDXOR_VS = 32'b000011???????????010?????1010111; - localparam [31:0] VREDMINU_VS = 32'b000100???????????010?????1010111; - localparam [31:0] VREDMIN_VS = 32'b000101???????????010?????1010111; - localparam [31:0] VREDMAXU_VS = 32'b000110???????????010?????1010111; - localparam [31:0] VREDMAX_VS = 32'b000111???????????010?????1010111; - localparam [31:0] VAADDU_VV = 32'b001000???????????010?????1010111; - localparam [31:0] VAADD_VV = 32'b001001???????????010?????1010111; - localparam [31:0] VASUBU_VV = 32'b001010???????????010?????1010111; - localparam [31:0] VASUB_VV = 32'b001011???????????010?????1010111; - localparam [31:0] VMV_X_S = 32'b0100001?????00000010?????1010111; - localparam [31:0] VZEXT_VF8 = 32'b010010??????00010010?????1010111; - localparam [31:0] VSEXT_VF8 = 32'b010010??????00011010?????1010111; - localparam [31:0] VZEXT_VF4 = 32'b010010??????00100010?????1010111; - localparam [31:0] VSEXT_VF4 = 32'b010010??????00101010?????1010111; - localparam [31:0] VZEXT_VF2 = 32'b010010??????00110010?????1010111; - localparam [31:0] VSEXT_VF2 = 32'b010010??????00111010?????1010111; - localparam [31:0] VCOMPRESS_VM = 32'b0101111??????????010?????1010111; - localparam [31:0] VMANDNOT_MM = 32'b011000???????????010?????1010111; - localparam [31:0] VMAND_MM = 32'b011001???????????010?????1010111; - localparam [31:0] VMOR_MM = 32'b011010???????????010?????1010111; - localparam [31:0] VMXOR_MM = 32'b011011???????????010?????1010111; - localparam [31:0] VMORNOT_MM = 32'b011100???????????010?????1010111; - localparam [31:0] VMNAND_MM = 32'b011101???????????010?????1010111; - localparam [31:0] VMNOR_MM = 32'b011110???????????010?????1010111; - localparam [31:0] VMXNOR_MM = 32'b011111???????????010?????1010111; - localparam [31:0] VMSBF_M = 32'b010100??????00001010?????1010111; - localparam [31:0] VMSOF_M = 32'b010100??????00010010?????1010111; - localparam [31:0] VMSIF_M = 32'b010100??????00011010?????1010111; - localparam [31:0] VIOTA_M = 32'b010100??????10000010?????1010111; - localparam [31:0] VID_V = 32'b010100?0000010001010?????1010111; - localparam [31:0] VPOPC_M = 32'b010000??????10000010?????1010111; - localparam [31:0] VFIRST_M = 32'b010000??????10001010?????1010111; - localparam [31:0] VDIVU_VV = 32'b100000???????????010?????1010111; - localparam [31:0] VDIV_VV = 32'b100001???????????010?????1010111; - localparam [31:0] VREMU_VV = 32'b100010???????????010?????1010111; - localparam [31:0] VREM_VV = 32'b100011???????????010?????1010111; - localparam [31:0] VMULHU_VV = 32'b100100???????????010?????1010111; - localparam [31:0] VMUL_VV = 32'b100101???????????010?????1010111; - localparam [31:0] VMULHSU_VV = 32'b100110???????????010?????1010111; - localparam [31:0] VMULH_VV = 32'b100111???????????010?????1010111; - localparam [31:0] VMADD_VV = 32'b101001???????????010?????1010111; - localparam [31:0] VNMSUB_VV = 32'b101011???????????010?????1010111; - localparam [31:0] VMACC_VV = 32'b101101???????????010?????1010111; - localparam [31:0] VNMSAC_VV = 32'b101111???????????010?????1010111; - localparam [31:0] VWADDU_VV = 32'b110000???????????010?????1010111; - localparam [31:0] VWADD_VV = 32'b110001???????????010?????1010111; - localparam [31:0] VWSUBU_VV = 32'b110010???????????010?????1010111; - localparam [31:0] VWSUB_VV = 32'b110011???????????010?????1010111; - localparam [31:0] VWADDU_WV = 32'b110100???????????010?????1010111; - localparam [31:0] VWADD_WV = 32'b110101???????????010?????1010111; - localparam [31:0] VWSUBU_WV = 32'b110110???????????010?????1010111; - localparam [31:0] VWSUB_WV = 32'b110111???????????010?????1010111; - localparam [31:0] VWMULU_VV = 32'b111000???????????010?????1010111; - localparam [31:0] VWMULSU_VV = 32'b111010???????????010?????1010111; - localparam [31:0] VWMUL_VV = 32'b111011???????????010?????1010111; - localparam [31:0] VWMACCU_VV = 32'b111100???????????010?????1010111; - localparam [31:0] VWMACC_VV = 32'b111101???????????010?????1010111; - localparam [31:0] VWMACCSU_VV = 32'b111111???????????010?????1010111; - localparam [31:0] VAADD_VX = 32'b001001???????????110?????1010111; - localparam [31:0] VASUB_VX = 32'b001011???????????110?????1010111; - localparam [31:0] VMV_S_X = 32'b010000100000?????110?????1010111; - localparam [31:0] VSLIDE1DOWN_VX = 32'b001111???????????110?????1010111; - localparam [31:0] VDIV_VX = 32'b100001???????????110?????1010111; - localparam [31:0] VREMU_VX = 32'b100010???????????110?????1010111; - localparam [31:0] VREM_VX = 32'b100011???????????110?????1010111; - localparam [31:0] VMUL_VX = 32'b100101???????????110?????1010111; - localparam [31:0] VMULH_VX = 32'b100111???????????110?????1010111; - localparam [31:0] VMADD_VX = 32'b101001???????????110?????1010111; - localparam [31:0] VNMSUB_VX = 32'b101011???????????110?????1010111; - localparam [31:0] VMACC_VX = 32'b101101???????????110?????1010111; - localparam [31:0] VNMSAC_VX = 32'b101111???????????110?????1010111; - localparam [31:0] VWADDU_VX = 32'b110000???????????110?????1010111; - localparam [31:0] VWADD_VX = 32'b110001???????????110?????1010111; - localparam [31:0] VWSUBU_VX = 32'b110010???????????110?????1010111; - localparam [31:0] VWSUB_VX = 32'b110011???????????110?????1010111; - localparam [31:0] VWADDU_WX = 32'b110100???????????110?????1010111; - localparam [31:0] VWADD_WX = 32'b110101???????????110?????1010111; - localparam [31:0] VWSUBU_WX = 32'b110110???????????110?????1010111; - localparam [31:0] VWSUB_WX = 32'b110111???????????110?????1010111; - localparam [31:0] VWMULU_VX = 32'b111000???????????110?????1010111; - localparam [31:0] VWMULSU_VX = 32'b111010???????????110?????1010111; - localparam [31:0] VWMUL_VX = 32'b111011???????????110?????1010111; - localparam [31:0] VWMACCU_VX = 32'b111100???????????110?????1010111; - localparam [31:0] VWMACC_VX = 32'b111101???????????110?????1010111; - localparam [31:0] VWMACCUS_VX = 32'b111110???????????110?????1010111; - localparam [31:0] VWMACCSU_VX = 32'b111111???????????110?????1010111; - localparam [31:0] VAMOSWAPEI8_V = 32'b00001????????????000?????0101111; - localparam [31:0] VAMOADDEI8_V = 32'b00000????????????000?????0101111; - localparam [31:0] VAMOXOREI8_V = 32'b00100????????????000?????0101111; - localparam [31:0] VAMOANDEI8_V = 32'b01100????????????000?????0101111; - localparam [31:0] VAMOOREI8_V = 32'b01000????????????000?????0101111; - localparam [31:0] VAMOMINEI8_V = 32'b10000????????????000?????0101111; - localparam [31:0] VAMOMAXEI8_V = 32'b10100????????????000?????0101111; - localparam [31:0] VAMOMINUEI8_V = 32'b11000????????????000?????0101111; - localparam [31:0] VAMOMAXUEI8_V = 32'b11100????????????000?????0101111; - localparam [31:0] VAMOSWAPEI16_V = 32'b00001????????????101?????0101111; - localparam [31:0] VAMOADDEI16_V = 32'b00000????????????101?????0101111; - localparam [31:0] VAMOXOREI16_V = 32'b00100????????????101?????0101111; - localparam [31:0] VAMOANDEI16_V = 32'b01100????????????101?????0101111; - localparam [31:0] VAMOOREI16_V = 32'b01000????????????101?????0101111; - localparam [31:0] VAMOMINEI16_V = 32'b10000????????????101?????0101111; - localparam [31:0] VAMOMAXEI16_V = 32'b10100????????????101?????0101111; - localparam [31:0] VAMOMINUEI16_V = 32'b11000????????????101?????0101111; - localparam [31:0] VAMOMAXUEI16_V = 32'b11100????????????101?????0101111; - localparam [31:0] VAMOSWAPEI32_V = 32'b00001????????????110?????0101111; - localparam [31:0] VAMOADDEI32_V = 32'b00000????????????110?????0101111; - localparam [31:0] VAMOXOREI32_V = 32'b00100????????????110?????0101111; - localparam [31:0] VAMOANDEI32_V = 32'b01100????????????110?????0101111; - localparam [31:0] VAMOOREI32_V = 32'b01000????????????110?????0101111; - localparam [31:0] VAMOMINEI32_V = 32'b10000????????????110?????0101111; - localparam [31:0] VAMOMAXEI32_V = 32'b10100????????????110?????0101111; - localparam [31:0] VAMOMINUEI32_V = 32'b11000????????????110?????0101111; - localparam [31:0] VAMOMAXUEI32_V = 32'b11100????????????110?????0101111; - localparam [31:0] VAMOSWAPEI64_V = 32'b00001????????????111?????0101111; - localparam [31:0] VAMOADDEI64_V = 32'b00000????????????111?????0101111; - localparam [31:0] VAMOXOREI64_V = 32'b00100????????????111?????0101111; - localparam [31:0] VAMOANDEI64_V = 32'b01100????????????111?????0101111; - localparam [31:0] VAMOOREI64_V = 32'b01000????????????111?????0101111; - localparam [31:0] VAMOMINEI64_V = 32'b10000????????????111?????0101111; - localparam [31:0] VAMOMAXEI64_V = 32'b10100????????????111?????0101111; - localparam [31:0] VAMOMINUEI64_V = 32'b11000????????????111?????0101111; - localparam [31:0] VAMOMAXUEI64_V = 32'b11100????????????111?????0101111; - localparam [31:0] VMVNFR_V = 32'b1001111??????????011?????1010111; - localparam [31:0] VL1R_V = 32'b000000101000?????000?????0000111; - localparam [31:0] VL2R_V = 32'b000001101000?????101?????0000111; - localparam [31:0] VL4R_V = 32'b000011101000?????110?????0000111; - localparam [31:0] VL8R_V = 32'b000111101000?????111?????0000111; - localparam [31:0] ECALL = 32'b00000000000000000000000001110011; - localparam [31:0] EBREAK = 32'b00000000000100000000000001110011; - localparam [31:0] URET = 32'b00000000001000000000000001110011; - localparam [31:0] SRET = 32'b00010000001000000000000001110011; - localparam [31:0] MRET = 32'b00110000001000000000000001110011; - localparam [31:0] DRET = 32'b01111011001000000000000001110011; - localparam [31:0] SFENCE_VMA = 32'b0001001??????????000000001110011; - localparam [31:0] WFI = 32'b00010000010100000000000001110011; - localparam [31:0] CSRRW = 32'b?????????????????001?????1110011; - localparam [31:0] CSRRS = 32'b?????????????????010?????1110011; - localparam [31:0] CSRRC = 32'b?????????????????011?????1110011; - localparam [31:0] CSRRWI = 32'b?????????????????101?????1110011; - localparam [31:0] CSRRSI = 32'b?????????????????110?????1110011; - localparam [31:0] CSRRCI = 32'b?????????????????111?????1110011; - localparam [31:0] LP_STARTI = 32'b????????????000000000000?1111011; - localparam [31:0] LP_ENDI = 32'b????????????000000010000?1111011; - localparam [31:0] LP_COUNT = 32'b000000000000?????0100000?1111011; - localparam [31:0] LP_COUNTI = 32'b????????????000000110000?1111011; - localparam [31:0] LP_SETUP = 32'b?????????????????1000000?1111011; - localparam [31:0] LP_SETUPI = 32'b?????????????????1010000?1111011; - localparam [31:0] P_LB_IRPOST = 32'b?????????????????000?????0001011; - localparam [31:0] P_LBU_IRPOST = 32'b?????????????????100?????0001011; - localparam [31:0] P_LH_IRPOST = 32'b?????????????????001?????0001011; - localparam [31:0] P_LHU_IRPOST = 32'b?????????????????101?????0001011; - localparam [31:0] P_LW_IRPOST = 32'b?????????????????010?????0001011; - localparam [31:0] P_LB_RRPOST = 32'b0000000??????????111?????0001011; - localparam [31:0] P_LBU_RRPOST = 32'b0100000??????????111?????0001011; - localparam [31:0] P_LH_RRPOST = 32'b0001000??????????111?????0001011; - localparam [31:0] P_LHU_RRPOST = 32'b0101000??????????111?????0001011; - localparam [31:0] P_LW_RRPOST = 32'b0010000??????????111?????0001011; - localparam [31:0] P_LB_RR = 32'b0000000??????????111?????0000011; - localparam [31:0] P_LBU_RR = 32'b0100000??????????111?????0000011; - localparam [31:0] P_LH_RR = 32'b0001000??????????111?????0000011; - localparam [31:0] P_LHU_RR = 32'b0101000??????????111?????0000011; - localparam [31:0] P_LW_RR = 32'b0010000??????????111?????0000011; - localparam [31:0] P_SB_IRPOST = 32'b?????????????????000?????0101011; - localparam [31:0] P_SH_IRPOST = 32'b?????????????????001?????0101011; - localparam [31:0] P_SW_IRPOST = 32'b?????????????????010?????0101011; - localparam [31:0] P_SB_RRPOST = 32'b0000000??????????100?????0101011; - localparam [31:0] P_SH_RRPOST = 32'b0000000??????????101?????0101011; - localparam [31:0] P_SW_RRPOST = 32'b0000000??????????110?????0101011; - localparam [31:0] P_SB_RR = 32'b0000000??????????100?????0100011; - localparam [31:0] P_SH_RR = 32'b0000000??????????101?????0100011; - localparam [31:0] P_SW_RR = 32'b0000000??????????110?????0100011; - localparam [31:0] P_ABS = 32'b000001000000?????000?????0110011; - localparam [31:0] P_SLET = 32'b0000010??????????010?????0110011; - localparam [31:0] P_SLETU = 32'b0000010??????????011?????0110011; - localparam [31:0] P_MIN = 32'b0000010??????????100?????0110011; - localparam [31:0] P_MINU = 32'b0000010??????????101?????0110011; - localparam [31:0] P_MAX = 32'b0000010??????????110?????0110011; - localparam [31:0] P_MAXU = 32'b0000010??????????111?????0110011; - localparam [31:0] P_EXTHS = 32'b000100000000?????100?????0110011; - localparam [31:0] P_EXTHZ = 32'b000100000000?????101?????0110011; - localparam [31:0] P_EXTBS = 32'b000100000000?????110?????0110011; - localparam [31:0] P_EXTBZ = 32'b000100000000?????111?????0110011; - localparam [31:0] P_CLIP = 32'b0001010??????????001?????0110011; - localparam [31:0] P_CLIPU = 32'b0001010??????????010?????0110011; - localparam [31:0] P_CLIPR = 32'b0001010??????????101?????0110011; - localparam [31:0] P_CLIPUR = 32'b0001010??????????110?????0110011; - localparam [31:0] P_BEQIMM = 32'b?????????????????010?????1100011; - localparam [31:0] P_BNEIMM = 32'b?????????????????011?????1100011; - localparam [31:0] P_MAC = 32'b0100001??????????000?????0110011; - localparam [31:0] P_MSU = 32'b0100001??????????001?????0110011; - localparam [31:0] PV_ADD_H = 32'b0000000??????????000?????1010111; - localparam [31:0] PV_ADD_SC_H = 32'b0000000??????????100?????1010111; - localparam [31:0] PV_ADD_SCI_H = 32'b000000???????????110?????1010111; - localparam [31:0] PV_ADD_B = 32'b0000000??????????001?????1010111; - localparam [31:0] PV_ADD_SC_B = 32'b0000000??????????101?????1010111; - localparam [31:0] PV_ADD_SCI_B = 32'b000000???????????111?????1010111; - localparam [31:0] PV_SUB_H = 32'b0000100??????????000?????1010111; - localparam [31:0] PV_SUB_SC_H = 32'b0000100??????????100?????1010111; - localparam [31:0] PV_SUB_SCI_H = 32'b000010???????????110?????1010111; - localparam [31:0] PV_SUB_B = 32'b0000100??????????001?????1010111; - localparam [31:0] PV_SUB_SC_B = 32'b0000100??????????101?????1010111; - localparam [31:0] PV_SUB_SCI_B = 32'b000010???????????111?????1010111; - localparam [31:0] PV_AVG_H = 32'b0001000??????????000?????1010111; - localparam [31:0] PV_AVG_SC_H = 32'b0001000??????????100?????1010111; - localparam [31:0] PV_AVG_SCI_H = 32'b000100???????????110?????1010111; - localparam [31:0] PV_AVG_B = 32'b0001000??????????001?????1010111; - localparam [31:0] PV_AVG_SC_B = 32'b0001000??????????101?????1010111; - localparam [31:0] PV_AVG_SCI_B = 32'b000100???????????111?????1010111; - localparam [31:0] PV_AVGU_H = 32'b0001100??????????000?????1010111; - localparam [31:0] PV_AVGU_SC_H = 32'b0001100??????????100?????1010111; - localparam [31:0] PV_AVGU_SCI_H = 32'b000110???????????110?????1010111; - localparam [31:0] PV_AVGU_B = 32'b0001100??????????001?????1010111; - localparam [31:0] PV_AVGU_SC_B = 32'b0001100??????????101?????1010111; - localparam [31:0] PV_AVGU_SCI_B = 32'b000110???????????111?????1010111; - localparam [31:0] PV_MIN_H = 32'b0010000??????????000?????1010111; - localparam [31:0] PV_MIN_SC_H = 32'b0010000??????????100?????1010111; - localparam [31:0] PV_MIN_SCI_H = 32'b001000???????????110?????1010111; - localparam [31:0] PV_MIN_B = 32'b0010000??????????001?????1010111; - localparam [31:0] PV_MIN_SC_B = 32'b0010000??????????101?????1010111; - localparam [31:0] PV_MIN_SCI_B = 32'b001000???????????111?????1010111; - localparam [31:0] PV_MINU_H = 32'b0010100??????????000?????1010111; - localparam [31:0] PV_MINU_SC_H = 32'b0010100??????????100?????1010111; - localparam [31:0] PV_MINU_SCI_H = 32'b001010???????????110?????1010111; - localparam [31:0] PV_MINU_B = 32'b0010100??????????001?????1010111; - localparam [31:0] PV_MINU_SC_B = 32'b0010100??????????101?????1010111; - localparam [31:0] PV_MINU_SCI_B = 32'b001010???????????111?????1010111; - localparam [31:0] PV_MAX_H = 32'b0011000??????????000?????1010111; - localparam [31:0] PV_MAX_SC_H = 32'b0011000??????????100?????1010111; - localparam [31:0] PV_MAX_SCI_H = 32'b001100???????????110?????1010111; - localparam [31:0] PV_MAX_B = 32'b0011000??????????001?????1010111; - localparam [31:0] PV_MAX_SC_B = 32'b0011000??????????101?????1010111; - localparam [31:0] PV_MAX_SCI_B = 32'b001100???????????111?????1010111; - localparam [31:0] PV_MAXU_H = 32'b0011100??????????000?????1010111; - localparam [31:0] PV_MAXU_SC_H = 32'b0011100??????????100?????1010111; - localparam [31:0] PV_MAXU_SCI_H = 32'b001110???????????110?????1010111; - localparam [31:0] PV_MAXU_B = 32'b0011100??????????001?????1010111; - localparam [31:0] PV_MAXU_SC_B = 32'b0011100??????????101?????1010111; - localparam [31:0] PV_MAXU_SCI_B = 32'b001110???????????111?????1010111; - localparam [31:0] PV_SRL_H = 32'b0100000??????????000?????1010111; - localparam [31:0] PV_SRL_SC_H = 32'b0100000??????????100?????1010111; - localparam [31:0] PV_SRL_SCI_H = 32'b010000???????????110?????1010111; - localparam [31:0] PV_SRL_B = 32'b0100000??????????001?????1010111; - localparam [31:0] PV_SRL_SC_B = 32'b0100000??????????101?????1010111; - localparam [31:0] PV_SRL_SCI_B = 32'b010000???????????111?????1010111; - localparam [31:0] PV_SRA_H = 32'b0100100??????????000?????1010111; - localparam [31:0] PV_SRA_SC_H = 32'b0100100??????????100?????1010111; - localparam [31:0] PV_SRA_SCI_H = 32'b010010???????????110?????1010111; - localparam [31:0] PV_SRA_B = 32'b0100100??????????001?????1010111; - localparam [31:0] PV_SRA_SC_B = 32'b0100100??????????101?????1010111; - localparam [31:0] PV_SRA_SCI_B = 32'b010010???????????111?????1010111; - localparam [31:0] PV_SLL_H = 32'b0101000??????????000?????1010111; - localparam [31:0] PV_SLL_SC_H = 32'b0101000??????????100?????1010111; - localparam [31:0] PV_SLL_SCI_H = 32'b010100???????????110?????1010111; - localparam [31:0] PV_SLL_B = 32'b0101000??????????001?????1010111; - localparam [31:0] PV_SLL_SC_B = 32'b0101000??????????101?????1010111; - localparam [31:0] PV_SLL_SCI_B = 32'b010100???????????111?????1010111; - localparam [31:0] PV_OR_H = 32'b0101100??????????000?????1010111; - localparam [31:0] PV_OR_SC_H = 32'b0101100??????????100?????1010111; - localparam [31:0] PV_OR_SCI_H = 32'b010110???????????110?????1010111; - localparam [31:0] PV_OR_B = 32'b0101100??????????001?????1010111; - localparam [31:0] PV_OR_SC_B = 32'b0101100??????????101?????1010111; - localparam [31:0] PV_OR_SCI_B = 32'b010110???????????111?????1010111; - localparam [31:0] PV_XOR_H = 32'b0110000??????????000?????1010111; - localparam [31:0] PV_XOR_SC_H = 32'b0110000??????????100?????1010111; - localparam [31:0] PV_XOR_SCI_H = 32'b011000???????????110?????1010111; - localparam [31:0] PV_XOR_B = 32'b0110000??????????001?????1010111; - localparam [31:0] PV_XOR_SC_B = 32'b0110000??????????101?????1010111; - localparam [31:0] PV_XOR_SCI_B = 32'b011000???????????111?????1010111; - localparam [31:0] PV_AND_H = 32'b0110100??????????000?????1010111; - localparam [31:0] PV_AND_SC_H = 32'b0110100??????????100?????1010111; - localparam [31:0] PV_AND_SCI_H = 32'b011010???????????110?????1010111; - localparam [31:0] PV_AND_B = 32'b0110100??????????001?????1010111; - localparam [31:0] PV_AND_SC_B = 32'b0110100??????????101?????1010111; - localparam [31:0] PV_AND_SCI_B = 32'b011010???????????111?????1010111; - localparam [31:0] PV_ABS_H = 32'b011100000000?????000?????1010111; - localparam [31:0] PV_ABS_B = 32'b011100000000?????001?????1010111; - localparam [31:0] PV_EXTRACT_H = 32'b011110???????????110?????1010111; - localparam [31:0] PV_EXTRACT_B = 32'b011110???????????111?????1010111; - localparam [31:0] PV_EXTRACTU_H = 32'b100100???????????110?????1010111; - localparam [31:0] PV_EXTRACTU_B = 32'b100100???????????111?????1010111; - localparam [31:0] PV_INSERT_H = 32'b101100???????????110?????1010111; - localparam [31:0] PV_INSERT_B = 32'b101100???????????111?????1010111; - localparam [31:0] PV_DOTUP_H = 32'b1000000??????????000?????1010111; - localparam [31:0] PV_DOTUP_SC_H = 32'b1000000??????????100?????1010111; - localparam [31:0] PV_DOTUP_SCI_H = 32'b100000???????????110?????1010111; - localparam [31:0] PV_DOTUP_B = 32'b1000000??????????001?????1010111; - localparam [31:0] PV_DOTUP_SC_B = 32'b1000000??????????101?????1010111; - localparam [31:0] PV_DOTUP_SCI_B = 32'b100000???????????111?????1010111; - localparam [31:0] PV_DOTUSP_H = 32'b1000100??????????000?????1010111; - localparam [31:0] PV_DOTUSP_SC_H = 32'b1000100??????????100?????1010111; - localparam [31:0] PV_DOTUSP_SCI_H = 32'b100010???????????110?????1010111; - localparam [31:0] PV_DOTUSP_B = 32'b1000100??????????001?????1010111; - localparam [31:0] PV_DOTUSP_SC_B = 32'b1000100??????????101?????1010111; - localparam [31:0] PV_DOTUSP_SCI_B = 32'b100010???????????111?????1010111; - localparam [31:0] PV_DOTSP_H = 32'b1001100??????????000?????1010111; - localparam [31:0] PV_DOTSP_SC_H = 32'b1001100??????????100?????1010111; - localparam [31:0] PV_DOTSP_SCI_H = 32'b100110???????????110?????1010111; - localparam [31:0] PV_DOTSP_B = 32'b1001100??????????001?????1010111; - localparam [31:0] PV_DOTSP_SC_B = 32'b1001100??????????101?????1010111; - localparam [31:0] PV_DOTSP_SCI_B = 32'b100110???????????111?????1010111; - localparam [31:0] PV_SDOTUP_H = 32'b1010000??????????000?????1010111; - localparam [31:0] PV_SDOTUP_SC_H = 32'b1010000??????????100?????1010111; - localparam [31:0] PV_SDOTUP_SCI_H = 32'b101000???????????110?????1010111; - localparam [31:0] PV_SDOTUP_B = 32'b1010000??????????001?????1010111; - localparam [31:0] PV_SDOTUP_SC_B = 32'b1010000??????????101?????1010111; - localparam [31:0] PV_SDOTUP_SCI_B = 32'b101000???????????111?????1010111; - localparam [31:0] PV_SDOTUSP_H = 32'b1010100??????????000?????1010111; - localparam [31:0] PV_SDOTUSP_SC_H = 32'b1010100??????????100?????1010111; - localparam [31:0] PV_SDOTUSP_SCI_H = 32'b101010???????????110?????1010111; - localparam [31:0] PV_SDOTUSP_B = 32'b1010100??????????001?????1010111; - localparam [31:0] PV_SDOTUSP_SC_B = 32'b1010100??????????101?????1010111; - localparam [31:0] PV_SDOTUSP_SCI_B = 32'b101010???????????111?????1010111; - localparam [31:0] PV_SDOTSP_H = 32'b1011100??????????000?????1010111; - localparam [31:0] PV_SDOTSP_SC_H = 32'b1011100??????????100?????1010111; - localparam [31:0] PV_SDOTSP_SCI_H = 32'b101110???????????110?????1010111; - localparam [31:0] PV_SDOTSP_B = 32'b1011100??????????001?????1010111; - localparam [31:0] PV_SDOTSP_SC_B = 32'b1011100??????????101?????1010111; - localparam [31:0] PV_SDOTSP_SCI_B = 32'b101110???????????111?????1010111; - localparam [31:0] PV_SHUFFLE2_H = 32'b1100100??????????000?????1010111; - localparam [31:0] PV_SHUFFLE2_B = 32'b1100100??????????001?????1010111; - localparam [31:0] FLAH = 32'b?????????????????001?????0000111; - localparam [31:0] FSAH = 32'b?????????????????001?????0100111; - localparam [31:0] FMADD_AH = 32'b?????10??????????101?????1000011; - localparam [31:0] FMSUB_AH = 32'b?????10??????????101?????1000111; - localparam [31:0] FNMSUB_AH = 32'b?????10??????????101?????1001011; - localparam [31:0] FNMADD_AH = 32'b?????10??????????101?????1001111; - localparam [31:0] FADD_AH = 32'b0000010??????????101?????1010011; - localparam [31:0] FSUB_AH = 32'b0000110??????????101?????1010011; - localparam [31:0] FMUL_AH = 32'b0001010??????????101?????1010011; - localparam [31:0] FDIV_AH = 32'b0001110??????????101?????1010011; - localparam [31:0] FSQRT_AH = 32'b010111000000?????101?????1010011; - localparam [31:0] FSGNJ_AH = 32'b0010010??????????100?????1010011; - localparam [31:0] FSGNJN_AH = 32'b0010010??????????101?????1010011; - localparam [31:0] FSGNJX_AH = 32'b0010010??????????110?????1010011; - localparam [31:0] FMIN_AH = 32'b0010110??????????100?????1010011; - localparam [31:0] FMAX_AH = 32'b0010110??????????101?????1010011; - localparam [31:0] FEQ_AH = 32'b1010010??????????110?????1010011; - localparam [31:0] FLT_AH = 32'b1010010??????????101?????1010011; - localparam [31:0] FLE_AH = 32'b1010010??????????100?????1010011; - localparam [31:0] FCVT_W_AH = 32'b110001000000?????101?????1010011; - localparam [31:0] FCVT_WU_AH = 32'b110001000001?????101?????1010011; - localparam [31:0] FCVT_AH_W = 32'b110101000000?????101?????1010011; - localparam [31:0] FCVT_AH_WU = 32'b110101000001?????101?????1010011; - localparam [31:0] FMV_X_AH = 32'b111001000000?????100?????1010011; - localparam [31:0] FCLASS_AH = 32'b111001000000?????101?????1010011; - localparam [31:0] FMV_AH_X = 32'b111101000000?????100?????1010011; - localparam [31:0] FCVT_L_AH = 32'b110001000010?????101?????1010011; - localparam [31:0] FCVT_LU_AH = 32'b110001000011?????101?????1010011; - localparam [31:0] FCVT_AH_L = 32'b110101000010?????101?????1010011; - localparam [31:0] FCVT_AH_LU = 32'b110101000011?????101?????1010011; - localparam [31:0] FCVT_S_AH = 32'b010000000110?????000?????1010011; - localparam [31:0] FCVT_AH_S = 32'b010001000000?????101?????1010011; - localparam [31:0] FCVT_D_AH = 32'b010000100110?????000?????1010011; - localparam [31:0] FCVT_AH_D = 32'b010001000001?????101?????1010011; - localparam [31:0] FCVT_H_AH = 32'b010001000110?????????????1010011; - localparam [31:0] FCVT_AH_H = 32'b010001000010?????101?????1010011; - localparam [31:0] FLB = 32'b?????????????????000?????0000111; - localparam [31:0] FSB = 32'b?????????????????000?????0100111; - localparam [31:0] FMADD_B = 32'b?????11??????????????????1000011; - localparam [31:0] FMSUB_B = 32'b?????11??????????????????1000111; - localparam [31:0] FNMSUB_B = 32'b?????11??????????????????1001011; - localparam [31:0] FNMADD_B = 32'b?????11??????????????????1001111; - localparam [31:0] FADD_B = 32'b0000011??????????????????1010011; - localparam [31:0] FSUB_B = 32'b0000111??????????????????1010011; - localparam [31:0] FMUL_B = 32'b0001011??????????????????1010011; - localparam [31:0] FDIV_B = 32'b0001111??????????????????1010011; - localparam [31:0] FSQRT_B = 32'b010111100000?????????????1010011; - localparam [31:0] FSGNJ_B = 32'b0010011??????????000?????1010011; - localparam [31:0] FSGNJN_B = 32'b0010011??????????001?????1010011; - localparam [31:0] FSGNJX_B = 32'b0010011??????????010?????1010011; - localparam [31:0] FMIN_B = 32'b0010111??????????000?????1010011; - localparam [31:0] FMAX_B = 32'b0010111??????????001?????1010011; - localparam [31:0] FEQ_B = 32'b1010011??????????010?????1010011; - localparam [31:0] FLT_B = 32'b1010011??????????001?????1010011; - localparam [31:0] FLE_B = 32'b1010011??????????000?????1010011; - localparam [31:0] FCVT_W_B = 32'b110001100000?????????????1010011; - localparam [31:0] FCVT_WU_B = 32'b110001100001?????????????1010011; - localparam [31:0] FCVT_B_W = 32'b110101100000?????????????1010011; - localparam [31:0] FCVT_B_WU = 32'b110101100001?????????????1010011; - localparam [31:0] FMV_X_B = 32'b111001100000?????000?????1010011; - localparam [31:0] FCLASS_B = 32'b111001100000?????001?????1010011; - localparam [31:0] FMV_B_X = 32'b111101100000?????000?????1010011; - localparam [31:0] FCVT_L_B = 32'b110001100010?????????????1010011; - localparam [31:0] FCVT_LU_B = 32'b110001100011?????????????1010011; - localparam [31:0] FCVT_B_L = 32'b110101100010?????????????1010011; - localparam [31:0] FCVT_B_LU = 32'b110101100011?????????????1010011; - localparam [31:0] FCVT_S_B = 32'b010000000011?????000?????1010011; - localparam [31:0] FCVT_B_S = 32'b010001100000?????????????1010011; - localparam [31:0] FCVT_D_B = 32'b010000100011?????000?????1010011; - localparam [31:0] FCVT_B_D = 32'b010001100001?????????????1010011; - localparam [31:0] FCVT_H_B = 32'b010001000011?????000?????1010011; - localparam [31:0] FCVT_B_H = 32'b010001100010?????????????1010011; - localparam [31:0] FCVT_AH_B = 32'b010001000011?????101?????1010011; - localparam [31:0] FCVT_B_AH = 32'b010001100110?????????????1010011; - localparam [31:0] VFADD_S = 32'b1000001??????????000?????0110011; - localparam [31:0] VFADD_R_S = 32'b1000001??????????100?????0110011; - localparam [31:0] VFSUB_S = 32'b1000010??????????000?????0110011; - localparam [31:0] VFSUB_R_S = 32'b1000010??????????100?????0110011; - localparam [31:0] VFMUL_S = 32'b1000011??????????000?????0110011; - localparam [31:0] VFMUL_R_S = 32'b1000011??????????100?????0110011; - localparam [31:0] VFDIV_S = 32'b1000100??????????000?????0110011; - localparam [31:0] VFDIV_R_S = 32'b1000100??????????100?????0110011; - localparam [31:0] VFMIN_S = 32'b1000101??????????000?????0110011; - localparam [31:0] VFMIN_R_S = 32'b1000101??????????100?????0110011; - localparam [31:0] VFMAX_S = 32'b1000110??????????000?????0110011; - localparam [31:0] VFMAX_R_S = 32'b1000110??????????100?????0110011; - localparam [31:0] VFSQRT_S = 32'b100011100000?????000?????0110011; - localparam [31:0] VFMAC_S = 32'b1001000??????????000?????0110011; - localparam [31:0] VFMAC_R_S = 32'b1001000??????????100?????0110011; - localparam [31:0] VFMRE_S = 32'b1001001??????????000?????0110011; - localparam [31:0] VFMRE_R_S = 32'b1001001??????????100?????0110011; - localparam [31:0] VFCLASS_S = 32'b100110000001?????000?????0110011; - localparam [31:0] VFSGNJ_S = 32'b1001101??????????000?????0110011; - localparam [31:0] VFSGNJ_R_S = 32'b1001101??????????100?????0110011; - localparam [31:0] VFSGNJN_S = 32'b1001110??????????000?????0110011; - localparam [31:0] VFSGNJN_R_S = 32'b1001110??????????100?????0110011; - localparam [31:0] VFSGNJX_S = 32'b1001111??????????000?????0110011; - localparam [31:0] VFSGNJX_R_S = 32'b1001111??????????100?????0110011; - localparam [31:0] VFEQ_S = 32'b1010000??????????000?????0110011; - localparam [31:0] VFEQ_R_S = 32'b1010000??????????100?????0110011; - localparam [31:0] VFNE_S = 32'b1010001??????????000?????0110011; - localparam [31:0] VFNE_R_S = 32'b1010001??????????100?????0110011; - localparam [31:0] VFLT_S = 32'b1010010??????????000?????0110011; - localparam [31:0] VFLT_R_S = 32'b1010010??????????100?????0110011; - localparam [31:0] VFGE_S = 32'b1010011??????????000?????0110011; - localparam [31:0] VFGE_R_S = 32'b1010011??????????100?????0110011; - localparam [31:0] VFLE_S = 32'b1010100??????????000?????0110011; - localparam [31:0] VFLE_R_S = 32'b1010100??????????100?????0110011; - localparam [31:0] VFGT_S = 32'b1010101??????????000?????0110011; - localparam [31:0] VFGT_R_S = 32'b1010101??????????100?????0110011; - localparam [31:0] VFMV_X_S = 32'b100110000000?????000?????0110011; - localparam [31:0] VFMV_S_X = 32'b100110000000?????100?????0110011; - localparam [31:0] VFCVT_X_S = 32'b100110000010?????000?????0110011; - localparam [31:0] VFCVT_XU_S = 32'b100110000010?????100?????0110011; - localparam [31:0] VFCVT_S_X = 32'b100110000011?????000?????0110011; - localparam [31:0] VFCVT_S_XU = 32'b100110000011?????100?????0110011; - localparam [31:0] VFCPKA_S_S = 32'b1011000??????????000?????0110011; - localparam [31:0] VFCPKB_S_S = 32'b1011000??????????100?????0110011; - localparam [31:0] VFCPKC_S_S = 32'b1011001??????????000?????0110011; - localparam [31:0] VFCPKD_S_S = 32'b1011001??????????100?????0110011; - localparam [31:0] VFCPKA_S_D = 32'b1011010??????????000?????0110011; - localparam [31:0] VFCPKB_S_D = 32'b1011010??????????100?????0110011; - localparam [31:0] VFCPKC_S_D = 32'b1011011??????????000?????0110011; - localparam [31:0] VFCPKD_S_D = 32'b1011011??????????100?????0110011; - localparam [31:0] VFADD_H = 32'b1000001??????????010?????0110011; - localparam [31:0] VFADD_R_H = 32'b1000001??????????110?????0110011; - localparam [31:0] VFSUB_H = 32'b1000010??????????010?????0110011; - localparam [31:0] VFSUB_R_H = 32'b1000010??????????110?????0110011; - localparam [31:0] VFMUL_H = 32'b1000011??????????010?????0110011; - localparam [31:0] VFMUL_R_H = 32'b1000011??????????110?????0110011; - localparam [31:0] VFDIV_H = 32'b1000100??????????010?????0110011; - localparam [31:0] VFDIV_R_H = 32'b1000100??????????110?????0110011; - localparam [31:0] VFMIN_H = 32'b1000101??????????010?????0110011; - localparam [31:0] VFMIN_R_H = 32'b1000101??????????110?????0110011; - localparam [31:0] VFMAX_H = 32'b1000110??????????010?????0110011; - localparam [31:0] VFMAX_R_H = 32'b1000110??????????110?????0110011; - localparam [31:0] VFSQRT_H = 32'b100011100000?????010?????0110011; - localparam [31:0] VFMAC_H = 32'b1001000??????????010?????0110011; - localparam [31:0] VFMAC_R_H = 32'b1001000??????????110?????0110011; - localparam [31:0] VFMRE_H = 32'b1001001??????????010?????0110011; - localparam [31:0] VFMRE_R_H = 32'b1001001??????????110?????0110011; - localparam [31:0] VFCLASS_H = 32'b100110000001?????010?????0110011; - localparam [31:0] VFSGNJ_H = 32'b1001101??????????010?????0110011; - localparam [31:0] VFSGNJ_R_H = 32'b1001101??????????110?????0110011; - localparam [31:0] VFSGNJN_H = 32'b1001110??????????010?????0110011; - localparam [31:0] VFSGNJN_R_H = 32'b1001110??????????110?????0110011; - localparam [31:0] VFSGNJX_H = 32'b1001111??????????010?????0110011; - localparam [31:0] VFSGNJX_R_H = 32'b1001111??????????110?????0110011; - localparam [31:0] VFEQ_H = 32'b1010000??????????010?????0110011; - localparam [31:0] VFEQ_R_H = 32'b1010000??????????110?????0110011; - localparam [31:0] VFNE_H = 32'b1010001??????????010?????0110011; - localparam [31:0] VFNE_R_H = 32'b1010001??????????110?????0110011; - localparam [31:0] VFLT_H = 32'b1010010??????????010?????0110011; - localparam [31:0] VFLT_R_H = 32'b1010010??????????110?????0110011; - localparam [31:0] VFGE_H = 32'b1010011??????????010?????0110011; - localparam [31:0] VFGE_R_H = 32'b1010011??????????110?????0110011; - localparam [31:0] VFLE_H = 32'b1010100??????????010?????0110011; - localparam [31:0] VFLE_R_H = 32'b1010100??????????110?????0110011; - localparam [31:0] VFGT_H = 32'b1010101??????????010?????0110011; - localparam [31:0] VFGT_R_H = 32'b1010101??????????110?????0110011; - localparam [31:0] VFMV_X_H = 32'b100110000000?????010?????0110011; - localparam [31:0] VFMV_H_X = 32'b100110000000?????110?????0110011; - localparam [31:0] VFCVT_X_H = 32'b100110000010?????010?????0110011; - localparam [31:0] VFCVT_XU_H = 32'b100110000010?????110?????0110011; - localparam [31:0] VFCVT_H_X = 32'b100110000011?????010?????0110011; - localparam [31:0] VFCVT_H_XU = 32'b100110000011?????110?????0110011; - localparam [31:0] VFCPKA_H_S = 32'b1011000??????????010?????0110011; - localparam [31:0] VFCPKB_H_S = 32'b1011000??????????110?????0110011; - localparam [31:0] VFCPKC_H_S = 32'b1011001??????????010?????0110011; - localparam [31:0] VFCPKD_H_S = 32'b1011001??????????110?????0110011; - localparam [31:0] VFCPKA_H_D = 32'b1011010??????????010?????0110011; - localparam [31:0] VFCPKB_H_D = 32'b1011010??????????110?????0110011; - localparam [31:0] VFCPKC_H_D = 32'b1011011??????????010?????0110011; - localparam [31:0] VFCPKD_H_D = 32'b1011011??????????110?????0110011; - localparam [31:0] VFCVT_S_H = 32'b100110000110?????000?????0110011; - localparam [31:0] VFCVTU_S_H = 32'b100110000110?????100?????0110011; - localparam [31:0] VFCVT_H_S = 32'b100110000100?????010?????0110011; - localparam [31:0] VFCVTU_H_S = 32'b100110000100?????110?????0110011; - localparam [31:0] VFADD_AH = 32'b1000001??????????001?????0110011; - localparam [31:0] VFADD_R_AH = 32'b1000001??????????101?????0110011; - localparam [31:0] VFSUB_AH = 32'b1000010??????????001?????0110011; - localparam [31:0] VFSUB_R_AH = 32'b1000010??????????101?????0110011; - localparam [31:0] VFMUL_AH = 32'b1000011??????????001?????0110011; - localparam [31:0] VFMUL_R_AH = 32'b1000011??????????101?????0110011; - localparam [31:0] VFDIV_AH = 32'b1000100??????????001?????0110011; - localparam [31:0] VFDIV_R_AH = 32'b1000100??????????101?????0110011; - localparam [31:0] VFMIN_AH = 32'b1000101??????????001?????0110011; - localparam [31:0] VFMIN_R_AH = 32'b1000101??????????101?????0110011; - localparam [31:0] VFMAX_AH = 32'b1000110??????????001?????0110011; - localparam [31:0] VFMAX_R_AH = 32'b1000110??????????101?????0110011; - localparam [31:0] VFSQRT_AH = 32'b100011100000?????001?????0110011; - localparam [31:0] VFMAC_AH = 32'b1001000??????????001?????0110011; - localparam [31:0] VFMAC_R_AH = 32'b1001000??????????101?????0110011; - localparam [31:0] VFMRE_AH = 32'b1001001??????????001?????0110011; - localparam [31:0] VFMRE_R_AH = 32'b1001001??????????101?????0110011; - localparam [31:0] VFCLASS_AH = 32'b100110000001?????001?????0110011; - localparam [31:0] VFSGNJ_AH = 32'b1001101??????????001?????0110011; - localparam [31:0] VFSGNJ_R_AH = 32'b1001101??????????101?????0110011; - localparam [31:0] VFSGNJN_AH = 32'b1001110??????????001?????0110011; - localparam [31:0] VFSGNJN_R_AH = 32'b1001110??????????101?????0110011; - localparam [31:0] VFSGNJX_AH = 32'b1001111??????????001?????0110011; - localparam [31:0] VFSGNJX_R_AH = 32'b1001111??????????101?????0110011; - localparam [31:0] VFEQ_AH = 32'b1010000??????????001?????0110011; - localparam [31:0] VFEQ_R_AH = 32'b1010000??????????101?????0110011; - localparam [31:0] VFNE_AH = 32'b1010001??????????001?????0110011; - localparam [31:0] VFNE_R_AH = 32'b1010001??????????101?????0110011; - localparam [31:0] VFLT_AH = 32'b1010010??????????001?????0110011; - localparam [31:0] VFLT_R_AH = 32'b1010010??????????101?????0110011; - localparam [31:0] VFGE_AH = 32'b1010011??????????001?????0110011; - localparam [31:0] VFGE_R_AH = 32'b1010011??????????101?????0110011; - localparam [31:0] VFLE_AH = 32'b1010100??????????001?????0110011; - localparam [31:0] VFLE_R_AH = 32'b1010100??????????101?????0110011; - localparam [31:0] VFGT_AH = 32'b1010101??????????001?????0110011; - localparam [31:0] VFGT_R_AH = 32'b1010101??????????101?????0110011; - localparam [31:0] VFMV_X_AH = 32'b100110000000?????001?????0110011; - localparam [31:0] VFMV_AH_X = 32'b100110000000?????101?????0110011; - localparam [31:0] VFCVT_X_AH = 32'b100110000010?????001?????0110011; - localparam [31:0] VFCVT_XU_AH = 32'b100110000010?????101?????0110011; - localparam [31:0] VFCVT_AH_X = 32'b100110000011?????001?????0110011; - localparam [31:0] VFCVT_AH_XU = 32'b100110000011?????101?????0110011; - localparam [31:0] VFCPKA_AH_S = 32'b1011000??????????001?????0110011; - localparam [31:0] VFCPKB_AH_S = 32'b1011000??????????101?????0110011; - localparam [31:0] VFCPKC_AH_S = 32'b1011001??????????001?????0110011; - localparam [31:0] VFCPKD_AH_S = 32'b1011001??????????101?????0110011; - localparam [31:0] VFCPKA_AH_D = 32'b1011010??????????001?????0110011; - localparam [31:0] VFCPKB_AH_D = 32'b1011010??????????101?????0110011; - localparam [31:0] VFCPKC_AH_D = 32'b1011011??????????001?????0110011; - localparam [31:0] VFCPKD_AH_D = 32'b1011011??????????101?????0110011; - localparam [31:0] VFCVT_S_AH = 32'b100110000101?????000?????0110011; - localparam [31:0] VFCVTU_S_AH = 32'b100110000101?????100?????0110011; - localparam [31:0] VFCVT_AH_S = 32'b100110000100?????001?????0110011; - localparam [31:0] VFCVTU_AH_S = 32'b100110000100?????101?????0110011; - localparam [31:0] VFCVT_H_AH = 32'b100110000101?????010?????0110011; - localparam [31:0] VFCVTU_H_AH = 32'b100110000101?????110?????0110011; - localparam [31:0] VFCVT_AH_H = 32'b100110000110?????001?????0110011; - localparam [31:0] VFCVTU_AH_H = 32'b100110000110?????101?????0110011; - localparam [31:0] VFADD_B = 32'b1000001??????????011?????0110011; - localparam [31:0] VFADD_R_B = 32'b1000001??????????111?????0110011; - localparam [31:0] VFSUB_B = 32'b1000010??????????011?????0110011; - localparam [31:0] VFSUB_R_B = 32'b1000010??????????111?????0110011; - localparam [31:0] VFMUL_B = 32'b1000011??????????011?????0110011; - localparam [31:0] VFMUL_R_B = 32'b1000011??????????111?????0110011; - localparam [31:0] VFDIV_B = 32'b1000100??????????011?????0110011; - localparam [31:0] VFDIV_R_B = 32'b1000100??????????111?????0110011; - localparam [31:0] VFMIN_B = 32'b1000101??????????011?????0110011; - localparam [31:0] VFMIN_R_B = 32'b1000101??????????111?????0110011; - localparam [31:0] VFMAX_B = 32'b1000110??????????011?????0110011; - localparam [31:0] VFMAX_R_B = 32'b1000110??????????111?????0110011; - localparam [31:0] VFSQRT_B = 32'b100011100000?????011?????0110011; - localparam [31:0] VFMAC_B = 32'b1001000??????????011?????0110011; - localparam [31:0] VFMAC_R_B = 32'b1001000??????????111?????0110011; - localparam [31:0] VFMRE_B = 32'b1001001??????????011?????0110011; - localparam [31:0] VFMRE_R_B = 32'b1001001??????????111?????0110011; - localparam [31:0] VFSGNJ_B = 32'b1001101??????????011?????0110011; - localparam [31:0] VFSGNJ_R_B = 32'b1001101??????????111?????0110011; - localparam [31:0] VFSGNJN_B = 32'b1001110??????????011?????0110011; - localparam [31:0] VFSGNJN_R_B = 32'b1001110??????????111?????0110011; - localparam [31:0] VFSGNJX_B = 32'b1001111??????????011?????0110011; - localparam [31:0] VFSGNJX_R_B = 32'b1001111??????????111?????0110011; - localparam [31:0] VFEQ_B = 32'b1010000??????????011?????0110011; - localparam [31:0] VFEQ_R_B = 32'b1010000??????????111?????0110011; - localparam [31:0] VFNE_B = 32'b1010001??????????011?????0110011; - localparam [31:0] VFNE_R_B = 32'b1010001??????????111?????0110011; - localparam [31:0] VFLT_B = 32'b1010010??????????011?????0110011; - localparam [31:0] VFLT_R_B = 32'b1010010??????????111?????0110011; - localparam [31:0] VFGE_B = 32'b1010011??????????011?????0110011; - localparam [31:0] VFGE_R_B = 32'b1010011??????????111?????0110011; - localparam [31:0] VFLE_B = 32'b1010100??????????011?????0110011; - localparam [31:0] VFLE_R_B = 32'b1010100??????????111?????0110011; - localparam [31:0] VFGT_B = 32'b1010101??????????011?????0110011; - localparam [31:0] VFGT_R_B = 32'b1010101??????????111?????0110011; - localparam [31:0] VFMV_X_B = 32'b100110000000?????011?????0110011; - localparam [31:0] VFMV_B_X = 32'b100110000000?????111?????0110011; - localparam [31:0] VFCLASS_B = 32'b100110000001?????011?????0110011; - localparam [31:0] VFCVT_X_B = 32'b100110000010?????011?????0110011; - localparam [31:0] VFCVT_XU_B = 32'b100110000010?????111?????0110011; - localparam [31:0] VFCVT_B_X = 32'b100110000011?????011?????0110011; - localparam [31:0] VFCVT_B_XU = 32'b100110000011?????111?????0110011; - localparam [31:0] VFCPKA_B_S = 32'b1011000??????????011?????0110011; - localparam [31:0] VFCPKB_B_S = 32'b1011000??????????111?????0110011; - localparam [31:0] VFCPKC_B_S = 32'b1011001??????????011?????0110011; - localparam [31:0] VFCPKD_B_S = 32'b1011001??????????111?????0110011; - localparam [31:0] VFCPKA_B_D = 32'b1011010??????????011?????0110011; - localparam [31:0] VFCPKB_B_D = 32'b1011010??????????111?????0110011; - localparam [31:0] VFCPKC_B_D = 32'b1011011??????????011?????0110011; - localparam [31:0] VFCPKD_B_D = 32'b1011011??????????111?????0110011; - localparam [31:0] VFCVT_S_B = 32'b100110000111?????000?????0110011; - localparam [31:0] VFCVTU_S_B = 32'b100110000111?????100?????0110011; - localparam [31:0] VFCVT_B_S = 32'b100110000100?????011?????0110011; - localparam [31:0] VFCVTU_B_S = 32'b100110000100?????111?????0110011; - localparam [31:0] VFCVT_H_B = 32'b100110000111?????010?????0110011; - localparam [31:0] VFCVTU_H_B = 32'b100110000111?????110?????0110011; - localparam [31:0] VFCVT_B_H = 32'b100110000110?????011?????0110011; - localparam [31:0] VFCVTU_B_H = 32'b100110000110?????111?????0110011; - localparam [31:0] VFCVT_AH_B = 32'b100110000111?????001?????0110011; - localparam [31:0] VFCVTU_AH_B = 32'b100110000111?????101?????0110011; - localparam [31:0] VFCVT_B_AH = 32'b100110000101?????011?????0110011; - localparam [31:0] VFCVTU_B_AH = 32'b100110000101?????111?????0110011; - localparam [31:0] VFDOTP_S = 32'b1001010??????????000?????0110011; - localparam [31:0] VFDOTP_R_S = 32'b1001010??????????100?????0110011; - localparam [31:0] VFAVG_S = 32'b1010110??????????000?????0110011; - localparam [31:0] VFAVG_R_S = 32'b1010110??????????100?????0110011; - localparam [31:0] FMULEX_S_H = 32'b0100110??????????????????1010011; - localparam [31:0] FMACEX_S_H = 32'b0101010??????????????????1010011; - localparam [31:0] VFDOTP_H = 32'b1001010??????????010?????0110011; - localparam [31:0] VFDOTP_R_H = 32'b1001010??????????110?????0110011; - localparam [31:0] VFDOTPEX_S_H = 32'b1001011??????????010?????0110011; - localparam [31:0] VFDOTPEX_S_R_H = 32'b1001011??????????110?????0110011; - localparam [31:0] VFAVG_H = 32'b1010110??????????010?????0110011; - localparam [31:0] VFAVG_R_H = 32'b1010110??????????110?????0110011; - localparam [31:0] FMULEX_S_AH = 32'b0100110??????????101?????1010011; - localparam [31:0] FMACEX_S_AH = 32'b0101010??????????101?????1010011; - localparam [31:0] VFDOTP_AH = 32'b1001010??????????001?????0110011; - localparam [31:0] VFDOTP_R_AH = 32'b1001010??????????101?????0110011; - localparam [31:0] VFDOTPEX_S_AH = 32'b1001011??????????001?????0110011; - localparam [31:0] VFDOTPEX_S_R_AH = 32'b1001011??????????101?????0110011; - localparam [31:0] VFAVG_AH = 32'b1010110??????????001?????0110011; - localparam [31:0] VFAVG_R_AH = 32'b1010110??????????101?????0110011; - localparam [31:0] FMULEX_S_B = 32'b0100111??????????????????1010011; - localparam [31:0] FMACEX_S_B = 32'b0101011??????????????????1010011; - localparam [31:0] VFDOTP_B = 32'b1001010??????????011?????0110011; - localparam [31:0] VFDOTP_R_B = 32'b1001010??????????111?????0110011; - localparam [31:0] VFDOTPEX_S_B = 32'b1001011??????????011?????0110011; - localparam [31:0] VFDOTPEX_S_R_B = 32'b1001011??????????111?????0110011; - localparam [31:0] VFAVG_B = 32'b1010110??????????011?????0110011; - localparam [31:0] VFAVG_R_B = 32'b1010110??????????111?????0110011; - /* CSR Addresses */ - localparam logic [11:0] CSR_FFLAGS = 12'h1; - localparam logic [11:0] CSR_FRM = 12'h2; - localparam logic [11:0] CSR_FCSR = 12'h3; - localparam logic [11:0] CSR_USTATUS = 12'h0; - localparam logic [11:0] CSR_UIE = 12'h4; - localparam logic [11:0] CSR_UTVEC = 12'h5; - localparam logic [11:0] CSR_VSTART = 12'h8; - localparam logic [11:0] CSR_VXSAT = 12'h9; - localparam logic [11:0] CSR_VXRM = 12'ha; - localparam logic [11:0] CSR_VCSR = 12'hf; - localparam logic [11:0] CSR_USCRATCH = 12'h40; - localparam logic [11:0] CSR_UEPC = 12'h41; - localparam logic [11:0] CSR_UCAUSE = 12'h42; - localparam logic [11:0] CSR_UTVAL = 12'h43; - localparam logic [11:0] CSR_UIP = 12'h44; - localparam logic [11:0] CSR_CYCLE = 12'hc00; - localparam logic [11:0] CSR_TIME = 12'hc01; - localparam logic [11:0] CSR_INSTRET = 12'hc02; - localparam logic [11:0] CSR_HPMCOUNTER3 = 12'hc03; - localparam logic [11:0] CSR_HPMCOUNTER4 = 12'hc04; - localparam logic [11:0] CSR_HPMCOUNTER5 = 12'hc05; - localparam logic [11:0] CSR_HPMCOUNTER6 = 12'hc06; - localparam logic [11:0] CSR_HPMCOUNTER7 = 12'hc07; - localparam logic [11:0] CSR_HPMCOUNTER8 = 12'hc08; - localparam logic [11:0] CSR_HPMCOUNTER9 = 12'hc09; - localparam logic [11:0] CSR_HPMCOUNTER10 = 12'hc0a; - localparam logic [11:0] CSR_HPMCOUNTER11 = 12'hc0b; - localparam logic [11:0] CSR_HPMCOUNTER12 = 12'hc0c; - localparam logic [11:0] CSR_HPMCOUNTER13 = 12'hc0d; - localparam logic [11:0] CSR_HPMCOUNTER14 = 12'hc0e; - localparam logic [11:0] CSR_HPMCOUNTER15 = 12'hc0f; - localparam logic [11:0] CSR_HPMCOUNTER16 = 12'hc10; - localparam logic [11:0] CSR_HPMCOUNTER17 = 12'hc11; - localparam logic [11:0] CSR_HPMCOUNTER18 = 12'hc12; - localparam logic [11:0] CSR_HPMCOUNTER19 = 12'hc13; - localparam logic [11:0] CSR_HPMCOUNTER20 = 12'hc14; - localparam logic [11:0] CSR_HPMCOUNTER21 = 12'hc15; - localparam logic [11:0] CSR_HPMCOUNTER22 = 12'hc16; - localparam logic [11:0] CSR_HPMCOUNTER23 = 12'hc17; - localparam logic [11:0] CSR_HPMCOUNTER24 = 12'hc18; - localparam logic [11:0] CSR_HPMCOUNTER25 = 12'hc19; - localparam logic [11:0] CSR_HPMCOUNTER26 = 12'hc1a; - localparam logic [11:0] CSR_HPMCOUNTER27 = 12'hc1b; - localparam logic [11:0] CSR_HPMCOUNTER28 = 12'hc1c; - localparam logic [11:0] CSR_HPMCOUNTER29 = 12'hc1d; - localparam logic [11:0] CSR_HPMCOUNTER30 = 12'hc1e; - localparam logic [11:0] CSR_HPMCOUNTER31 = 12'hc1f; - localparam logic [11:0] CSR_VL = 12'hc20; - localparam logic [11:0] CSR_VTYPE = 12'hc21; - localparam logic [11:0] CSR_VLENB = 12'hc22; - localparam logic [11:0] CSR_SSTATUS = 12'h100; - localparam logic [11:0] CSR_SEDELEG = 12'h102; - localparam logic [11:0] CSR_SIDELEG = 12'h103; - localparam logic [11:0] CSR_SIE = 12'h104; - localparam logic [11:0] CSR_STVEC = 12'h105; - localparam logic [11:0] CSR_SCOUNTEREN = 12'h106; - localparam logic [11:0] CSR_SSCRATCH = 12'h140; - localparam logic [11:0] CSR_SEPC = 12'h141; - localparam logic [11:0] CSR_SCAUSE = 12'h142; - localparam logic [11:0] CSR_STVAL = 12'h143; - localparam logic [11:0] CSR_SIP = 12'h144; - localparam logic [11:0] CSR_SATP = 12'h180; - localparam logic [11:0] CSR_VSSTATUS = 12'h200; - localparam logic [11:0] CSR_VSIE = 12'h204; - localparam logic [11:0] CSR_VSTVEC = 12'h205; - localparam logic [11:0] CSR_VSSCRATCH = 12'h240; - localparam logic [11:0] CSR_VSEPC = 12'h241; - localparam logic [11:0] CSR_VSCAUSE = 12'h242; - localparam logic [11:0] CSR_VSTVAL = 12'h243; - localparam logic [11:0] CSR_VSIP = 12'h244; - localparam logic [11:0] CSR_VSATP = 12'h280; - localparam logic [11:0] CSR_HSTATUS = 12'h600; - localparam logic [11:0] CSR_HEDELEG = 12'h602; - localparam logic [11:0] CSR_HIDELEG = 12'h603; - localparam logic [11:0] CSR_HIE = 12'h604; - localparam logic [11:0] CSR_HTIMEDELTA = 12'h605; - localparam logic [11:0] CSR_HCOUNTEREN = 12'h606; - localparam logic [11:0] CSR_HGEIE = 12'h607; - localparam logic [11:0] CSR_HTVAL = 12'h643; - localparam logic [11:0] CSR_HIP = 12'h644; - localparam logic [11:0] CSR_HVIP = 12'h645; - localparam logic [11:0] CSR_HTINST = 12'h64a; - localparam logic [11:0] CSR_HGATP = 12'h680; - localparam logic [11:0] CSR_HGEIP = 12'he12; - localparam logic [11:0] CSR_UTVT = 12'h7; - localparam logic [11:0] CSR_UNXTI = 12'h45; - localparam logic [11:0] CSR_UINTSTATUS = 12'h46; - localparam logic [11:0] CSR_USCRATCHCSW = 12'h48; - localparam logic [11:0] CSR_USCRATCHCSWL = 12'h49; - localparam logic [11:0] CSR_STVT = 12'h107; - localparam logic [11:0] CSR_SNXTI = 12'h145; - localparam logic [11:0] CSR_SINTSTATUS = 12'h146; - localparam logic [11:0] CSR_SSCRATCHCSW = 12'h148; - localparam logic [11:0] CSR_SSCRATCHCSWL = 12'h149; - localparam logic [11:0] CSR_MTVT = 12'h307; - localparam logic [11:0] CSR_MNXTI = 12'h345; - localparam logic [11:0] CSR_MINTSTATUS = 12'h346; - localparam logic [11:0] CSR_MSCRATCHCSW = 12'h348; - localparam logic [11:0] CSR_MSCRATCHCSWL = 12'h349; - localparam logic [11:0] CSR_MSTATUS = 12'h300; - localparam logic [11:0] CSR_MISA = 12'h301; - localparam logic [11:0] CSR_MEDELEG = 12'h302; - localparam logic [11:0] CSR_MIDELEG = 12'h303; - localparam logic [11:0] CSR_MIE = 12'h304; - localparam logic [11:0] CSR_MTVEC = 12'h305; - localparam logic [11:0] CSR_MCOUNTEREN = 12'h306; - localparam logic [11:0] CSR_MCOUNTINHIBIT = 12'h320; - localparam logic [11:0] CSR_MSCRATCH = 12'h340; - localparam logic [11:0] CSR_MEPC = 12'h341; - localparam logic [11:0] CSR_MCAUSE = 12'h342; - localparam logic [11:0] CSR_MTVAL = 12'h343; - localparam logic [11:0] CSR_MIP = 12'h344; - localparam logic [11:0] CSR_MTINST = 12'h34a; - localparam logic [11:0] CSR_MTVAL2 = 12'h34b; - localparam logic [11:0] CSR_PMPCFG0 = 12'h3a0; - localparam logic [11:0] CSR_PMPCFG1 = 12'h3a1; - localparam logic [11:0] CSR_PMPCFG2 = 12'h3a2; - localparam logic [11:0] CSR_PMPCFG3 = 12'h3a3; - localparam logic [11:0] CSR_PMPADDR0 = 12'h3b0; - localparam logic [11:0] CSR_PMPADDR1 = 12'h3b1; - localparam logic [11:0] CSR_PMPADDR2 = 12'h3b2; - localparam logic [11:0] CSR_PMPADDR3 = 12'h3b3; - localparam logic [11:0] CSR_PMPADDR4 = 12'h3b4; - localparam logic [11:0] CSR_PMPADDR5 = 12'h3b5; - localparam logic [11:0] CSR_PMPADDR6 = 12'h3b6; - localparam logic [11:0] CSR_PMPADDR7 = 12'h3b7; - localparam logic [11:0] CSR_PMPADDR8 = 12'h3b8; - localparam logic [11:0] CSR_PMPADDR9 = 12'h3b9; - localparam logic [11:0] CSR_PMPADDR10 = 12'h3ba; - localparam logic [11:0] CSR_PMPADDR11 = 12'h3bb; - localparam logic [11:0] CSR_PMPADDR12 = 12'h3bc; - localparam logic [11:0] CSR_PMPADDR13 = 12'h3bd; - localparam logic [11:0] CSR_PMPADDR14 = 12'h3be; - localparam logic [11:0] CSR_PMPADDR15 = 12'h3bf; - localparam logic [11:0] CSR_TSELECT = 12'h7a0; - localparam logic [11:0] CSR_TDATA1 = 12'h7a1; - localparam logic [11:0] CSR_TDATA2 = 12'h7a2; - localparam logic [11:0] CSR_TDATA3 = 12'h7a3; - localparam logic [11:0] CSR_DCSR = 12'h7b0; - localparam logic [11:0] CSR_DPC = 12'h7b1; - localparam logic [11:0] CSR_DSCRATCH0 = 12'h7b2; - localparam logic [11:0] CSR_DSCRATCH1 = 12'h7b3; - localparam logic [11:0] CSR_MCYCLE = 12'hb00; - localparam logic [11:0] CSR_MINSTRET = 12'hb02; - localparam logic [11:0] CSR_MHPMCOUNTER3 = 12'hb03; - localparam logic [11:0] CSR_MHPMCOUNTER4 = 12'hb04; - localparam logic [11:0] CSR_MHPMCOUNTER5 = 12'hb05; - localparam logic [11:0] CSR_MHPMCOUNTER6 = 12'hb06; - localparam logic [11:0] CSR_MHPMCOUNTER7 = 12'hb07; - localparam logic [11:0] CSR_MHPMCOUNTER8 = 12'hb08; - localparam logic [11:0] CSR_MHPMCOUNTER9 = 12'hb09; - localparam logic [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; - localparam logic [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; - localparam logic [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; - localparam logic [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; - localparam logic [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; - localparam logic [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; - localparam logic [11:0] CSR_MHPMCOUNTER16 = 12'hb10; - localparam logic [11:0] CSR_MHPMCOUNTER17 = 12'hb11; - localparam logic [11:0] CSR_MHPMCOUNTER18 = 12'hb12; - localparam logic [11:0] CSR_MHPMCOUNTER19 = 12'hb13; - localparam logic [11:0] CSR_MHPMCOUNTER20 = 12'hb14; - localparam logic [11:0] CSR_MHPMCOUNTER21 = 12'hb15; - localparam logic [11:0] CSR_MHPMCOUNTER22 = 12'hb16; - localparam logic [11:0] CSR_MHPMCOUNTER23 = 12'hb17; - localparam logic [11:0] CSR_MHPMCOUNTER24 = 12'hb18; - localparam logic [11:0] CSR_MHPMCOUNTER25 = 12'hb19; - localparam logic [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; - localparam logic [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; - localparam logic [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; - localparam logic [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; - localparam logic [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; - localparam logic [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; - localparam logic [11:0] CSR_MHPMEVENT3 = 12'h323; - localparam logic [11:0] CSR_MHPMEVENT4 = 12'h324; - localparam logic [11:0] CSR_MHPMEVENT5 = 12'h325; - localparam logic [11:0] CSR_MHPMEVENT6 = 12'h326; - localparam logic [11:0] CSR_MHPMEVENT7 = 12'h327; - localparam logic [11:0] CSR_MHPMEVENT8 = 12'h328; - localparam logic [11:0] CSR_MHPMEVENT9 = 12'h329; - localparam logic [11:0] CSR_MHPMEVENT10 = 12'h32a; - localparam logic [11:0] CSR_MHPMEVENT11 = 12'h32b; - localparam logic [11:0] CSR_MHPMEVENT12 = 12'h32c; - localparam logic [11:0] CSR_MHPMEVENT13 = 12'h32d; - localparam logic [11:0] CSR_MHPMEVENT14 = 12'h32e; - localparam logic [11:0] CSR_MHPMEVENT15 = 12'h32f; - localparam logic [11:0] CSR_MHPMEVENT16 = 12'h330; - localparam logic [11:0] CSR_MHPMEVENT17 = 12'h331; - localparam logic [11:0] CSR_MHPMEVENT18 = 12'h332; - localparam logic [11:0] CSR_MHPMEVENT19 = 12'h333; - localparam logic [11:0] CSR_MHPMEVENT20 = 12'h334; - localparam logic [11:0] CSR_MHPMEVENT21 = 12'h335; - localparam logic [11:0] CSR_MHPMEVENT22 = 12'h336; - localparam logic [11:0] CSR_MHPMEVENT23 = 12'h337; - localparam logic [11:0] CSR_MHPMEVENT24 = 12'h338; - localparam logic [11:0] CSR_MHPMEVENT25 = 12'h339; - localparam logic [11:0] CSR_MHPMEVENT26 = 12'h33a; - localparam logic [11:0] CSR_MHPMEVENT27 = 12'h33b; - localparam logic [11:0] CSR_MHPMEVENT28 = 12'h33c; - localparam logic [11:0] CSR_MHPMEVENT29 = 12'h33d; - localparam logic [11:0] CSR_MHPMEVENT30 = 12'h33e; - localparam logic [11:0] CSR_MHPMEVENT31 = 12'h33f; - localparam logic [11:0] CSR_TRACE = 12'h7d0; - localparam logic [11:0] CSR_MVENDORID = 12'hf11; - localparam logic [11:0] CSR_MARCHID = 12'hf12; - localparam logic [11:0] CSR_MIMPID = 12'hf13; - localparam logic [11:0] CSR_MHARTID = 12'hf14; - localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615; - localparam logic [11:0] CSR_CYCLEH = 12'hc80; - localparam logic [11:0] CSR_TIMEH = 12'hc81; - localparam logic [11:0] CSR_INSTRETH = 12'hc82; - localparam logic [11:0] CSR_HPMCOUNTER3H = 12'hc83; - localparam logic [11:0] CSR_HPMCOUNTER4H = 12'hc84; - localparam logic [11:0] CSR_HPMCOUNTER5H = 12'hc85; - localparam logic [11:0] CSR_HPMCOUNTER6H = 12'hc86; - localparam logic [11:0] CSR_HPMCOUNTER7H = 12'hc87; - localparam logic [11:0] CSR_HPMCOUNTER8H = 12'hc88; - localparam logic [11:0] CSR_HPMCOUNTER9H = 12'hc89; - localparam logic [11:0] CSR_HPMCOUNTER10H = 12'hc8a; - localparam logic [11:0] CSR_HPMCOUNTER11H = 12'hc8b; - localparam logic [11:0] CSR_HPMCOUNTER12H = 12'hc8c; - localparam logic [11:0] CSR_HPMCOUNTER13H = 12'hc8d; - localparam logic [11:0] CSR_HPMCOUNTER14H = 12'hc8e; - localparam logic [11:0] CSR_HPMCOUNTER15H = 12'hc8f; - localparam logic [11:0] CSR_HPMCOUNTER16H = 12'hc90; - localparam logic [11:0] CSR_HPMCOUNTER17H = 12'hc91; - localparam logic [11:0] CSR_HPMCOUNTER18H = 12'hc92; - localparam logic [11:0] CSR_HPMCOUNTER19H = 12'hc93; - localparam logic [11:0] CSR_HPMCOUNTER20H = 12'hc94; - localparam logic [11:0] CSR_HPMCOUNTER21H = 12'hc95; - localparam logic [11:0] CSR_HPMCOUNTER22H = 12'hc96; - localparam logic [11:0] CSR_HPMCOUNTER23H = 12'hc97; - localparam logic [11:0] CSR_HPMCOUNTER24H = 12'hc98; - localparam logic [11:0] CSR_HPMCOUNTER25H = 12'hc99; - localparam logic [11:0] CSR_HPMCOUNTER26H = 12'hc9a; - localparam logic [11:0] CSR_HPMCOUNTER27H = 12'hc9b; - localparam logic [11:0] CSR_HPMCOUNTER28H = 12'hc9c; - localparam logic [11:0] CSR_HPMCOUNTER29H = 12'hc9d; - localparam logic [11:0] CSR_HPMCOUNTER30H = 12'hc9e; - localparam logic [11:0] CSR_HPMCOUNTER31H = 12'hc9f; - localparam logic [11:0] CSR_MSTATUSH = 12'h310; - localparam logic [11:0] CSR_MCYCLEH = 12'hb80; - localparam logic [11:0] CSR_MINSTRETH = 12'hb82; - localparam logic [11:0] CSR_MHPMCOUNTER3H = 12'hb83; - localparam logic [11:0] CSR_MHPMCOUNTER4H = 12'hb84; - localparam logic [11:0] CSR_MHPMCOUNTER5H = 12'hb85; - localparam logic [11:0] CSR_MHPMCOUNTER6H = 12'hb86; - localparam logic [11:0] CSR_MHPMCOUNTER7H = 12'hb87; - localparam logic [11:0] CSR_MHPMCOUNTER8H = 12'hb88; - localparam logic [11:0] CSR_MHPMCOUNTER9H = 12'hb89; - localparam logic [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; - localparam logic [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; - localparam logic [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; - localparam logic [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; - localparam logic [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; - localparam logic [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; - localparam logic [11:0] CSR_MHPMCOUNTER16H = 12'hb90; - localparam logic [11:0] CSR_MHPMCOUNTER17H = 12'hb91; - localparam logic [11:0] CSR_MHPMCOUNTER18H = 12'hb92; - localparam logic [11:0] CSR_MHPMCOUNTER19H = 12'hb93; - localparam logic [11:0] CSR_MHPMCOUNTER20H = 12'hb94; - localparam logic [11:0] CSR_MHPMCOUNTER21H = 12'hb95; - localparam logic [11:0] CSR_MHPMCOUNTER22H = 12'hb96; - localparam logic [11:0] CSR_MHPMCOUNTER23H = 12'hb97; - localparam logic [11:0] CSR_MHPMCOUNTER24H = 12'hb98; - localparam logic [11:0] CSR_MHPMCOUNTER25H = 12'hb99; - localparam logic [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; - localparam logic [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; - localparam logic [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; - localparam logic [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; - localparam logic [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; - localparam logic [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; -endpackage diff --git a/opcodes-dma b/opcodes-dma new file mode 100644 index 00000000..6909e522 --- /dev/null +++ b/opcodes-dma @@ -0,0 +1,8 @@ +dmsrc rs1 rs2 11..7=0 31..25=0 14..12=0 6..2=0x0A 1..0=0x3 +dmdst rs1 rs2 11..7=0 31..25=1 14..12=0 6..2=0x0A 1..0=0x3 +dmcpyi rd rs1 imm5 31..25=2 14..12=0 6..2=0x0A 1..0=0x3 +dmcpy rd rs1 rs2 31..25=3 14..12=0 6..2=0x0A 1..0=0x3 +dmstati rd imm5 19..15=0 31..25=4 14..12=0 6..2=0x0A 1..0=0x3 +dmstat rd rs2 19..15=0 31..25=5 14..12=0 6..2=0x0A 1..0=0x3 +dmstr rs1 rs2 11..7=0 31..25=6 14..12=0 6..2=0x0A 1..0=0x3 +dmrep rs1 24..20=0 11..7=0 31..25=7 14..12=0 6..2=0x0A 1..0=0x3 diff --git a/opcodes-flt-occamy b/opcodes-flt-occamy new file mode 100644 index 00000000..f5ff0064 --- /dev/null +++ b/opcodes-flt-occamy @@ -0,0 +1,789 @@ +# SMALLFLOAT EXTENSION OPCODES +# +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, +# shamtw, shamt, rm + +# ASCII Art from here: https://fsymbols.com/generators/carty/ + +# ░██████╗░█████╗░░█████╗░██╗░░░░░░█████╗░██████╗░ +# ██╔════╝██╔══██╗██╔══██╗██║░░░░░██╔══██╗██╔══██╗ +# ╚█████╗░██║░░╚═╝███████║██║░░░░░███████║██████╔╝ +# ░╚═══██╗██║░░██╗██╔══██║██║░░░░░██╔══██║██╔══██╗ +# ██████╔╝╚█████╔╝██║░░██║███████╗██║░░██║██║░░██║ +# ╚═════╝░░╚════╝░╚═╝░░╚═╝╚══════╝╚═╝░░╚═╝╚═╝░░╚═╝ + +#SMALLFLOAT SCALAR (fmt: 0=s, 1=d, 2=h (ha with rm=0b101) 3=b) +# same instrucion format as F extension +# collected under "Xsmallfloat" name - naming not final + +# █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▀█ █▄▄ █▀░ + +# RV32Xfhalf - half-precision floats +# startgroup Xfhalf half-precision floats +flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 +fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 +fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 +fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 +fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 +flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 +fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 +# RV64Xfhalf: in addition to the above +fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +# XfhalfwithF - half-precision conversions with F extension +fcvt.s.h rd rs1 24..20=2 31..27=0x08 14..12=0 26..25=0 6..2=0x14 1..0=3 +fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +# XfhalfwithD - half-precision conversions with D extension (in addition to XfhalfwithF) +fcvt.d.h rd rs1 24..20=2 31..27=0x08 14..12=0 26..25=1 6..2=0x14 1..0=3 +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   █▀█ █▀█ █▄▄ █▀░ + +# RV32Xfalthalf - alternate half-precision floats +# startgroup Xfalthalf alternate half-precision floats +@flah rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 +@fsah imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 +@fmadd.ah rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +@fmsub.ah rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +@fnmsub.ah rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +@fnmadd.ah rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 +@fadd.ah rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +@fsub.ah rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +@fmul.ah rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +@fdiv.ah rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +@fsqrt.ah rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 +@fsgnj.ah rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +@fsgnjn.ah rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +@fsgnjx.ah rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +@fmin.ah rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +@fmax.ah rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +@feq.ah rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 +@flt.ah rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +@fle.ah rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +@fcvt.w.ah rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.wu.ah rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +@fmv.x.ah rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +@fclass.ah rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 +@fmv.ah.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 +# RV64Xfhalf: in addition to the above +@fcvt.l.ah rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.lu.ah rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +# XfhalfwithF - half-precision conversions with F extension +@fcvt.s.ah rd rs1 24..20=2 31..27=0x08 14..12=0 26..25=0 6..2=0x14 1..0=3 +@fcvt.ah.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +# XfhalfwithD - half-precision conversions with D extension (in addition to XfhalfwithF) +@fcvt.d.ah rd rs1 24..20=2 31..27=0x08 14..12=0 26..25=1 6..2=0x14 1..0=3 +@fcvt.ah.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +# Xfalthalfwithhalf - alternate half-precision conversions with Xfhalf extension +fcvt.h.h rd rs1 24..20=2 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.h rd rs1 24..20=2 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.h.ah rd rs1 24..20=2 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +@fcvt.ah.ah rd rs1 24..20=2 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +# end_group + +# █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# RV32Xfquarter - quarter-precision floats +# startgroup Xfquarter quarter-precision floats +# b collides with quad precision (q) so they are pseudo here (not pseudo for LLVM). +flb rd rs1 imm12 14..12=0 6..2=0x01 1..0=3 +fsb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x09 1..0=3 +@fmadd.b rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 +@fmsub.b rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 +@fnmsub.b rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 +@fnmadd.b rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 +@fadd.b rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 +@fsub.b rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 +@fmul.b rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 +@fdiv.b rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 +@fsqrt.b rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 +@fsgnj.b rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fsgnjn.b rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fsgnjx.b rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +@fmin.b rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fmax.b rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 +@feq.b rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 +@flt.b rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fle.b rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fcvt.w.b rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.wu.b rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.b.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.b.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +@fmv.x.b rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fclass.b rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fmv.b.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=3 6..2=0x14 1..0=3 +# RV64Xfquarter: in addition to the above +@fcvt.l.b rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.lu.b rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.b.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.b.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +# XfquarterwithF - quarter-precision conversions with F extension +@fcvt.s.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=0 6..2=0x14 1..0=3 +@fcvt.b.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +# XfquarterwithD - quarter-precision conversions with D extension (in addition to XfquarterwithF) +@fcvt.d.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=1 6..2=0x14 1..0=3 +@fcvt.b.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +# Xfquarterwithhalf - quarter-precision conversions with Xfhalf extension +fcvt.h.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=2 6..2=0x14 1..0=3 +fcvt.b.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +# Xfquarterwithalthalf - quarter-precision conversions with Xfalthalf extension +@fcvt.ah.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=2 6..2=0x14 1..0=3 +@fcvt.b.ah rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +# end_group + + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# RV32Xfaltquarter - alternate quarter-precision floats +# startgroup Xfaltquarter alternate quarter-precision floats +# ab collides with quad precision (q) so they are pseudo here. +@flab rd rs1 imm12 14..12=0 6..2=0x01 1..0=3 +@fsab imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x09 1..0=3 +@fmadd.ab rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 +@fmsub.ab rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 +@fnmsub.ab rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 +@fnmadd.ab rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 +@fadd.ab rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 +@fsub.ab rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 +@fmul.ab rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 +@fdiv.ab rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 +@fsqrt.ab rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 +@fsgnj.ab rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fsgnjn.ab rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fsgnjx.ab rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +@fmin.ab rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fmax.ab rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 +@feq.ab rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 +@flt.ab rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fle.ab rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fcvt.w.ab rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.wu.ab rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.ab.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +@fcvt.ab.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +@fmv.x.ab rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fclass.ab rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 +@fmv.ab.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=3 6..2=0x14 1..0=3 +# RV64Xfaltquarter: in addition to the above +@fcvt.l.ab rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +@fcvt.lu.ab rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 # same as .b +# XfaltquarterwithF - quarter-precision conversions with F extension +@fcvt.s.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=0 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +# XfaltquarterwithD - quarter-precision conversions with D extension (in addition to XfquarterwithF) +@fcvt.d.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=1 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +# Xfaltquarterwithhalf - quarter-precision conversions with Xfhalf extension +@fcvt.h.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=2 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +# Xfaltquarterwithalthalf - quarter-precision conversions with Xfalthalf extension +@fcvt.ah.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=2 6..2=0x14 1..0=3 # same as .b +@fcvt.ab.ah rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 # same as .b +# Xfaltquarterwithquarter - quarter-precision conversions with Xfalthalf extension +fcvt.b.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fcvt.ab.b rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fcvt.b.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=3 6..2=0x14 1..0=3 +@fcvt.ab.ab rd rs1 24..20=3 31..27=0x08 14..12=0 26..25=3 6..2=0x14 1..0=3 +# end_group + + +# ██╗░░░██╗███████╗░█████╗░████████╗░█████╗░██████╗░ +# ██║░░░██║██╔════╝██╔══██╗╚══██╔══╝██╔══██╗██╔══██╗ +# ╚██╗░██╔╝█████╗░░██║░░╚═╝░░░██║░░░██║░░██║██████╔╝ +# ░╚████╔╝░██╔══╝░░██║░░██╗░░░██║░░░██║░░██║██╔══██╗ +# ░░╚██╔╝░░███████╗╚█████╔╝░░░██║░░░╚█████╔╝██║░░██║ +# ░░░╚═╝░░░╚══════╝░╚════╝░░░░╚═╝░░░░╚════╝░╚═╝░░╚═╝ + +#SMALLFLOAT VECTORIAL (vfmt: 0=s (ILLEGAL in RV32), 1=ah, 2=h, 3=b) +# 31..30=2 29..25=vecfltop rs2 rs1 14=R 13..12=vfmt rd 6..2=OP 1..0=3 +# 29..25=0x00 is already used by a bitman instruction +# collected under Xfvec - naming not final + +# █▀ █ █▄░█ █▀▀ █░░ █▀▀ +# ▄█ █ █░▀█ █▄█ █▄▄ ██▄ + +# Xfvecsingle - vectorial single-precision floats - requires FLEN >= 64 +# startgroup Xfvecsingle vectorial single-precision floats - requires FLEN >= 64 +vfadd.s rd rs1 rs2 31..30=2 29..25=0x01 14=0 13..12=0 6..2=0x0C 1..0=3 +vfadd.r.s rd rs1 rs2 31..30=2 29..25=0x01 14=1 13..12=0 6..2=0x0C 1..0=3 +vfsub.s rd rs1 rs2 31..30=2 29..25=0x02 14=0 13..12=0 6..2=0x0C 1..0=3 +vfsub.r.s rd rs1 rs2 31..30=2 29..25=0x02 14=1 13..12=0 6..2=0x0C 1..0=3 +vfmul.s rd rs1 rs2 31..30=2 29..25=0x03 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmul.r.s rd rs1 rs2 31..30=2 29..25=0x03 14=1 13..12=0 6..2=0x0C 1..0=3 +vfdiv.s rd rs1 rs2 31..30=2 29..25=0x04 14=0 13..12=0 6..2=0x0C 1..0=3 +vfdiv.r.s rd rs1 rs2 31..30=2 29..25=0x04 14=1 13..12=0 6..2=0x0C 1..0=3 +vfmin.s rd rs1 rs2 31..30=2 29..25=0x05 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmin.r.s rd rs1 rs2 31..30=2 29..25=0x05 14=1 13..12=0 6..2=0x0C 1..0=3 +vfmax.s rd rs1 rs2 31..30=2 29..25=0x06 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmax.r.s rd rs1 rs2 31..30=2 29..25=0x06 14=1 13..12=0 6..2=0x0C 1..0=3 +vfsqrt.s rd rs1 24..20=0 31..30=2 29..25=0x07 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmac.s rd rs1 rs2 31..30=2 29..25=0x08 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmac.r.s rd rs1 rs2 31..30=2 29..25=0x08 14=1 13..12=0 6..2=0x0C 1..0=3 +vfmre.s rd rs1 rs2 31..30=2 29..25=0x09 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmre.r.s rd rs1 rs2 31..30=2 29..25=0x09 14=1 13..12=0 6..2=0x0C 1..0=3 +vfclass.s rd rs1 24..20=1 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfsgnj.s rd rs1 rs2 31..30=2 29..25=0x0D 14=0 13..12=0 6..2=0x0C 1..0=3 +vfsgnj.r.s rd rs1 rs2 31..30=2 29..25=0x0D 14=1 13..12=0 6..2=0x0C 1..0=3 +vfsgnjn.s rd rs1 rs2 31..30=2 29..25=0x0E 14=0 13..12=0 6..2=0x0C 1..0=3 +vfsgnjn.r.s rd rs1 rs2 31..30=2 29..25=0x0E 14=1 13..12=0 6..2=0x0C 1..0=3 +vfsgnjx.s rd rs1 rs2 31..30=2 29..25=0x0F 14=0 13..12=0 6..2=0x0C 1..0=3 +vfsgnjx.r.s rd rs1 rs2 31..30=2 29..25=0x0F 14=1 13..12=0 6..2=0x0C 1..0=3 +vfeq.s rd rs1 rs2 31..30=2 29..25=0x10 14=0 13..12=0 6..2=0x0C 1..0=3 +vfeq.r.s rd rs1 rs2 31..30=2 29..25=0x10 14=1 13..12=0 6..2=0x0C 1..0=3 +vfne.s rd rs1 rs2 31..30=2 29..25=0x11 14=0 13..12=0 6..2=0x0C 1..0=3 +vfne.r.s rd rs1 rs2 31..30=2 29..25=0x11 14=1 13..12=0 6..2=0x0C 1..0=3 +vflt.s rd rs1 rs2 31..30=2 29..25=0x12 14=0 13..12=0 6..2=0x0C 1..0=3 +vflt.r.s rd rs1 rs2 31..30=2 29..25=0x12 14=1 13..12=0 6..2=0x0C 1..0=3 +vfge.s rd rs1 rs2 31..30=2 29..25=0x13 14=0 13..12=0 6..2=0x0C 1..0=3 +vfge.r.s rd rs1 rs2 31..30=2 29..25=0x13 14=1 13..12=0 6..2=0x0C 1..0=3 +vfle.s rd rs1 rs2 31..30=2 29..25=0x14 14=0 13..12=0 6..2=0x0C 1..0=3 +vfle.r.s rd rs1 rs2 31..30=2 29..25=0x14 14=1 13..12=0 6..2=0x0C 1..0=3 +vfgt.s rd rs1 rs2 31..30=2 29..25=0x15 14=0 13..12=0 6..2=0x0C 1..0=3 +vfgt.r.s rd rs1 rs2 31..30=2 29..25=0x15 14=1 13..12=0 6..2=0x0C 1..0=3 +# XfvecsinglenothirtytwoD: only unless RV32D +vfmv.x.s rd rs1 24..20=0 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfmv.s.x rd rs1 24..20=0 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcvt.x.s rd rs1 24..20=2 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcvt.xu.s rd rs1 24..20=2 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcvt.s.x rd rs1 24..20=3 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcvt.s.xu rd rs1 24..20=3 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +# XfvecsinglewithF - vectorial single-precision conversions with F extension, a-d legality depends on FLEN +vfcpka.s.s rd rs1 rs2 31..30=2 29..25=0x18 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcpkb.s.s rd rs1 rs2 31..30=2 29..25=0x18 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcpkc.s.s rd rs1 rs2 31..30=2 29..25=0x19 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcpkd.s.s rd rs1 rs2 31..30=2 29..25=0x19 14=1 13..12=0 6..2=0x0C 1..0=3 +# XfvecsinglewithD - vectorial single-precision conversions with D extension, a-d legality depends on FLEN (in addition to the above) +vfcpka.s.d rd rs1 rs2 31..30=2 29..25=0x1A 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcpkb.s.d rd rs1 rs2 31..30=2 29..25=0x1A 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcpkc.s.d rd rs1 rs2 31..30=2 29..25=0x1B 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcpkd.s.d rd rs1 rs2 31..30=2 29..25=0x1B 14=1 13..12=0 6..2=0x0C 1..0=3 +# Xfvecalthalfwithhalf - vectorial alternate half-precision conversions with Xfvechalf extension +vfcvt.h.h rd rs1 24..20=5 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.h.ah rd rs1 24..20=5 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.ah.h rd rs1 24..20=5 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcvtu.h.h rd rs1 24..20=5 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.h.ah rd rs1 24..20=5 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.ah.h rd rs1 24..20=5 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +# end_group + +# █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▀█ █▄▄ █▀░ + +# Xfvechalf - vectorial half-precision floats - requires FLEN >= 32 +# startgroup Xfvechalf vectorial half-precision floats - requires FLEN >= 32 +vfadd.h rd rs1 rs2 31..30=2 29..25=0x01 14=0 13..12=2 6..2=0x0C 1..0=3 +vfadd.r.h rd rs1 rs2 31..30=2 29..25=0x01 14=1 13..12=2 6..2=0x0C 1..0=3 +vfsub.h rd rs1 rs2 31..30=2 29..25=0x02 14=0 13..12=2 6..2=0x0C 1..0=3 +vfsub.r.h rd rs1 rs2 31..30=2 29..25=0x02 14=1 13..12=2 6..2=0x0C 1..0=3 +vfmul.h rd rs1 rs2 31..30=2 29..25=0x03 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmul.r.h rd rs1 rs2 31..30=2 29..25=0x03 14=1 13..12=2 6..2=0x0C 1..0=3 +vfdiv.h rd rs1 rs2 31..30=2 29..25=0x04 14=0 13..12=2 6..2=0x0C 1..0=3 +vfdiv.r.h rd rs1 rs2 31..30=2 29..25=0x04 14=1 13..12=2 6..2=0x0C 1..0=3 +vfmin.h rd rs1 rs2 31..30=2 29..25=0x05 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmin.r.h rd rs1 rs2 31..30=2 29..25=0x05 14=1 13..12=2 6..2=0x0C 1..0=3 +vfmax.h rd rs1 rs2 31..30=2 29..25=0x06 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmax.r.h rd rs1 rs2 31..30=2 29..25=0x06 14=1 13..12=2 6..2=0x0C 1..0=3 +vfsqrt.h rd rs1 24..20=0 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmac.h rd rs1 rs2 31..30=2 29..25=0x08 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmac.r.h rd rs1 rs2 31..30=2 29..25=0x08 14=1 13..12=2 6..2=0x0C 1..0=3 +vfmre.h rd rs1 rs2 31..30=2 29..25=0x09 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmre.r.h rd rs1 rs2 31..30=2 29..25=0x09 14=1 13..12=2 6..2=0x0C 1..0=3 +vfclass.h rd rs1 24..20=1 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfsgnj.h rd rs1 rs2 31..30=2 29..25=0x0D 14=0 13..12=2 6..2=0x0C 1..0=3 +vfsgnj.r.h rd rs1 rs2 31..30=2 29..25=0x0D 14=1 13..12=2 6..2=0x0C 1..0=3 +vfsgnjn.h rd rs1 rs2 31..30=2 29..25=0x0E 14=0 13..12=2 6..2=0x0C 1..0=3 +vfsgnjn.r.h rd rs1 rs2 31..30=2 29..25=0x0E 14=1 13..12=2 6..2=0x0C 1..0=3 +vfsgnjx.h rd rs1 rs2 31..30=2 29..25=0x0F 14=0 13..12=2 6..2=0x0C 1..0=3 +vfsgnjx.r.h rd rs1 rs2 31..30=2 29..25=0x0F 14=1 13..12=2 6..2=0x0C 1..0=3 +vfeq.h rd rs1 rs2 31..30=2 29..25=0x10 14=0 13..12=2 6..2=0x0C 1..0=3 +vfeq.r.h rd rs1 rs2 31..30=2 29..25=0x10 14=1 13..12=2 6..2=0x0C 1..0=3 +vfne.h rd rs1 rs2 31..30=2 29..25=0x11 14=0 13..12=2 6..2=0x0C 1..0=3 +vfne.r.h rd rs1 rs2 31..30=2 29..25=0x11 14=1 13..12=2 6..2=0x0C 1..0=3 +vflt.h rd rs1 rs2 31..30=2 29..25=0x12 14=0 13..12=2 6..2=0x0C 1..0=3 +vflt.r.h rd rs1 rs2 31..30=2 29..25=0x12 14=1 13..12=2 6..2=0x0C 1..0=3 +vfge.h rd rs1 rs2 31..30=2 29..25=0x13 14=0 13..12=2 6..2=0x0C 1..0=3 +vfge.r.h rd rs1 rs2 31..30=2 29..25=0x13 14=1 13..12=2 6..2=0x0C 1..0=3 +vfle.h rd rs1 rs2 31..30=2 29..25=0x14 14=0 13..12=2 6..2=0x0C 1..0=3 +vfle.r.h rd rs1 rs2 31..30=2 29..25=0x14 14=1 13..12=2 6..2=0x0C 1..0=3 +vfgt.h rd rs1 rs2 31..30=2 29..25=0x15 14=0 13..12=2 6..2=0x0C 1..0=3 +vfgt.r.h rd rs1 rs2 31..30=2 29..25=0x15 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfnothirtytwoD: only unless RV32D +vfmv.x.h rd rs1 24..20=0 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfmv.h.x rd rs1 24..20=0 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +vfcvt.x.h rd rs1 24..20=2 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcvt.xu.h rd rs1 24..20=2 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +vfcvt.h.x rd rs1 24..20=3 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcvt.h.xu rd rs1 24..20=3 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfwithF - vectorial half-precision conversions with F extension, a-d legality depends on FLEN +vfcpka.h.s rd rs1 rs2 31..30=2 29..25=0x18 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcpkb.h.s rd rs1 rs2 31..30=2 29..25=0x18 14=1 13..12=2 6..2=0x0C 1..0=3 +vfcpkc.h.s rd rs1 rs2 31..30=2 29..25=0x19 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcpkd.h.s rd rs1 rs2 31..30=2 29..25=0x19 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfwithD - vectorial half-precision conversions with D extension, a-d legality depends on FLEN (in addition to the above) +vfcpka.h.d rd rs1 rs2 31..30=2 29..25=0x1A 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcpkb.h.d rd rs1 rs2 31..30=2 29..25=0x1A 14=1 13..12=2 6..2=0x0C 1..0=3 +vfcpkc.h.d rd rs1 rs2 31..30=2 29..25=0x1B 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcpkd.h.d rd rs1 rs2 31..30=2 29..25=0x1B 14=1 13..12=2 6..2=0x0C 1..0=3 +# Xfvecalthalfwithsingle - vectorial half-precision conversions with Xfvecsingle extension +vfcvt.s.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcvtu.s.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcvt.h.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcvtu.h.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   █▀█ █▀█ █▄▄ █▀░ + +# Xfvecalthalf - vectorial alternate half-precision floats - requires FLEN >= 32 +# startgroup Xfvecalthalf vectorial alternate half-precision floats - requires FLEN >= 32 +@vfadd.ah rd rs1 rs2 31..30=2 29..25=0x01 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfadd.r.ah rd rs1 rs2 31..30=2 29..25=0x01 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfsub.ah rd rs1 rs2 31..30=2 29..25=0x02 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfsub.r.ah rd rs1 rs2 31..30=2 29..25=0x02 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfmul.ah rd rs1 rs2 31..30=2 29..25=0x03 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmul.r.ah rd rs1 rs2 31..30=2 29..25=0x03 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfdiv.ah rd rs1 rs2 31..30=2 29..25=0x04 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdiv.r.ah rd rs1 rs2 31..30=2 29..25=0x04 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfmin.ah rd rs1 rs2 31..30=2 29..25=0x05 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmin.r.ah rd rs1 rs2 31..30=2 29..25=0x05 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfmax.ah rd rs1 rs2 31..30=2 29..25=0x06 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmax.r.ah rd rs1 rs2 31..30=2 29..25=0x06 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfsqrt.ah rd rs1 24..20=0 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmac.ah rd rs1 rs2 31..30=2 29..25=0x08 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmac.r.ah rd rs1 rs2 31..30=2 29..25=0x08 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfmre.ah rd rs1 rs2 31..30=2 29..25=0x09 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmre.r.ah rd rs1 rs2 31..30=2 29..25=0x09 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfclass.ah rd rs1 24..20=1 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfsgnj.ah rd rs1 rs2 31..30=2 29..25=0x0D 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfsgnj.r.ah rd rs1 rs2 31..30=2 29..25=0x0D 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfsgnjn.ah rd rs1 rs2 31..30=2 29..25=0x0E 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfsgnjn.r.ah rd rs1 rs2 31..30=2 29..25=0x0E 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfsgnjx.ah rd rs1 rs2 31..30=2 29..25=0x0F 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfsgnjx.r.ah rd rs1 rs2 31..30=2 29..25=0x0F 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfeq.ah rd rs1 rs2 31..30=2 29..25=0x10 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfeq.r.ah rd rs1 rs2 31..30=2 29..25=0x10 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfne.ah rd rs1 rs2 31..30=2 29..25=0x11 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfne.r.ah rd rs1 rs2 31..30=2 29..25=0x11 14=1 13..12=2 6..2=0x0C 1..0=3 +@vflt.ah rd rs1 rs2 31..30=2 29..25=0x12 14=0 13..12=2 6..2=0x0C 1..0=3 +@vflt.r.ah rd rs1 rs2 31..30=2 29..25=0x12 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfge.ah rd rs1 rs2 31..30=2 29..25=0x13 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfge.r.ah rd rs1 rs2 31..30=2 29..25=0x13 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfle.ah rd rs1 rs2 31..30=2 29..25=0x14 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfle.r.ah rd rs1 rs2 31..30=2 29..25=0x14 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfgt.ah rd rs1 rs2 31..30=2 29..25=0x15 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfgt.r.ah rd rs1 rs2 31..30=2 29..25=0x15 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfnothirtytwoD: only unless RV32D +@vfmv.x.ah rd rs1 24..20=0 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfmv.ah.x rd rs1 24..20=0 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.x.ah rd rs1 24..20=2 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.xu.ah rd rs1 24..20=2 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.ah.x rd rs1 24..20=3 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.ah.xu rd rs1 24..20=3 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfwithF - vectorial half-precision conversions with F extension, a-d legality depends on FLEN +@vfcpka.ah.s rd rs1 rs2 31..30=2 29..25=0x18 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcpkb.ah.s rd rs1 rs2 31..30=2 29..25=0x18 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcpkc.ah.s rd rs1 rs2 31..30=2 29..25=0x19 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcpkd.ah.s rd rs1 rs2 31..30=2 29..25=0x19 14=1 13..12=2 6..2=0x0C 1..0=3 +# XfvechalfwithD - vectorial half-precision conversions with D extension, a-d legality depends on FLEN (in addition to the above) +@vfcpka.ah.d rd rs1 rs2 31..30=2 29..25=0x1A 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcpkb.ah.d rd rs1 rs2 31..30=2 29..25=0x1A 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcpkc.ah.d rd rs1 rs2 31..30=2 29..25=0x1B 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcpkd.ah.d rd rs1 rs2 31..30=2 29..25=0x1B 14=1 13..12=2 6..2=0x0C 1..0=3 +# Xfvecalthalfwithsingle - vectorial half-precision conversions with Xfvecsingle extension +@vfcvt.s.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfcvtu.s.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +@vfcvt.ah.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.ah.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +# end_group + +# █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfvecquarter - vectorial quarter-precision floats - requires FLEN >= 16 +# startgroup Xfvecquarter vectorial quarter-precision floats - requires FLEN >= 16 +vfadd.b rd rs1 rs2 31..30=2 29..25=0x01 14=0 13..12=3 6..2=0x0C 1..0=3 +vfadd.r.b rd rs1 rs2 31..30=2 29..25=0x01 14=1 13..12=3 6..2=0x0C 1..0=3 +vfsub.b rd rs1 rs2 31..30=2 29..25=0x02 14=0 13..12=3 6..2=0x0C 1..0=3 +vfsub.r.b rd rs1 rs2 31..30=2 29..25=0x02 14=1 13..12=3 6..2=0x0C 1..0=3 +vfmul.b rd rs1 rs2 31..30=2 29..25=0x03 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmul.r.b rd rs1 rs2 31..30=2 29..25=0x03 14=1 13..12=3 6..2=0x0C 1..0=3 +vfdiv.b rd rs1 rs2 31..30=2 29..25=0x04 14=0 13..12=3 6..2=0x0C 1..0=3 +vfdiv.r.b rd rs1 rs2 31..30=2 29..25=0x04 14=1 13..12=3 6..2=0x0C 1..0=3 +vfmin.b rd rs1 rs2 31..30=2 29..25=0x05 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmin.r.b rd rs1 rs2 31..30=2 29..25=0x05 14=1 13..12=3 6..2=0x0C 1..0=3 +vfmax.b rd rs1 rs2 31..30=2 29..25=0x06 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmax.r.b rd rs1 rs2 31..30=2 29..25=0x06 14=1 13..12=3 6..2=0x0C 1..0=3 +vfsqrt.b rd rs1 24..20=0 31..30=2 29..25=0x07 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmac.b rd rs1 rs2 31..30=2 29..25=0x08 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmac.r.b rd rs1 rs2 31..30=2 29..25=0x08 14=1 13..12=3 6..2=0x0C 1..0=3 +vfmre.b rd rs1 rs2 31..30=2 29..25=0x09 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmre.r.b rd rs1 rs2 31..30=2 29..25=0x09 14=1 13..12=3 6..2=0x0C 1..0=3 +vfsgnj.b rd rs1 rs2 31..30=2 29..25=0x0D 14=0 13..12=3 6..2=0x0C 1..0=3 +vfsgnj.r.b rd rs1 rs2 31..30=2 29..25=0x0D 14=1 13..12=3 6..2=0x0C 1..0=3 +vfsgnjn.b rd rs1 rs2 31..30=2 29..25=0x0E 14=0 13..12=3 6..2=0x0C 1..0=3 +vfsgnjn.r.b rd rs1 rs2 31..30=2 29..25=0x0E 14=1 13..12=3 6..2=0x0C 1..0=3 +vfsgnjx.b rd rs1 rs2 31..30=2 29..25=0x0F 14=0 13..12=3 6..2=0x0C 1..0=3 +vfsgnjx.r.b rd rs1 rs2 31..30=2 29..25=0x0F 14=1 13..12=3 6..2=0x0C 1..0=3 +vfeq.b rd rs1 rs2 31..30=2 29..25=0x10 14=0 13..12=3 6..2=0x0C 1..0=3 +vfeq.r.b rd rs1 rs2 31..30=2 29..25=0x10 14=1 13..12=3 6..2=0x0C 1..0=3 +vfne.b rd rs1 rs2 31..30=2 29..25=0x11 14=0 13..12=3 6..2=0x0C 1..0=3 +vfne.r.b rd rs1 rs2 31..30=2 29..25=0x11 14=1 13..12=3 6..2=0x0C 1..0=3 +vflt.b rd rs1 rs2 31..30=2 29..25=0x12 14=0 13..12=3 6..2=0x0C 1..0=3 +vflt.r.b rd rs1 rs2 31..30=2 29..25=0x12 14=1 13..12=3 6..2=0x0C 1..0=3 +vfge.b rd rs1 rs2 31..30=2 29..25=0x13 14=0 13..12=3 6..2=0x0C 1..0=3 +vfge.r.b rd rs1 rs2 31..30=2 29..25=0x13 14=1 13..12=3 6..2=0x0C 1..0=3 +vfle.b rd rs1 rs2 31..30=2 29..25=0x14 14=0 13..12=3 6..2=0x0C 1..0=3 +vfle.r.b rd rs1 rs2 31..30=2 29..25=0x14 14=1 13..12=3 6..2=0x0C 1..0=3 +vfgt.b rd rs1 rs2 31..30=2 29..25=0x15 14=0 13..12=3 6..2=0x0C 1..0=3 +vfgt.r.b rd rs1 rs2 31..30=2 29..25=0x15 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarternothirtytwoD: only unless RV32D +vfmv.x.b rd rs1 24..20=0 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfmv.b.x rd rs1 24..20=0 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +vfclass.b rd rs1 24..20=1 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvt.x.b rd rs1 24..20=2 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvt.xu.b rd rs1 24..20=2 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +vfcvt.b.x rd rs1 24..20=3 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvt.b.xu rd rs1 24..20=3 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarterwithF - vectorial quarter-precision conversions with F extension, a-d legality depends on FLEN +vfcpka.b.s rd rs1 rs2 31..30=2 29..25=0x18 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcpkb.b.s rd rs1 rs2 31..30=2 29..25=0x18 14=1 13..12=3 6..2=0x0C 1..0=3 +vfcpkc.b.s rd rs1 rs2 31..30=2 29..25=0x19 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcpkd.b.s rd rs1 rs2 31..30=2 29..25=0x19 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarterwithD - vectorial quarter-precision conversions with D extension, a-d legality depends on FLEN (in addition to above) +vfcpka.b.d rd rs1 rs2 31..30=2 29..25=0x1A 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcpkb.b.d rd rs1 rs2 31..30=2 29..25=0x1A 14=1 13..12=3 6..2=0x0C 1..0=3 +vfcpkc.b.d rd rs1 rs2 31..30=2 29..25=0x1B 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcpkd.b.d rd rs1 rs2 31..30=2 29..25=0x1B 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithsingle - vectorial quarter-precision conversions with Xfvecsingle extension +vfcvt.s.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +vfcvtu.s.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +vfcvt.b.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvtu.b.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithhalf - vectorial quarter-precision conversions with Xfvechalf extension +vfcvt.h.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +vfcvtu.h.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +vfcvt.b.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvtu.b.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithalthalf - vectorial quarter-precision conversions with Xfvecalthalf extension +@vfcvt.ah.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.ah.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.b.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.b.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithhalf - vectorial quarter-precision conversions with Xfvechalf extension +vfcvt.b.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.ab.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.b.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +vfcvtu.b.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.ab.b rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.b.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# end_group + + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfvecaltquarter - vectorial alternative quarter-precision floats - requires FLEN >= 16 +# startgroup Xfvecaltquarter vectorial alternative quarter-precision floats - requires FLEN >= 16 +@vfadd.ab rd rs1 rs2 31..30=2 29..25=0x01 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfadd.r.ab rd rs1 rs2 31..30=2 29..25=0x01 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfsub.ab rd rs1 rs2 31..30=2 29..25=0x02 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfsub.r.ab rd rs1 rs2 31..30=2 29..25=0x02 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfmul.ab rd rs1 rs2 31..30=2 29..25=0x03 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmul.r.ab rd rs1 rs2 31..30=2 29..25=0x03 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfdiv.ab rd rs1 rs2 31..30=2 29..25=0x04 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfdiv.r.ab rd rs1 rs2 31..30=2 29..25=0x04 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfmin.ab rd rs1 rs2 31..30=2 29..25=0x05 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmin.r.ab rd rs1 rs2 31..30=2 29..25=0x05 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfmax.ab rd rs1 rs2 31..30=2 29..25=0x06 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmax.r.ab rd rs1 rs2 31..30=2 29..25=0x06 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfsqrt.ab rd rs1 24..20=0 31..30=2 29..25=0x07 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmac.ab rd rs1 rs2 31..30=2 29..25=0x08 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmac.r.ab rd rs1 rs2 31..30=2 29..25=0x08 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfmre.ab rd rs1 rs2 31..30=2 29..25=0x09 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmre.r.ab rd rs1 rs2 31..30=2 29..25=0x09 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfsgnj.ab rd rs1 rs2 31..30=2 29..25=0x0D 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfsgnj.r.ab rd rs1 rs2 31..30=2 29..25=0x0D 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfsgnjn.ab rd rs1 rs2 31..30=2 29..25=0x0E 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfsgnjn.r.ab rd rs1 rs2 31..30=2 29..25=0x0E 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfsgnjx.ab rd rs1 rs2 31..30=2 29..25=0x0F 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfsgnjx.r.ab rd rs1 rs2 31..30=2 29..25=0x0F 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfeq.ab rd rs1 rs2 31..30=2 29..25=0x10 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfeq.r.ab rd rs1 rs2 31..30=2 29..25=0x10 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfne.ab rd rs1 rs2 31..30=2 29..25=0x11 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfne.r.ab rd rs1 rs2 31..30=2 29..25=0x11 14=1 13..12=3 6..2=0x0C 1..0=3 +@vflt.ab rd rs1 rs2 31..30=2 29..25=0x12 14=0 13..12=3 6..2=0x0C 1..0=3 +@vflt.r.ab rd rs1 rs2 31..30=2 29..25=0x12 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfge.ab rd rs1 rs2 31..30=2 29..25=0x13 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfge.r.ab rd rs1 rs2 31..30=2 29..25=0x13 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfle.ab rd rs1 rs2 31..30=2 29..25=0x14 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfle.r.ab rd rs1 rs2 31..30=2 29..25=0x14 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfgt.ab rd rs1 rs2 31..30=2 29..25=0x15 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfgt.r.ab rd rs1 rs2 31..30=2 29..25=0x15 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarternothirtytwoD: only unless RV32D +@vfmv.x.ab rd rs1 24..20=0 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfmv.ab.x rd rs1 24..20=0 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfclass.ab rd rs1 24..20=1 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.x.ab rd rs1 24..20=2 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.xu.ab rd rs1 24..20=2 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.ab.x rd rs1 24..20=3 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvt.ab.xu rd rs1 24..20=3 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarterwithF - vectorial quarter-precision conversions with F extension, a-d legality depends on FLEN +@vfcpka.ab.s rd rs1 rs2 31..30=2 29..25=0x18 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcpkb.ab.s rd rs1 rs2 31..30=2 29..25=0x18 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfcpkc.ab.s rd rs1 rs2 31..30=2 29..25=0x19 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcpkd.ab.s rd rs1 rs2 31..30=2 29..25=0x19 14=1 13..12=3 6..2=0x0C 1..0=3 +# XfvecquarterwithD - vectorial quarter-precision conversions with D extension, a-d legality depends on FLEN (in addition to above) +@vfcpka.ab.d rd rs1 rs2 31..30=2 29..25=0x1A 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcpkb.ab.d rd rs1 rs2 31..30=2 29..25=0x1A 14=1 13..12=3 6..2=0x0C 1..0=3 +@vfcpkc.ab.d rd rs1 rs2 31..30=2 29..25=0x1B 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcpkd.ab.d rd rs1 rs2 31..30=2 29..25=0x1B 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithsingle - vectorial quarter-precision conversions with Xfvecsingle extension +@vfcvt.s.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfcvtu.s.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=0 6..2=0x0C 1..0=3 +@vfcvt.ab.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.ab.s rd rs1 24..20=4 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithhalf - vectorial quarter-precision conversions with Xfvechalf extension +@vfcvt.h.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.h.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.ab.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.ab.h rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# Xfvecquarterwithalthalf - vectorial quarter-precision conversions with Xfvecalthalf extension +@vfcvt.ah.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfcvtu.ah.ab rd rs1 24..20=7 31..30=2 29..25=0x0C 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfcvt.ab.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfcvtu.ab.ah rd rs1 24..20=6 31..30=2 29..25=0x0C 14=1 13..12=3 6..2=0x0C 1..0=3 +# end_group + +# ░█████╗░██╗░░░██╗██╗░░██╗██╗██╗░░░░░██╗░█████╗░██████╗░██╗░░░██╗ +# ██╔══██╗██║░░░██║╚██╗██╔╝██║██║░░░░░██║██╔══██╗██╔══██╗╚██╗░██╔╝ +# ███████║██║░░░██║░╚███╔╝░██║██║░░░░░██║███████║██████╔╝░╚████╔╝░ +# ██╔══██║██║░░░██║░██╔██╗░██║██║░░░░░██║██╔══██║██╔══██╗░░╚██╔╝░░ +# ██║░░██║╚██████╔╝██╔╝╚██╗██║███████╗██║██║░░██║██║░░██║░░░██║░░░ +# ╚═╝░░╚═╝░╚═════╝░╚═╝░░╚═╝╚═╝╚══════╝╚═╝╚═╝░░╚═╝╚═╝░░╚═╝░░░╚═╝░░░ + +#SMALLFLOAT AUXILIARY +# collected under Xfaux - naming not final + +# █▀ █ █▄░█ █▀▀ █░░ █▀▀ +# ▄█ █ █░▀█ █▄█ █▄▄ ██▄ + +# Xfauxsingle - single-precision auxiliary operations - requires F extension +# startgroup Xfauxsingle single-precision auxiliary operations - requires F extension +# no instructions currently +# end_group + +# █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▀█ █▄▄ █▀░ + +# Xfauxhalf - half-precision auxiliary operations - requires Xfhalf extension +# startgroup Xfauxhalf half-precision auxiliary operations - requires Xfhalf extension +fmulex.s.h rd rs1 rs2 31..27=0x09 rm 26..25=2 6..2=0x14 1..0=3 +fmacex.s.h rd rs1 rs2 31..27=0x0A rm 26..25=2 6..2=0x14 1..0=3 +# endgroup + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   █▀█ █▀█ █▄▄ █▀░ + +# Xfauxalthalf - alternate half-precision auxiliary operations - requires Xfalthalf extension +# startgroup Xfauxalthalf alternate half-precision auxiliary operations - requires Xfalthalf extension +@fmulex.s.ah rd rs1 rs2 31..27=0x09 rm 26..25=2 6..2=0x14 1..0=3 +@fmacex.s.ah rd rs1 rs2 31..27=0x0A rm 26..25=2 6..2=0x14 1..0=3 +# end_group + +# █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfauxquarter - quarter-precision auxiliary operations - requires Xfquarter extension +# startgroup Xfauxquarter quarter-precision auxiliary operations - requires Xfquarter extension +fmulex.s.b rd rs1 rs2 31..27=0x09 rm 26..25=3 6..2=0x14 1..0=3 +fmacex.s.b rd rs1 rs2 31..27=0x0A rm 26..25=3 6..2=0x14 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfauxaltquarter - alternate quarter-precision auxiliary operations - requires Xfaltquarter extension +# startgroup Xfauxaltquarter alternate quarter-precision auxiliary operations - requires Xfaltquarter extension +@fmulex.s.ab rd rs1 rs2 31..27=0x09 rm 26..25=3 6..2=0x14 1..0=3 +@fmacex.s.ab rd rs1 rs2 31..27=0x0A rm 26..25=3 6..2=0x14 1..0=3 + +# ░█████╗░██╗░░░██╗██╗░░██╗  ██╗░░░██╗███████╗░█████╗░████████╗░█████╗░██████╗░ +# ██╔══██╗██║░░░██║╚██╗██╔╝  ██║░░░██║██╔════╝██╔══██╗╚══██╔══╝██╔══██╗██╔══██╗ +# ███████║██║░░░██║░╚███╔╝░  ╚██╗░██╔╝█████╗░░██║░░╚═╝░░░██║░░░██║░░██║██████╔╝ +# ██╔══██║██║░░░██║░██╔██╗░  ░╚████╔╝░██╔══╝░░██║░░██╗░░░██║░░░██║░░██║██╔══██╗ +# ██║░░██║╚██████╔╝██╔╝╚██╗  ░░╚██╔╝░░███████╗╚█████╔╝░░░██║░░░╚█████╔╝██║░░██║ +# ╚═╝░░╚═╝░╚═════╝░╚═╝░░╚═╝  ░░░╚═╝░░░╚══════╝░╚════╝░░░░╚═╝░░░░╚════╝░╚═╝░░╚═╝ + +# █▀ █ █▄░█ █▀▀ █░░ █▀▀ +# ▄█ █ █░▀█ █▄█ █▄▄ ██▄ + +# Xfauxvecsingle - vectorial single-precision auxiliary operations - requires Xfvecsingle extension +# startgroup Xfauxvecsingle vectorial single-precision auxiliary operations - requires Xfvecsingle extension +vfsum.s rd rs1 24..20=0x1C 31..30=2 29..25=0x07 14=0 13..12=0 6..2=0x0C 1..0=3 +vfnsum.s rd rs1 24..20=0x1C 31..30=2 29..25=0x17 14=0 13..12=0 6..2=0x0C 1..0=3 +#vfdotp.s rd rs1 rs2 31..30=2 29..25=0x0A 14=0 13..12=0 6..2=0x0C 1..0=3 +#vfdotp.r.s rd rs1 rs2 31..30=2 29..25=0x0A 14=1 13..12=0 6..2=0x0C 1..0=3 +#vfavg.s rd rs1 rs2 31..30=2 29..25=0x16 14=0 13..12=0 6..2=0x0C 1..0=3 +#vfavg.r.s rd rs1 rs2 31..30=2 29..25=0x16 14=1 13..12=0 6..2=0x0C 1..0=3 +# end_group + +# █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▀█ █▄▄ █▀░ + +# Xfauxvechalf - vectorial half-precision auxiliary operations - requires Xfvechalf extension +# startgroup Xfauxvechalf vectorial half-precision auxiliary operations - requires Xfvechalf extension +vfsum.h rd rs1 24..20=0x1E 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +vfnsum.h rd rs1 24..20=0x1E 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +#vfdotp.h rd rs1 rs2 31..30=2 29..25=0x0A 14=0 13..12=2 6..2=0x0C 1..0=3 +#vfdotp.r.h rd rs1 rs2 31..30=2 29..25=0x0A 14=1 13..12=2 6..2=0x0C 1..0=3 +#vfavg.h rd rs1 rs2 31..30=2 29..25=0x16 14=0 13..12=2 6..2=0x0C 1..0=3 +#vfavg.r.h rd rs1 rs2 31..30=2 29..25=0x16 14=1 13..12=2 6..2=0x0C 1..0=3 +# endgroup + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   █▀█ █▀█ █▄▄ █▀░ + +# Xfauxvecalthalf - vectorial alternate half-precision auxiliary operations - requires Xfvecalthalf extension +# startgroup Xfauxvecalthalf - vectorial alternate half-precision auxiliary operations - requires Xfvecalthalf extension +@vfsum.ah rd rs1 24..20=0x1E 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfnsum.ah rd rs1 24..20=0x1E 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +#@vfdotp.ah rd rs1 rs2 31..30=2 29..25=0x0A 14=0 13..12=2 6..2=0x0C 1..0=3 +#@vfdotp.r.ah rd rs1 rs2 31..30=2 29..25=0x0A 14=1 13..12=2 6..2=0x0C 1..0=3 +#@vfavg.ah rd rs1 rs2 31..30=2 29..25=0x16 14=0 13..12=2 6..2=0x0C 1..0=3 +#@vfavg.r.ah rd rs1 rs2 31..30=2 29..25=0x16 14=1 13..12=2 6..2=0x0C 1..0=3 +# end_group + +# █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfauxvecquarter & Xfauxvechalf - vectorial quarter-precision auxiliary operations - requires Xfvecquarter extension +# startgroup Xfauxvecquarter vectorial quarter-precision auxiliary operations - requires Xfvecquarter extension +vfsum.b rd rs1 24..20=0x07 31..30=2 29..25=0x07 14=0 13..12=3 6..2=0x0C 1..0=3 +vfnsum.b rd rs1 24..20=0x07 31..30=2 29..25=0x17 14=0 13..12=3 6..2=0x0C 1..0=3 +#vfdotp.b rd rs1 rs2 31..30=2 29..25=0x0A 14=0 13..12=3 6..2=0x0C 1..0=3 +#vfdotp.r.b rd rs1 rs2 31..30=2 29..25=0x0A 14=1 13..12=3 6..2=0x0C 1..0=3 +#vfavg.b rd rs1 rs2 31..30=2 29..25=0x16 14=0 13..12=3 6..2=0x0C 1..0=3 +#vfavg.r.b rd rs1 rs2 31..30=2 29..25=0x16 14=1 13..12=3 6..2=0x0C 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfauxvecaltquarter & Xfauxvechalf - vectorial alternate quarter-precision auxiliary operations - requires Xfvecaltquarter extension +# startgroup Xfauxvecaltquarter - vectorial alternate quarter-precision auxiliary operations - requires Xfvecaltquarter extension +@vfsum.ab rd rs1 24..20=0x07 31..30=2 29..25=0x07 14=0 13..12=3 6..2=0x0C 1..0=3 +@vfnsum.ab rd rs1 24..20=0x07 31..30=2 29..25=0x17 14=0 13..12=3 6..2=0x0C 1..0=3 +#@vfdotp.ab rd rs1 rs2 31..30=2 29..25=0x0A 14=0 13..12=3 6..2=0x0C 1..0=3 +#@vfdotp.r.ab rd rs1 rs2 31..30=2 29..25=0x0A 14=1 13..12=3 6..2=0x0C 1..0=3 +#@vfavg.ab rd rs1 rs2 31..30=2 29..25=0x16 14=0 13..12=3 6..2=0x0C 1..0=3 +#@vfavg.r.ab rd rs1 rs2 31..30=2 29..25=0x16 14=1 13..12=3 6..2=0x0C 1..0=3 +# end_group + +# ██╗░░░██╗███████╗░█████╗░  ███████╗██╗░░██╗██████╗░░█████╗░███╗░░██╗██████╗░██╗███╗░░██╗░██████╗░ +# ██║░░░██║██╔════╝██╔══██╗  ██╔════╝╚██╗██╔╝██╔══██╗██╔══██╗████╗░██║██╔══██╗██║████╗░██║██╔════╝░ +# ╚██╗░██╔╝█████╗░░██║░░╚═╝  █████╗░░░╚███╔╝░██████╔╝███████║██╔██╗██║██║░░██║██║██╔██╗██║██║░░██╗░ +# ░╚████╔╝░██╔══╝░░██║░░██╗  ██╔══╝░░░██╔██╗░██╔═══╝░██╔══██║██║╚████║██║░░██║██║██║╚████║██║░░╚██╗ +# ░░╚██╔╝░░███████╗╚█████╔╝  ███████╗██╔╝╚██╗██║░░░░░██║░░██║██║░╚███║██████╔╝██║██║░╚███║╚██████╔╝ +# ░░░╚═╝░░░╚══════╝░╚════╝░  ╚══════╝╚═╝░░╚═╝╚═╝░░░░░╚═╝░░╚═╝╚═╝░░╚══╝╚═════╝░╚═╝╚═╝░░╚══╝░╚═════╝░ + +# █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▀█ █▄▄ █▀░ + +# Xfexpauxvechalf - vectorial half-precision expanding auxiliary operations - requires Xfvechalf extension +# startgroup Xfexpauxvechalf vectorial half-precision expanding auxiliary operations - requires Xfvechalf extension +vfsumex.s.h rd rs1 24..20=0x16 31..30=2 29..25=0x07 14=0 13..12=0 6..2=0x0C 1..0=3 +vfnsumex.s.h rd rs1 24..20=0x16 31..30=2 29..25=0x17 14=0 13..12=0 6..2=0x0C 1..0=3 +vfdotpex.s.h rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=0 6..2=0x0C 1..0=3 +vfdotpex.s.r.h rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=0 6..2=0x0C 1..0=3 +vfndotpex.s.h rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=0 6..2=0x0C 1..0=3 +vfndotpex.s.r.h rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=0 6..2=0x0C 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █░█ ▄▀█ █░░ █▀▀ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   █▀█ █▀█ █▄▄ █▀░ + +# Xfexpauxvecalthalf - vectorial alternate half-precision expanding auxiliary operations +# startgroup Xfexpauxvecalthalf vectorial alternate half-precision expanding auxiliary operations +@vfsumex.s.ah rd rs1 24..20=0x16 31..30=2 29..25=0x07 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfnsumex.s.ah rd rs1 24..20=0x16 31..30=2 29..25=0x17 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfdotpex.s.ah rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfdotpex.s.r.ah rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=0 6..2=0x0C 1..0=3 +@vfndotpex.s.ah rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=0 6..2=0x0C 1..0=3 +@vfndotpex.s.r.ah rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=0 6..2=0x0C 1..0=3 +# end_group + +# █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfexpauxvecquarter - vectorial quarter-precision expanding auxiliary operations +# startgroup Xfexpauxvecquarter vectorial quarter-precision expanding auxiliary operations +vfsumex.h.b rd rs1 24..20=0x17 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +vfnsumex.h.b rd rs1 24..20=0x17 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +vfdotpex.h.b rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=2 6..2=0x0C 1..0=3 +vfdotpex.h.r.b rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=2 6..2=0x0C 1..0=3 +vfndotpex.h.b rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=2 6..2=0x0C 1..0=3 +vfndotpex.h.r.b rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfsumex.ah.b rd rs1 24..20=0x17 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfnsumex.ah.b rd rs1 24..20=0x17 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.ah.b rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.ah.r.b rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.ah.b rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.ah.r.b rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=2 6..2=0x0C 1..0=3 +# end_group + +# ▄▀█ █░░ ▀█▀ █▀▀ █▀█ █▄░█ ▄▀█ ▀█▀ █▀▀   █▀█ █░█ ▄▀█ █▀█ ▀█▀ █▀▀ █▀█ +# █▀█ █▄▄ ░█░ ██▄ █▀▄ █░▀█ █▀█ ░█░ ██▄   ▀▀█ █▄█ █▀█ █▀▄ ░█░ ██▄ █▀▄ + +# Xfexpauxvecaltquarter - vectorial alternate quarter-precision expanding auxiliary operations +# startgroup Xfexpauxvecaltquarter vectorial alternate quarter-precision expanding auxiliary operations +@vfsumex.h.ab rd rs1 24..20=0x17 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfnsumex.h.ab rd rs1 24..20=0x17 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.h.ab rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.h.r.ab rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.h.ab rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.h.r.ab rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=2 6..2=0x0C 1..0=3 +# Same with alternate half destination +@vfsumex.ah.ab rd rs1 24..20=0x17 31..30=2 29..25=0x07 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfnsumex.ah.ab rd rs1 24..20=0x17 31..30=2 29..25=0x17 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.ah.ab rd rs1 rs2 31..30=2 29..25=0x0B 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfdotpex.ah.r.ab rd rs1 rs2 31..30=2 29..25=0x0B 14=1 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.ah.ab rd rs1 rs2 31..30=2 29..25=0x1D 14=0 13..12=2 6..2=0x0C 1..0=3 +@vfndotpex.ah.r.ab rd rs1 rs2 31..30=2 29..25=0x1D 14=1 13..12=2 6..2=0x0C 1..0=3 +# endgroup diff --git a/opcodes-ipu b/opcodes-ipu new file mode 100644 index 00000000..5bc1d16b --- /dev/null +++ b/opcodes-ipu @@ -0,0 +1,97 @@ +imv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x16 1..0=3 +imv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x16 1..0=3 + +iaddi rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3 +islli rd rs1 31..26=0 shamt 14..12=1 6..2=0x1E 1..0=3 +islti rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3 +isltiu rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3 +ixori rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3 +isrli rd rs1 31..26=0 shamt 14..12=5 6..2=0x1E 1..0=3 +israi rd rs1 31..26=16 shamt 14..12=5 6..2=0x1E 1..0=3 +iori rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3 +iandi rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3 + +iadd rd rs1 rs2 31..25=0 14..12=0 6..2=0x16 1..0=3 +isub rd rs1 rs2 31..25=32 14..12=0 6..2=0x16 1..0=3 +isll rd rs1 rs2 31..25=0 14..12=1 6..2=0x16 1..0=3 +islt rd rs1 rs2 31..25=0 14..12=2 6..2=0x16 1..0=3 +isltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x16 1..0=3 +ixor rd rs1 rs2 31..25=0 14..12=4 6..2=0x16 1..0=3 +isrl rd rs1 rs2 31..25=0 14..12=5 6..2=0x16 1..0=3 +isra rd rs1 rs2 31..25=32 14..12=5 6..2=0x16 1..0=3 +ior rd rs1 rs2 31..25=0 14..12=6 6..2=0x16 1..0=3 +iand rd rs1 rs2 31..25=0 14..12=7 6..2=0x16 1..0=3 + +imadd rd rs1 rs2 rs3 26..25=1 14..12=0 6..2=0x16 1..0=3 +imsub rd rs1 rs2 rs3 26..25=1 14..12=1 6..2=0x16 1..0=3 +inmsub rd rs1 rs2 rs3 26..25=1 14..12=2 6..2=0x16 1..0=3 +inmadd rd rs1 rs2 rs3 26..25=1 14..12=3 6..2=0x16 1..0=3 + +imul rd rs1 rs2 31..25=2 14..12=0 6..2=0x16 1..0=3 +imulh rd rs1 rs2 31..25=2 14..12=1 6..2=0x16 1..0=3 +imulhsu rd rs1 rs2 31..25=2 14..12=2 6..2=0x16 1..0=3 +imulhu rd rs1 rs2 31..25=2 14..12=3 6..2=0x16 1..0=3 + +iandn rd rs1 rs2 31..25=32 14..12=7 6..2=0x16 1..0=3 +iorn rd rs1 rs2 31..25=32 14..12=6 6..2=0x16 1..0=3 +ixnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x16 1..0=3 + +islo rd rs1 rs2 31..25=16 14..12=1 6..2=0x16 1..0=3 +isro rd rs1 rs2 31..25=16 14..12=5 6..2=0x16 1..0=3 +irol rd rs1 rs2 31..25=48 14..12=1 6..2=0x16 1..0=3 +iror rd rs1 rs2 31..25=48 14..12=5 6..2=0x16 1..0=3 + +isbclr rd rs1 rs2 31..25=36 14..12=1 6..2=0x16 1..0=3 +isbset rd rs1 rs2 31..25=20 14..12=1 6..2=0x16 1..0=3 +isbinv rd rs1 rs2 31..25=52 14..12=1 6..2=0x16 1..0=3 +isbext rd rs1 rs2 31..25=36 14..12=5 6..2=0x16 1..0=3 +igorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x16 1..0=3 +igrev rd rs1 rs2 31..25=52 14..12=5 6..2=0x16 1..0=3 + +isloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x1E 1..0=3 +isroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x1E 1..0=3 +irori rd rs1 31..26=24 shamt 14..12=5 6..2=0x1E 1..0=3 + +isbclri rd rs1 31..26=18 shamt 14..12=1 6..2=0x1E 1..0=3 +isbseti rd rs1 31..26=10 shamt 14..12=1 6..2=0x1E 1..0=3 +isbinvi rd rs1 31..26=26 shamt 14..12=1 6..2=0x1E 1..0=3 +isbexti rd rs1 31..26=18 shamt 14..12=5 6..2=0x1E 1..0=3 +igorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x1E 1..0=3 +igrevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x1E 1..0=3 + +iclz rd rs1 31..20=0x600 14..12=2 6..2=0x16 1..0=3 +ictz rd rs1 31..20=0x601 14..12=2 6..2=0x16 1..0=3 +ipcnt rd rs1 31..20=0x602 14..12=2 6..2=0x16 1..0=3 +isext.b rd rs1 31..20=0x604 14..12=2 6..2=0x16 1..0=3 +isext.h rd rs1 31..20=0x605 14..12=2 6..2=0x16 1..0=3 + +icrc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x16 1..0=3 +icrc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x16 1..0=3 +icrc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x16 1..0=3 +icrc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x16 1..0=3 +icrc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x16 1..0=3 +icrc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x16 1..0=3 + +ish1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x16 1..0=3 +ish2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x16 1..0=3 +ish3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x16 1..0=3 + +iclmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x16 1..0=3 +iclmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x16 1..0=3 +iclmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x16 1..0=3 +imin rd rs1 rs2 31..25=5 14..12=4 6..2=0x16 1..0=3 +imax rd rs1 rs2 31..25=5 14..12=5 6..2=0x16 1..0=3 +iminu rd rs1 rs2 31..25=5 14..12=6 6..2=0x16 1..0=3 +imaxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x16 1..0=3 + +ishfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x16 1..0=3 +iunshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x16 1..0=3 +ibext rd rs1 rs2 31..25=4 14..12=6 6..2=0x16 1..0=3 +ibdep rd rs1 rs2 31..25=36 14..12=6 6..2=0x16 1..0=3 +ipack rd rs1 rs2 31..25=4 14..12=4 6..2=0x16 1..0=3 +ipacku rd rs1 rs2 31..25=36 14..12=4 6..2=0x16 1..0=3 +ipackh rd rs1 rs2 31..25=4 14..12=7 6..2=0x16 1..0=3 +ibfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x16 1..0=3 + +ishfli rd rs1 31..25=4 shamtw 14..12=1 6..2=0x1E 1..0=3 +iunshfli rd rs1 31..25=4 shamtw 14..12=5 6..2=0x1E 1..0=3 diff --git a/opcodes-rep b/opcodes-rep new file mode 100644 index 00000000..847e6f6e --- /dev/null +++ b/opcodes-rep @@ -0,0 +1,3 @@ +frep.o rs1 imm12 stagger_max stagger_mask 7=1 6..2=0x02 1..0=3 +frep.i rs1 imm12 stagger_max stagger_mask 7=0 6..2=0x02 1..0=3 +irep rd rs1 imm12 rm 6..2=0x0F 1..0=3 diff --git a/opcodes-rv32b_CUSTOM b/opcodes-rv32b_CUSTOM new file mode 100644 index 00000000..00d610c9 --- /dev/null +++ b/opcodes-rv32b_CUSTOM @@ -0,0 +1,71 @@ +# RV32B +andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 +orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 +xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 + +slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 +sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 +rol rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3 +ror rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3 + +sbclr rd rs1 rs2 31..25=36 14..12=1 6..2=0x0C 1..0=3 +sbset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 +sbinv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 +sbext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 +gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 +grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 + +sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 +sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 +rori rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3 + +sbclri rd rs1 31..26=18 shamt 14..12=1 6..2=0x04 1..0=3 +sbseti rd rs1 31..26=10 shamt 14..12=1 6..2=0x04 1..0=3 +sbinvi rd rs1 31..26=26 shamt 14..12=1 6..2=0x04 1..0=3 +sbexti rd rs1 31..26=18 shamt 14..12=5 6..2=0x04 1..0=3 +gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 +grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 + +cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 +cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 + +fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 +fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 +fsri rd rs1 shamt rs3 26=1 14..12=5 6..2=0x04 1..0=3 + +clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 +ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 +pcnt rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 +sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 +sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 + +crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 +crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 +crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 +crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 +crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 +crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 + +sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 +sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 +sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 + +clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 +clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 +clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 +min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 +max rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 +minu rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 +maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 + +shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 +unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 +bext rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 +bdep rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 +pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 +packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 +packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 +bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 + +shfli rd rs1 31..25=4 shamtw 14..12=1 6..2=0x04 1..0=3 +unshfli rd rs1 31..25=4 shamtw 14..12=5 6..2=0x04 1..0=3 \ No newline at end of file diff --git a/opcodes_sflt_CUSTOM b/opcodes-sflt_CUSTOM similarity index 100% rename from opcodes_sflt_CUSTOM rename to opcodes-sflt_CUSTOM diff --git a/opcodes-ssr b/opcodes-ssr new file mode 100644 index 00000000..b796ca14 --- /dev/null +++ b/opcodes-ssr @@ -0,0 +1,4 @@ +scfgri rd imm12 19..15=0 14..12=1 6..2=0x0A 1..0=0x3 +scfgwi rs1 imm12 11..7=0 14..12=2 6..2=0x0A 1..0=0x3 +scfgr rd rs2 31..25=0 19..15=1 14..12=1 6..2=0x0A 1..0=0x3 +scfgw rs1 rs2 31..25=0 11..7=1 14..12=2 6..2=0x0A 1..0=0x3 diff --git a/opcodes-xpulpabs_CUSTOM b/opcodes-xpulpabs_CUSTOM new file mode 100644 index 00000000..6f7351f6 --- /dev/null +++ b/opcodes-xpulpabs_CUSTOM @@ -0,0 +1,10 @@ +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, +# shamtw, shamt, rm + +p.abs rd rs1 31..25=2 24..20=0 14..12=0 6..2=0x0C 1..0=3 \ No newline at end of file diff --git a/opcodes-xpulpminmax_CUSTOM b/opcodes-xpulpminmax_CUSTOM index 8185540e..061e6e7f 100644 --- a/opcodes-xpulpminmax_CUSTOM +++ b/opcodes-xpulpminmax_CUSTOM @@ -12,5 +12,5 @@ p.minu rd rs1 rs2 31..25=2 14..12=5 6..2=0x0C 1..0=3 p.max rd rs1 rs2 31..25=2 14..12=6 6..2=0x0C 1..0=3 p.maxu rd rs1 rs2 31..25=2 14..12=7 6..2=0x0C 1..0=3 # might be missing p.avg, p.avgu respectively p.addN, p.adduN -p.addN rd rs1 rs2 31..30=0 Luimm5 14..12=2 6..=0x16 1..0=3 -p.adduN rd rs1 rs2 31..30=2 Luimm5 14..12=2 6..=0x16 1..0=3 \ No newline at end of file +p.addN rd rs1 rs2 31..30=0 Luimm5 14..12=2 6..2=0x16 1..0=3 +p.adduN rd rs1 rs2 31..30=2 Luimm5 14..12=2 6..2=0x16 1..0=3 \ No newline at end of file diff --git a/opcodes-xpulpvectshufflepack_CUSTOM b/opcodes-xpulpvectshufflepack_CUSTOM index 1fd0b32a..2acc1e41 100644 --- a/opcodes-xpulpvectshufflepack_CUSTOM +++ b/opcodes-xpulpvectshufflepack_CUSTOM @@ -14,8 +14,8 @@ pv.shufflei0.sci.b rd rs1 imm6 31..27=24 26=0 14..12=7 6..2=0x15 1..0=3 pv.shufflei1.sci.b rd rs1 imm6 31..27=29 26=0 14..12=7 6..2=0x15 1..0=3 pv.shufflei2.sci.b rd rs1 imm6 31..27=30 26=0 14..12=7 6..2=0x15 1..0=3 pv.shufflei3.sci.b rd rs1 imm6 31..27=31 26=0 14..12=7 6..2=0x15 1..0=3 -pv.shuffle.h rd rs1 rs2 31..27=24 26=0 25=0 14..12=0 6..2=0x15 1..0=3 -pv.shuffle.b rd rs1 rs2 31..27=24 26=0 25=0 14..12=1 6..2=0x15 1..0=3 +pv.shuffle2.h rd rs1 rs2 31..27=25 26=0 25=0 14..12=0 6..2=0x15 1..0=3 +pv.shuffle2.b rd rs1 rs2 31..27=25 26=0 25=0 14..12=1 6..2=0x15 1..0=3 pv.pack rd rs1 rs2 31..27=26 26=0 25=0 14..12=0 6..2=0x15 1..0=3 pv.pack.h rd rs1 rs2 31..27=26 26=0 25=1 14..12=0 6..2=0x15 1..0=3 pv.packhi.b rd rs1 rs2 31..27=27 26=0 25=0 14..12=1 6..2=0x15 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index e359f7d9..da662928 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -56,6 +56,29 @@ arglut['nf'] = (31,29) arglut['simm5'] = (19,15) arglut['zimm11'] = (30,20) +# for snitch +arglut['vseglen'] = (31,29) +arglut['stagger_max'] = (14,12) +arglut['stagger_mask'] = (11,8) + +bits_imm12 = [ + ("imm12lo", 4, 0, 0), # imm12lo[4:0] -> imm[4:0] + ("imm12hi", 6, 0, 5), # imm12hi[6:0] -> imm[11:5] +] + +bits_bimm12 = [ + ("bimm12lo", 0, 0, 11), # bimm12lo[0] -> imm[11] + ("bimm12lo", 4, 1, 1), # bimm12lo[4:1] -> imm[4:1] + ("bimm12hi", 5, 0, 5), # bimm12hi[5:0] -> imm[10:5] + ("bimm12hi", 6, 6, 12), # bimm12hi[6] -> imm[12] +] + +bits_jimm20 = [ + ("jimm20", 7, 0, 12), # jimm20[7:0] -> imm[19:12] + ("jimm20", 8, 8, 11), # jimm20[8] -> imm[11] + ("jimm20", 18, 9, 1), # jimm20[18:9] -> imm[10:1] + ("jimm20", 19, 19, 20), # jimm20[19] -> imm[20] +] causes = [ (0x00, 'misaligned fetch'), @@ -96,6 +119,9 @@ csrs = [ (0x042, 'ucause'), (0x043, 'utval'), (0x044, 'uip'), + + # Custom User R/W + (0x800, 'fmode'), # Standard User RO (0xC00, 'cycle'), @@ -302,6 +328,10 @@ csrs = [ (0xF12, 'marchid'), (0xF13, 'mimpid'), (0xF14, 'mhartid'), + + # Custom CSR + (0x7C0, 'ssr'), + (0x7C1, 'fpmode'), ] csrs32 = [ @@ -416,6 +446,251 @@ def make_c(match,mask): print('DECLARE_CAUSE("%s", CAUSE_%s)' % (name, name.upper().replace(' ', '_'))) print('#endif') + +def make_sv(match,mask): + print('// Automatically generated by parse-opcodes (pulp-fork).') + print('package riscv_defines;') + for name in namelist: + sv_insn_mask = "" + for i in range(32): + if (mask[name] & (1 << i)) != 0: + match_bit = (match[name] >> i) & 1; + sv_insn_mask = str(match_bit) + sv_insn_mask + else: + sv_insn_mask = '?' + sv_insn_mask + + name2 = name.upper().replace('.','_') + print('parameter MATCH_%s = 32\'h%x;' % (name2, (match[name]))) + print('parameter MASK_%s = 32\'h%x;' % (name2, (mask[name]))) + print('parameter SV_%s = 32\'b%s;' % (name2, sv_insn_mask)) + for num, name in csrs+csrs32: + print('parameter CSR_%s = 32\'h%x;' % (name.upper(), (num))) + for num, name in causes: + print('parameter CAUSE_%s = 5\'h%x;' % (name.upper().replace(' ', '_'), (num))) + print('endpackage') + + +def make_camel_case(name): + return "".join([name.capitalize() for name in name.split('.')]) + +def make_camel_case_arg(arg): + return make_camel_case(".".join(".".join(arg).split('_')) or "Unit") + +def make_func_case_arg(arg): + return "_".join((a.lower() for a in arg)) or "unit" + +def make_rust_field_shuffle(recipe, sign_extend_to=None): + ops = list() + for (field, hi, lo, dst) in recipe: + ops.append("((self.{} >> {}) & 0x{:x}) << {}".format( + field, + lo, + (1 << (hi-lo+1)) - 1, + dst + )) + ops = " | ".join(ops) + if sign_extend_to is not None: + ops = "((({0}) << {1}) as i32) >> {1}".format(ops, 32 - sign_extend_to) + return ops + +def make_rust(): + print("// Automatically generated by parse-opcodes.") + print() + + # Group instructions based on their mask. + insts_by_mask = dict() + for name, m in mask.items(): + if not pseudos.get(name): + insts_by_mask.setdefault(m, []).append(name) + distinct_masks = list(sorted(insts_by_mask.keys())) + + # Group instructions based on their arguments. + insts_by_args = dict() + for name, arg in arguments.items(): + if not pseudos.get(name): + insts_by_args.setdefault(tuple(sorted(arg)), []).append(name) + distinct_args = list(sorted(insts_by_args.keys())) + + # Emit the argument formats. + print("/// The different instruction formats.") + print("#[derive(Debug, Copy, Clone)]") + print("pub enum Format {") + print(" Illegal(u32),") + for a in distinct_args: + print(" {0}(Format{0}),".format(make_camel_case_arg(a))) + print("}") + print() + print("impl Format {") + print(" pub fn raw(&self) -> u32 {") + print(" match self {") + print(" Self::Illegal(x) => *x,") + for a in distinct_args: + print(" Self::{}(x) => x.raw,".format(make_camel_case_arg(a))) + print(" }") + print(" }") + print("}") + print() + print("impl std::fmt::Display for Format {") + print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {") + print(" match self {") + print(" Self::Illegal(x) => write!(f, \"\", x),") + for a in distinct_args: + print(" Self::{}(x) => write!(f, \"{{}}\", x),".format(make_camel_case_arg(a))) + print(" }") + print(" }") + print("}") + print() + + # Emit the per-format opcodes. + for a in distinct_args: + name = make_camel_case_arg(a) + print("/// The `{}` instruction format.".format(name)) + print("#[derive(Debug, Copy, Clone)]") + print("pub struct Format{} {{".format(name)) + args = ["pub op: Opcode{}".format(name), "pub raw: u32"] + ["pub {}: u32".format(n.lower()) for n in a] + args = "\n ".join(("{},".format(n) for n in args)) + print(" {}".format(args)) + print("}") + print() + print("impl Format{} {{".format(name)) + if "imm12" in a: + print(" pub fn imm(&self) -> i32 {") + print(" ((self.imm12 << 20) as i32) >> 20"); + print(" }") + if "imm12hi" in a and "imm12lo" in a: + print(" pub fn imm(&self) -> i32 {") + print(" {}".format(make_rust_field_shuffle(bits_imm12, 12))); + print(" }") + if "bimm12hi" in a and "bimm12lo" in a: + print(" pub fn bimm(&self) -> i32 {") + print(" {}".format(make_rust_field_shuffle(bits_bimm12, 13))); + print(" }") + if "jimm20" in a: + print(" pub fn jimm(&self) -> i32 {") + print(" {}".format(make_rust_field_shuffle(bits_jimm20, 21))); + print(" }") + print("}") + print() + print("/// Opcodes with the `{}` instruction format.".format(name)) + print("#[derive(Debug, Copy, Clone)]") + print("pub enum Opcode{} {{".format(name)) + for op in insts_by_args[a]: + print(" {},".format(make_camel_case(op))) + print("}") + print() + print("impl std::fmt::Display for Format{} {{".format(name)) + print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {") + print(" write!(f, \"{}\", self.op)?;") + for arg in a: + print(" write!(f, \" {}={{:x}}\", self.{})?;".format(arg, arg.lower())) + print(" Ok(())") + print(" }") + print("}") + print() + print("impl std::fmt::Display for Opcode{} {{".format(name)) + print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {") + print(" match self {") + for n in insts_by_args[a]: + print(" Self::{} => write!(f, \"{}\"),".format(make_camel_case(n), n)) + print(" }") + print(" }") + print("}") + print("") + + # Emit the parse function. + print("/// Parse a `u32` into an instruction.") + print("pub fn parse_u32(raw: u32) -> Format {") + for m in distinct_masks: + print(" match raw & 0x{:x} {{".format(m)) + for n in insts_by_mask[m]: + a = tuple(sorted(arguments[n])) + print(" 0x{:x} => return parse_{}(Opcode{}::{}, raw),".format( + match[n], + make_func_case_arg(a), + make_camel_case_arg(a), + make_camel_case(n) + )) + print(" _ => (),") + print(" }") + print(" Format::Illegal(raw)") + print("}") + print() + print("/// Parse the first bytes of a `&[u8]` slice into an instruction.") + print("pub fn parse(mut raw: &[u8]) -> Format {") + print(" use byteorder::{LittleEndian, ReadBytesExt};") + print(" raw.read_u32::().map(parse_u32).unwrap_or(Format::Illegal(0))") + print("}") + print() + for a in distinct_args: + name = make_camel_case_arg(a) + func_name = make_func_case_arg(a) + print("/// Parse an instruction with the `{}` format.".format(name)) + print("pub fn parse_{}(op: Opcode{}, raw: u32) -> Format {{".format(func_name, name)) + print(" Format::{}(Format{} {{".format(name, name)) + print(" op,") + print(" raw,") + for arg in a: + lo = arglut[arg][1] + hi = arglut[arg][0] + print(" {}: (raw >> {}) & 0x{:x},".format(arg.lower(), lo, (1<<(hi-lo+1))-1)) + print(" })") + print("}") + print() + + # Emit function to get instruction string. + print("/// Decode instruction into string.") + print("pub fn inst_to_string(raw: Format) -> String {") + print(" match raw {") + for a in distinct_args: + print(" Format::{0}(x) => x.op.to_string(),".format(make_camel_case_arg(a))) + print(" _ => \"Unsupported instruction format\".to_string(),") + print(" }") + print("}") + + # Emit configuration. + print("/// Struct to store the latency of each instruction.") + print("#[derive(Debug, serde::Serialize, serde::Deserialize)]") + print("pub struct Latency {") + for a in distinct_args: + print(" // Format::{0}".format(make_camel_case_arg(a))) + for n in insts_by_args[a]: + print(" {}: u8,".format("_".join(n.split('.')))) + print("}") + print() + + # Create a default configuration. + print("/// Struct to store the latency of each instruction.") + print("impl Default for Latency {") + print(" fn default() -> Latency {") + print(" Latency {") + for a in distinct_args: + for n in insts_by_args[a]: + print(" {}: 1,".format("_".join(n.split('.')))) + print(" }") + print(" }") + print("}") + + # Emit CSR enum + print("/// CSR") + print("#[derive(Debug, Copy, Clone)]") + print("#[repr(C)]") + print("pub enum Csr {") + for csr in csrs+csrs32: + print(f' {make_camel_case(csr[1])} = 0x{csr[0]:03x},') + print("}") + + +def make_py(match,mask): + print('# Automatically generated by parse-opcodes.') + for name in namelist: + name2 = name.upper().replace('.', '_') + print('MATCH_%s = %s' % (name2, hex(match[name]))) + print('MASK_%s = %s' % (name2, hex(mask[name]))) + for num, name in csrs+csrs32: + print('CSR_%s = %s' % (name.upper(), hex(num))) + for num, name in causes: + print('CAUSE_%s = %s' % (name.upper().replace(' ', '_'), hex(num))) + def yank(num,start,len): return (num >> start) & ((1 << len) - 1) @@ -1117,9 +1392,15 @@ if __name__ == "__main__": make_chisel() elif sys.argv[1] == '-sverilog': make_sverilog() + elif sys.argv[1] == '-rust': + make_rust() elif sys.argv[1] == '-c': make_c(match,mask) + elif sys.argv[1] == '-sv': + make_sv(match,mask) elif sys.argv[1] == '-go': make_go() + elif sys.argv[1] == '-py': + make_py(match,mask) else: assert 0