.gitlab-ci.yml

# Copyright 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

variables:
  GIT_STRATEGY: clone
  GIT_SUBMODULE_STRATEGY: recursive
  PYTHON: /usr/local/anaconda3-2022.05/bin/python3
  BENDER: bender-0.27.1
  CLANG_FORMAT: clang-format-10.0.1
  CC: gcc-9.2.0
  CXX: g++-9.2.0
  VCS: vcs-2020.12
  VERILATOR: verilator-4.110
  QUESTA: questa-2022.3
  LLVM_BINROOT: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin
  CLANG: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang
  RISCV_GCC_VERSION: 8.3.0-2020.04.0

before_script:
  # yamllint disable rule:line-length
  - $PYTHON -m venv .venv
  - source .venv/bin/activate
  - bender update
  - pip install -r python-requirements.txt
  # Install CVA6 compiler toolchain
  - curl -Ls -o riscv-gcc.tar.gz https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-$RISCV_GCC_VERSION-x86_64-linux-ubuntu14.tar.gz
  - mkdir -p .tools/riscv && chmod 777 .tools/riscv
  - tar -C .tools/riscv -xf riscv-gcc.tar.gz --strip-components=1
  - export PATH="$(pwd)/.tools/riscv/bin:$PATH"
  # Install verible
  - mkdir -p .tools/verible && chmod 777 .tools/verible
  - curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3222-gb19cdf44/verible-v0.0-3222-gb19cdf44-CentOS-7.9.2009-Core-x86_64.tar.gz | tar xz -C .tools/verible --strip-components=1
  - export PATH="$(pwd)/.tools/verible/bin:$PATH"
  # yamllint enable rule:line-length

##############
# Build docs #
##############

docs:
  script:
    - mkdocs build

###############################
# Single-cluster Occamy tests #
###############################

# Questa
occamy-single-cluster-vsim:
  script:
    - cd target/sim
    - make CFG_OVERRIDE=cfg/single-cluster.hjson rtl
    - make sw
    - $QUESTA make bin/occamy_top.vsim
    - $QUESTA ../../deps/snitch_cluster/util/sim/simulate.py
        sw/run-single-cluster.yaml --simulator vsim
        --sim-bin bin/occamy_top.vsim

#####################
# Full Occamy tests #
#####################

# Questa
occamy-full-vsim:
  script:
    - cd target/sim
    - make CFG_OVERRIDE=cfg/full.hjson rtl
    - make LENGTH=384 sw
    - $QUESTA make bin/occamy_top.vsim
    - $QUESTA ../../deps/snitch_cluster/util/sim/simulate.py
        sw/run-full-occamy.yaml --simulator vsim
        --sim-bin bin/occamy_top.vsim