diff --git a/src/backend/src/idma_backend.sv.tpl b/src/backend/src/idma_backend.sv.tpl index 6eae0743..5f2e52a1 100644 --- a/src/backend/src/idma_backend.sv.tpl +++ b/src/backend/src/idma_backend.sv.tpl @@ -40,25 +40,25 @@ module idma_backend${name_uniqueifier} #( 0, %endif /// Mask invalid data on the manager interface - parameter bit MaskInvalidData = 1'b1, + parameter bit MaskInvalidData = 1'b1, /// Should hardware legalization be present? (recommended) /// If not, software legalization is required to ensure the transfers are /// AXI4-conformal - parameter bit HardwareLegalizer = 1'b1, + parameter bit HardwareLegalizer = 1'b1, /// Reject zero-length transfers - parameter bit RejectZeroTransfers = 1'b1, + parameter bit RejectZeroTransfers = 1'b1, /// Should the error handler be present? parameter idma_pkg::error_cap_e ErrorCap = idma_pkg::NO_ERROR_HANDLING, /// Print the info of the FIFO configuration - parameter bit PrintFifoInfo = 1'b0, + parameter bit PrintFifoInfo = 1'b0, /// 1D iDMA request type - parameter type idma_req_t = logic, + parameter type idma_req_t = logic, /// iDMA response type - parameter type idma_rsp_t = logic, + parameter type idma_rsp_t = logic, /// Error Handler request type - parameter type idma_eh_req_t = logic, + parameter type idma_eh_req_t = logic, /// iDMA busy signal - parameter type idma_busy_t = logic\ + parameter type idma_busy_t = logic\ % for protocol in used_protocols: , /// ${database[protocol]['full_name']} Request and Response channel type @@ -85,11 +85,11 @@ module idma_backend${name_uniqueifier} #( /// Address Write Channel type parameter type write_meta_channel_t = logic, /// Address Read Channel type - parameter type read_meta_channel_t = logic, + parameter type read_meta_channel_t = logic, /// Strobe Width (do not override!) - parameter int unsigned StrbWidth = DataWidth / 8, + parameter int unsigned StrbWidth = DataWidth / 8, /// Offset Width (do not override!) - parameter int unsigned OffsetWidth = $clog2(StrbWidth) + parameter int unsigned OffsetWidth = $clog2(StrbWidth) )( /// Clock input logic clk_i, @@ -278,10 +278,10 @@ _rsp_t ${protocol}_write_rsp_i, /// The mutable transfer type holds important information that is mutated by the /// `legalizer` block. typedef struct packed { - tf_len_t length; - addr_t addr; - logic valid; - addr_t base_addr; + tf_len_t length; + addr_t addr; + logic valid; + addr_t base_addr; } idma_mut_tf_t; @@ -312,7 +312,7 @@ _rsp_t ${protocol}_write_rsp_i, logic w_super_last; // Datapath FIFO signals -> used to decouple legalizer and datapath - logic r_dp_req_in_ready , w_dp_req_in_ready; + logic r_dp_req_in_ready, w_dp_req_in_ready; logic r_dp_req_out_valid, w_dp_req_out_valid; logic r_dp_req_out_ready, w_dp_req_out_ready; r_dp_req_t r_dp_req_out; @@ -325,8 +325,8 @@ _rsp_t ${protocol}_write_rsp_i, logic r_dp_rsp_ready, w_dp_rsp_ready; // Ax handshaking - logic ar_ready, ar_ready_dp; - logic aw_ready, aw_ready_dp; + logic ar_ready, ar_ready_dp; + logic aw_ready, aw_ready_dp; logic aw_valid_dp, ar_valid_dp; // Ax request from R-AW coupler to datapath @@ -402,30 +402,30 @@ _rsp_t ${protocol}_write_rsp_i, if (HardwareLegalizer) begin : gen_hw_legalizer // hardware legalizer is present idma_legalizer${name_uniqueifier} #( - .CombinedShifter ( CombinedShifter ), - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .idma_req_t ( idma_req_t ), - .idma_r_req_t ( idma_r_req_t ), - .idma_w_req_t ( idma_w_req_t ), - .idma_mut_tf_t ( idma_mut_tf_t ), - .idma_mut_tf_opt_t ( idma_mut_tf_opt_t ) + .CombinedShifter ( CombinedShifter ), + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .idma_req_t ( idma_req_t ), + .idma_r_req_t ( idma_r_req_t ), + .idma_w_req_t ( idma_w_req_t ), + .idma_mut_tf_t ( idma_mut_tf_t ), + .idma_mut_tf_opt_t ( idma_mut_tf_opt_t ) ) i_idma_legalizer ( - .clk_i, - .rst_ni, - .req_i ( idma_req_i ), - .valid_i ( req_valid ), - .ready_o ( req_ready_o ), - .r_req_o ( r_req ), - .w_req_o ( w_req ), - .r_valid_o ( r_valid ), - .w_valid_o ( w_valid ), - .r_ready_i ( r_ready ), - .w_ready_i ( w_ready ), - .flush_i ( legalizer_flush ), - .kill_i ( legalizer_kill ), - .r_busy_o ( busy_o.r_leg_busy ), - .w_busy_o ( busy_o.w_leg_busy ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( idma_req_i ), + .valid_i ( req_valid ), + .ready_o ( req_ready_o ), + .r_req_o ( r_req ), + .w_req_o ( w_req ), + .r_valid_o ( r_valid ), + .w_valid_o ( w_valid ), + .r_ready_i ( r_ready ), + .w_ready_i ( w_ready ), + .flush_i ( legalizer_flush ), + .kill_i ( legalizer_kill ), + .r_busy_o ( busy_o.r_leg_busy ), + .w_busy_o ( busy_o.w_leg_busy ) ); end else begin : gen_no_hw_legalizer @@ -434,8 +434,8 @@ _rsp_t ${protocol}_write_rsp_i, stream_fork #( .N_OUP ( 32'd2 ) ) i_stream_fork ( - .clk_i, - .rst_ni, + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .valid_i ( req_valid ), .ready_o ( req_ready_o ), .valid_o ( { r_valid, w_valid } ), @@ -447,68 +447,6 @@ _rsp_t ${protocol}_write_rsp_i, assign len = ((idma_req_i.length + idma_req_i.src_addr[OffsetWidth-1:0] - 'd1) >> OffsetWidth); - - // if (Protocol1 == idma_pkg::AXI) begin : gen_axi_ar_req - // // assemble AR request - // assign r_req.ar_req = '{ - // id: idma_req_i.opt.axi_id, - // addr: { idma_req_i.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // len: len, - // size: axi_pkg::size_t'(OffsetWidth), - // burst: idma_req_i.opt.src.burst, - // lock: idma_req_i.opt.src.lock, - // cache: idma_req_i.opt.src.cache, - // prot: idma_req_i.opt.src.prot, - // qos: idma_req_i.opt.src.qos, - // region: idma_req_i.opt.src.region, - // user: '0 - // }; - // end else if (Protocol1 == idma_pkg::AXI_LITE) begin : gen_axi_lite_ar_req - // // assemble AR request - // assign r_req.ar_req = '{ - // addr: { idma_req_i.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // prot: idma_req_i.opt.src.prot - // }; - // end else begin : gen_ar_req_error - // `IDMA_NONSYNTH_BLOCK( - // initial begin - // $fatal(1, "Backend: legalizer bypass ar req not implemented for requested ", - // "protocol!"); - // end - // ) - // end - - // if (Protocol2 == idma_pkg::AXI) begin : gen_axi_aw_req - // // assemble AW request - // assign w_req.aw_req = '{ - // id: idma_req_i.opt.axi_id, - // addr: { idma_req_i.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // len: len, - // size: axi_pkg::size_t'(OffsetWidth), - // burst: idma_req_i.opt.dst.burst, - // lock: idma_req_i.opt.dst.lock, - // cache: idma_req_i.opt.dst.cache, - // prot: idma_req_i.opt.dst.prot, - // qos: idma_req_i.opt.dst.qos, - // region: idma_req_i.opt.dst.region, - // user: '0, - // atop: '0 - // }; - // end else if (Protocol2 == idma_pkg::AXI_LITE) begin : gen_axi_lite_aw_req - // // assemble AW request - // assign w_req.aw_req = '{ - // addr: { idma_req_i.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // prot: idma_req_i.opt.dst.prot - // }; - // end else begin : gen_aw_req_error - // `IDMA_NONSYNTH_BLOCK( - // initial begin - // $fatal(1, "Backend: legalizer bypass aw req not implemented for requested ", - // "protocol!"); - // end - // ) - // end - // assemble read datapath request assign r_req.r_dp_req = '{ offset: idma_req_i.src_addr[OffsetWidth-1:0], @@ -551,43 +489,43 @@ _rsp_t ${protocol}_write_rsp_i, if (ErrorCap == idma_pkg::ERROR_HANDLING) begin : gen_error_handler % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): idma_error_handler #( - .MetaFifoDepth ( MetaFifoDepth ), - .PrintFifoInfo ( PrintFifoInfo ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_eh_req_t ), - .addr_t ( addr_t ), - .r_dp_rsp_t ( r_dp_rsp_t ), - .w_dp_rsp_t ( w_dp_rsp_t ) + .MetaFifoDepth ( MetaFifoDepth ), + .PrintFifoInfo ( PrintFifoInfo ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_eh_req_t ), + .addr_t ( addr_t ), + .r_dp_rsp_t ( r_dp_rsp_t ), + .w_dp_rsp_t ( w_dp_rsp_t ) ) i_idma_error_handler ( - .clk_i, - .rst_ni, - .testmode_i, - .rsp_o ( idma_rsp ), - .rsp_valid_o ( rsp_valid ), - .rsp_ready_i ( rsp_ready ), - .req_valid_i ( req_valid ), - .req_ready_i ( req_ready_o ), - .eh_i ( idma_eh_req_i ), - .eh_valid_i ( eh_req_valid_i ), - .eh_ready_o ( eh_req_ready_o ), - .r_addr_i ( r_req.ar_req.axi.ar_chan.addr ), - .r_consume_i ( r_valid & r_ready ), - .w_addr_i ( w_req.aw_req.axi.aw_chan.addr ), - .w_consume_i ( w_valid & w_ready ), - .legalizer_flush_o ( legalizer_flush ), - .legalizer_kill_o ( legalizer_kill ), - .dp_busy_i ( dp_busy ), - .dp_poison_o ( dp_poison ), - .r_dp_rsp_i ( r_dp_rsp ), - .r_dp_valid_i ( r_dp_rsp_valid ), - .r_dp_ready_o ( r_dp_rsp_ready ), - .w_dp_rsp_i ( w_dp_rsp ), - .w_dp_valid_i ( w_dp_rsp_valid ), - .w_dp_ready_o ( w_dp_rsp_ready ), - .w_last_burst_i ( w_last_burst ), - .w_super_last_i ( w_super_last ), - .fsm_busy_o ( busy_o.eh_fsm_busy ), - .cnt_busy_o ( busy_o.eh_cnt_busy ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .rsp_o ( idma_rsp ), + .rsp_valid_o ( rsp_valid ), + .rsp_ready_i ( rsp_ready ), + .req_valid_i ( req_valid ), + .req_ready_i ( req_ready_o ), + .eh_i ( idma_eh_req_i ), + .eh_valid_i ( eh_req_valid_i ), + .eh_ready_o ( eh_req_ready_o ), + .r_addr_i ( r_req.ar_req.axi.ar_chan.addr ), + .w_addr_i ( w_req.aw_req.axi.aw_chan.addr ), + .r_consume_i ( r_valid & r_ready ), + .w_consume_i ( w_valid & w_ready ), + .legalizer_flush_o ( legalizer_flush ), + .legalizer_kill_o ( legalizer_kill ), + .dp_busy_i ( dp_busy ), + .dp_poison_o ( dp_poison ), + .r_dp_rsp_i ( r_dp_rsp ), + .r_dp_valid_i ( r_dp_rsp_valid ), + .r_dp_ready_o ( r_dp_rsp_ready ), + .w_dp_rsp_i ( w_dp_rsp ), + .w_dp_valid_i ( w_dp_rsp_valid ), + .w_dp_ready_o ( w_dp_rsp_ready ), + .w_last_burst_i ( w_last_burst ), + .w_super_last_i ( w_super_last ), + .fsm_busy_o ( busy_o.eh_fsm_busy ), + .cnt_busy_o ( busy_o.eh_cnt_busy ) ); % else: `IDMA_NONSYNTH_BLOCK( @@ -632,39 +570,39 @@ _rsp_t ${protocol}_write_rsp_i, // Datapath decoupling //-------------------------------------- idma_stream_fifo #( - .Depth ( NumAxInFlight ), - .type_t ( r_dp_req_t ), - .PrintInfo ( PrintFifoInfo ) + .Depth ( NumAxInFlight ), + .type_t ( r_dp_req_t ), + .PrintInfo ( PrintFifoInfo ) ) i_r_dp_req ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( r_req.r_dp_req ), - .valid_i ( r_valid ), - .ready_o ( r_dp_req_in_ready ), - .data_o ( r_dp_req_out ), - .valid_o ( r_dp_req_out_valid ), - .ready_i ( r_dp_req_out_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( r_req.r_dp_req ), + .valid_i ( r_valid ), + .ready_o ( r_dp_req_in_ready ), + .data_o ( r_dp_req_out ), + .valid_o ( r_dp_req_out_valid ), + .ready_i ( r_dp_req_out_ready ) ); idma_stream_fifo #( - .Depth ( NumAxInFlight ), - .type_t ( w_dp_req_t ), - .PrintInfo ( PrintFifoInfo ) + .Depth ( NumAxInFlight ), + .type_t ( w_dp_req_t ), + .PrintInfo ( PrintFifoInfo ) ) i_w_dp_req ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( w_req.w_dp_req ), - .valid_i ( w_valid ), - .ready_o ( w_dp_req_in_ready ), - .data_o ( w_dp_req_out ), - .valid_o ( w_dp_req_out_valid ), - .ready_i ( w_dp_req_out_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( w_req.w_dp_req ), + .valid_i ( w_valid ), + .ready_o ( w_dp_req_in_ready ), + .data_o ( w_dp_req_out ), + .valid_o ( w_dp_req_out_valid ), + .ready_i ( w_dp_req_out_ready ) ); // Add fall-through register to allow the input to be ready if the output is not. This @@ -685,9 +623,9 @@ _rsp_t ${protocol}_write_rsp_i, % endif ) ) i_ar_fall_through_register ( - .clk_i, - .rst_ni, - .testmode_i, + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( ar_ready ), @@ -712,17 +650,17 @@ _rsp_t ${protocol}_write_rsp_i, .type_t ( logic [1:0] ), .PrintInfo ( PrintFifoInfo ) ) i_w_last ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( {w_req.super_last, w_req.last} ), - .valid_i ( w_valid & w_ready ), - .ready_o ( w_last_ready ), - .data_o ( {w_super_last, w_last_burst} ), - .valid_o ( /* NOT CONNECTED */ ), - .ready_i ( w_dp_rsp_valid & w_dp_rsp_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( {w_req.super_last, w_req.last} ), + .valid_i ( w_valid & w_ready ), + .ready_o ( w_last_ready ), + .data_o ( {w_super_last, w_last_burst} ), + .valid_o ( /* NOT CONNECTED */ ), + .ready_i ( w_dp_rsp_valid & w_dp_rsp_ready ) ); //-------------------------------------- diff --git a/src/backend/src/idma_backend_synth.sv.tpl b/src/backend/src/idma_backend_synth.sv.tpl index d0fcfeec..f5689f5a 100644 --- a/src/backend/src/idma_backend_synth.sv.tpl +++ b/src/backend/src/idma_backend_synth.sv.tpl @@ -13,29 +13,29 @@ module idma_backend_synth${name_uniqueifier} #( /// Should both data shifts be done before the dataflow element? /// If this is enabled, then the data inserted into the dataflow element /// will no longer be word aligned, but only a single shifter is needed - parameter bit CombinedShifter = 1'b0, + parameter bit CombinedShifter = 1'b0, /// Data width - parameter int unsigned DataWidth = 32'd32, + parameter int unsigned DataWidth = 32'd32, /// Address width - parameter int unsigned AddrWidth = 32'd32, + parameter int unsigned AddrWidth = 32'd32, /// AXI user width - parameter int unsigned UserWidth = 32'd1, + parameter int unsigned UserWidth = 32'd1, /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd1, /// Number of transaction that can be in-flight concurrently - parameter int unsigned NumAxInFlight = 32'd3, + parameter int unsigned NumAxInFlight = 32'd3, /// The depth of the internal reorder buffer: /// - '2': minimal possible configuration /// - '3': efficiently handle misaligned transfers (recommended) - parameter int unsigned BufferDepth = 32'd3, + parameter int unsigned BufferDepth = 32'd3, /// With of a transfer: max transfer size is `2**TFLenWidth` bytes - parameter int unsigned TFLenWidth = 32'd32, + parameter int unsigned TFLenWidth = 32'd32, /// The depth of the memory system the backend is attached to - parameter int unsigned MemSysDepth = 32'd0, + parameter int unsigned MemSysDepth = 32'd0, /// Mask invalid data on the manager interface - parameter bit MaskInvalidData = 1'b1, + parameter bit MaskInvalidData = 1'b1, /// Should the `R`-`AW` coupling hardware be present? (recommended) - parameter bit RAWCouplingAvail = \ + parameter bit RAWCouplingAvail = \ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): 1, % else: @@ -44,11 +44,11 @@ module idma_backend_synth${name_uniqueifier} #( /// Should hardware legalization be present? (recommended) /// If not, software legalization is required to ensure the transfers are /// AXI4-conformal - parameter bit HardwareLegalizer = 1'b1, + parameter bit HardwareLegalizer = 1'b1, /// Reject zero-length transfers - parameter bit RejectZeroTransfers = 1'b1, + parameter bit RejectZeroTransfers = 1'b1, /// Should the error handler be present? - parameter bit ErrorHandling = 1'b\ + parameter bit ErrorHandling = 1'b\ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): 1, % else: @@ -56,23 +56,23 @@ module idma_backend_synth${name_uniqueifier} #( %endif // Dependent parameters; do not override! /// Strobe Width (do not override!) - parameter int unsigned StrbWidth = DataWidth / 8, + parameter int unsigned StrbWidth = DataWidth / 8, /// Offset Width (do not override!) - parameter int unsigned OffsetWidth = $clog2(StrbWidth), + parameter int unsigned OffsetWidth = $clog2(StrbWidth), /// Address type (do not override!) - parameter type addr_t = logic[AddrWidth-1:0], + parameter type addr_t = logic[AddrWidth-1:0], /// Data type (do not override!) - parameter type data_t = logic[DataWidth-1:0], + parameter type data_t = logic[DataWidth-1:0], /// Strobe type (do not override!) - parameter type strb_t = logic[StrbWidth-1:0], + parameter type strb_t = logic[StrbWidth-1:0], /// User type (do not override!) - parameter type user_t = logic[UserWidth-1:0], + parameter type user_t = logic[UserWidth-1:0], /// ID type (do not override!) - parameter type id_t = logic[AxiIdWidth-1:0], + parameter type id_t = logic[AxiIdWidth-1:0], /// Transfer length type (do not override!) - parameter type tf_len_t = logic[TFLenWidth-1:0], + parameter type tf_len_t = logic[TFLenWidth-1:0], /// Offset type (do not override!) - parameter type offset_t = logic[OffsetWidth-1:0] + parameter type offset_t = logic[OffsetWidth-1:0] )( input logic clk_i, input logic rst_ni, diff --git a/src/backend/src/idma_channel_coupler.sv b/src/backend/src/idma_channel_coupler.sv index 24f99f26..811ac316 100644 --- a/src/backend/src/idma_channel_coupler.sv +++ b/src/backend/src/idma_channel_coupler.sv @@ -120,7 +120,7 @@ module idma_channel_coupler #( assign aw_req_in.decoupled = aw_decouple_aw_i; // aw payload is just connected to fifo - assign aw_req_o = aw_req_out.aw; + assign aw_req_o = aw_req_out.aw; // use a credit counter to keep track of AWs to send always_comb begin : proc_credit_cnt @@ -129,7 +129,7 @@ module idma_channel_coupler #( aw_to_send_d = aw_to_send_q; // if we bypass the logic - aw_sent = aw_req_out.decoupled & aw_valid; + aw_sent = aw_req_out.decoupled & aw_valid; // first is asserted and aw is ready -> just send AW out // without changing the credit counter value diff --git a/src/backend/src/idma_dataflow_element.sv b/src/backend/src/idma_dataflow_element.sv index c48dc047..368c9471 100644 --- a/src/backend/src/idma_dataflow_element.sv +++ b/src/backend/src/idma_dataflow_element.sv @@ -41,15 +41,14 @@ module idma_dataflow_element #( .clk_i, .rst_ni, .testmode_i, - .flush_i ( 1'b0 ), - .data_i ( data_i [i] ), - .valid_i ( valid_i [i] ), - .ready_o ( ready_o [i] ), - .data_o ( data_o [i] ), - .valid_o ( valid_o [i] ), - .ready_i ( ready_i [i] ) + .flush_i ( 1'b0 ), + .data_i ( data_i [i] ), + .valid_i ( valid_i [i] ), + .ready_o ( ready_o [i] ), + .data_o ( data_o [i] ), + .valid_o ( valid_o [i] ), + .ready_i ( ready_i [i] ) ); end : gen_fifo_buffer endmodule : idma_dataflow_element - diff --git a/src/backend/src/idma_error_handler.sv b/src/backend/src/idma_error_handler.sv index ec911876..62f75551 100644 --- a/src/backend/src/idma_error_handler.sv +++ b/src/backend/src/idma_error_handler.sv @@ -55,13 +55,13 @@ module idma_error_handler #( input logic req_ready_i, /// The current read address (burst address) injected into the datapath - input addr_t r_addr_i, + input addr_t r_addr_i, /// The address is consumed by the datapath - input logic r_consume_i, + input logic r_consume_i, /// The current write address (burst address) injected into the datapath - input addr_t w_addr_i, + input addr_t w_addr_i, /// The address is consumed by the datapath - input logic w_consume_i, + input logic w_consume_i, /// Invalidate the current burst transfer, stops emission of requests output logic legalizer_flush_o, @@ -230,9 +230,9 @@ module idma_error_handler #( // a proper write response (lowest priority) if (w_dp_rsp_i.resp == axi_pkg::RESP_OKAY & w_dp_valid_i & w_last_burst_i) begin - rsp_o = '0; - rsp_o.last = w_super_last_i; - rsp_valid_o = 1'b1; + rsp_o = '0; + rsp_o.last = w_super_last_i; + rsp_valid_o = 1'b1; //rb_out_ready = 1'b1; // pop buffer end @@ -250,9 +250,9 @@ module idma_error_handler #( r_dp_ready_o = 1'b0; // go to one of the wait states if (w_last_burst_i) begin - state_d = WAIT_LAST_W; + state_d = WAIT_LAST_W; end else begin - state_d = WAIT; + state_d = WAIT; end end @@ -279,8 +279,8 @@ module idma_error_handler #( if (eh_valid_i) begin // continue case (~error reporting) if (eh_i == idma_pkg::CONTINUE) begin - eh_ready_o = 1'b1; - state_d = IDLE; + eh_ready_o = 1'b1; + state_d = IDLE; end // abort if (eh_i == idma_pkg::ABORT) begin @@ -289,13 +289,13 @@ module idma_error_handler #( // - some transfers might complete properly so no flush allowed! // in this case just continue if (num_outst_q > 'd1) begin - eh_ready_o = 1'b1; - state_d = IDLE; + eh_ready_o = 1'b1; + state_d = IDLE; // we are aborting a long transfer (it is still in the legalizer and // therefore the only active transfer in the datapath) end else if (num_outst_q == 'd1) begin - eh_ready_o = 1'b1; - state_d = LEG_FLUSH; + eh_ready_o = 1'b1; + state_d = LEG_FLUSH; // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin @@ -312,7 +312,7 @@ module idma_error_handler #( WAIT_LAST_W : begin // continue case (~error reporting) if (eh_i == idma_pkg::CONTINUE) begin - eh_ready_o = 1'b1; + eh_ready_o = 1'b1; state_d = EMIT_EXTRA_RSP; end // abort @@ -322,13 +322,13 @@ module idma_error_handler #( // - some transfers might complete properly so no flush allowed! // in this case just continue if (num_outst_q > 'd1) begin - eh_ready_o = 1'b1; - state_d = EMIT_EXTRA_RSP; + eh_ready_o = 1'b1; + state_d = EMIT_EXTRA_RSP; // we are aborting a long transfer (it is still in the legalizer and // therefore the only active transfer in the datapath) end else if (num_outst_q == 'd1) begin - eh_ready_o = 1'b1; - state_d = LEG_FLUSH; + eh_ready_o = 1'b1; + state_d = LEG_FLUSH; // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin @@ -356,8 +356,8 @@ module idma_error_handler #( r_dp_ready_o = 1'b1; // once the datapath is idle return to idle if (!dp_busy_i) begin - state_d = EMIT_EXTRA_RSP; - legalizer_kill_o = 1'b1; + state_d = EMIT_EXTRA_RSP; + legalizer_kill_o = 1'b1; end end diff --git a/src/backend/src/idma_legalizer.sv.tpl b/src/backend/src/idma_legalizer.sv.tpl index 4bd5982d..cba17e83 100644 --- a/src/backend/src/idma_legalizer.sv.tpl +++ b/src/backend/src/idma_legalizer.sv.tpl @@ -143,9 +143,9 @@ ${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\ logic w_tf_ena; // page boundaries - page_len_t r_num_bytes_to_pb; - page_len_t w_num_bytes_to_pb; - page_len_t c_num_bytes_to_pb; + page_len_t r_num_bytes_to_pb; + page_len_t w_num_bytes_to_pb; + page_len_t c_num_bytes_to_pb; // read process page_len_t r_num_bytes_possible; @@ -524,9 +524,9 @@ w_tf_q.length[PageAddrWidth:0] ), //-------------------------------------- if (kill_i) begin // kill the current state - r_tf_d = '0; + r_tf_d = '0; + w_tf_d = '0; r_done = 1'b1; - w_tf_d = '0; w_done = 1'b1; end @@ -790,9 +790,9 @@ ${database[protocol]['legalizer_write_data_path']} //-------------------------------------- // State //-------------------------------------- - `FF(opt_tf_q, opt_tf_d, '0, clk_i, rst_ni) - `FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni) - `FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni) + `FF (opt_tf_q, opt_tf_d, '0, clk_i, rst_ni) + `FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni) + `FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni) //-------------------------------------- diff --git a/src/backend/src/protocol_managers/axi/idma_axi_read.sv b/src/backend/src/protocol_managers/axi/idma_axi_read.sv index 8b130d61..ba9b615d 100644 --- a/src/backend/src/protocol_managers/axi/idma_axi_read.sv +++ b/src/backend/src/protocol_managers/axi/idma_axi_read.sv @@ -55,9 +55,9 @@ module idma_axi_read #( output logic ar_ready_o, /// AXI4+ATOP read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI4+ATOP read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -167,7 +167,7 @@ module idma_axi_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read @@ -190,11 +190,11 @@ module idma_axi_read #( // Unused AXI signals //-------------------------------------- assign read_req_o.aw_valid = 1'b0; - assign read_req_o.w_valid = 1'b0; - assign read_req_o.b_ready = 1'b0; + assign read_req_o.w_valid = 1'b0; + assign read_req_o.b_ready = 1'b0; assign read_req_o.aw = '0; - assign read_req_o.w = '0; + assign read_req_o.w = '0; //-------------------------------------- // State diff --git a/src/backend/src/protocol_managers/axi/idma_axi_write.sv b/src/backend/src/protocol_managers/axi/idma_axi_write.sv index d50bc8c9..174e05df 100644 --- a/src/backend/src/protocol_managers/axi/idma_axi_write.sv +++ b/src/backend/src/protocol_managers/axi/idma_axi_write.sv @@ -180,8 +180,8 @@ module idma_axi_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.w.data = '0; - write_req_o.w.strb = '0; + write_req_o.w.data = '0; + write_req_o.w.strb = '0; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -200,8 +200,8 @@ module idma_axi_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.w.data = buffer_out_i; - assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; + assign write_req_o.w.data = buffer_out_i; + assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; end // the w last signal should only be applied to the bus if an actual transfer happens @@ -214,11 +214,11 @@ module idma_axi_write #( always_comb begin : proc_write_control // defaults: // beat counter - w_num_beats_d = w_num_beats_q; - w_cnt_valid_d = w_cnt_valid_q; + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; // mask control - first_w = 1'b0; - last_w = 1'b0; + first_w = 1'b0; + last_w = 1'b0; // differentiate between the burst and non-burst case. If a transfer // consists just of one beat the counters are disabled @@ -279,10 +279,9 @@ module idma_axi_write #( //-------------------------------------- // Unused AXI signals //-------------------------------------- + assign write_req_o.ar = '0; assign write_req_o.ar_valid = 1'b0; - assign write_req_o.r_ready = 1'b0; - - assign write_req_o.ar = '0; + assign write_req_o.r_ready = 1'b0; //-------------------------------------- // State diff --git a/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_read.sv b/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_read.sv index c6815cb4..c0bc3fbe 100644 --- a/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_read.sv +++ b/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_read.sv @@ -48,9 +48,9 @@ module idma_axi_lite_read #( output logic ar_ready_o, /// AXI Lite read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI Lite read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -119,7 +119,7 @@ module idma_axi_lite_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read @@ -131,8 +131,7 @@ module idma_axi_lite_read #( assign r_dp_rsp_o.first = 1'b1; // r_dp_valid_o is triggered once the last element is here or an error occurs - assign r_dp_valid_o = read_rsp_i.r_valid & in_ready; - + assign r_dp_valid_o = read_rsp_i.r_valid & in_ready; assign r_chan_ready_o = read_req_o.r_ready; assign r_chan_valid_o = read_rsp_i.r_valid; @@ -140,10 +139,10 @@ module idma_axi_lite_read #( // Unused AXI Lite signals //-------------------------------------- assign read_req_o.aw_valid = 1'b0; - assign read_req_o.w_valid = 1'b0; - assign read_req_o.b_ready = 1'b0; + assign read_req_o.w_valid = 1'b0; + assign read_req_o.b_ready = 1'b0; assign read_req_o.aw = '0; - assign read_req_o.w = '0; + assign read_req_o.w = '0; endmodule : idma_axi_lite_read diff --git a/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_write.sv b/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_write.sv index ee73469b..efab2b53 100644 --- a/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_write.sv +++ b/src/backend/src/protocol_managers/axi_lite/idma_axi_lite_write.sv @@ -99,7 +99,6 @@ module idma_axi_lite_write #( assign mask_out = ('1 << w_dp_req_i.offset) & ((w_dp_req_i.tailer != '0) ? ('1 >> (StrbWidth - w_dp_req_i.tailer)) : '1); - //-------------------------------------- // Write control //-------------------------------------- @@ -133,8 +132,8 @@ module idma_axi_lite_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.w.data = '0; - write_req_o.w.strb = '0; + write_req_o.w.data = '0; + write_req_o.w.strb = '0; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -153,14 +152,13 @@ module idma_axi_lite_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.w.data = buffer_out_i; - assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; + assign write_req_o.w.data = buffer_out_i; + assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; end // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_ready_o = write_happening; - //-------------------------------------- // Write response //-------------------------------------- @@ -174,13 +172,11 @@ module idma_axi_lite_write #( // write responses assign write_req_o.b_ready = w_dp_ready_i; - //-------------------------------------- // Unused AXI Lite signals //-------------------------------------- + assign write_req_o.ar = '0; assign write_req_o.ar_valid = 1'b0; - assign write_req_o.r_ready = 1'b0; - - assign write_req_o.ar = '0; + assign write_req_o.r_ready = 1'b0; endmodule : idma_axi_lite_write diff --git a/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_read.sv b/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_read.sv index dc4aa607..4edd7366 100644 --- a/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_read.sv +++ b/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_read.sv @@ -48,9 +48,9 @@ module idma_axi_stream_read #( output logic read_meta_ready_o, /// AXI Stream read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI Stream read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -117,14 +117,13 @@ module idma_axi_stream_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i; + assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_rsp_i.tvalid & in_ready; - - assign r_chan_ready_o = read_req_o.tready; - assign r_chan_valid_o = read_rsp_i.tvalid; + assign r_chan_ready_o = read_req_o.tready; + assign r_chan_valid_o = read_rsp_i.tvalid; // connect r_dp response payload assign r_dp_rsp_o.resp = '0; diff --git a/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_write.sv b/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_write.sv index afe868ff..493f9b5e 100644 --- a/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_write.sv +++ b/src/backend/src/protocol_managers/axi_stream/idma_axi_stream_write.sv @@ -122,7 +122,7 @@ module idma_axi_stream_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.t = aw_req_i.axi_stream.t_chan; + write_req_o.t = aw_req_i.axi_stream.t_chan; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -148,7 +148,7 @@ module idma_axi_stream_write #( // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_req_ready_o = write_happening; - assign aw_ready_o = write_happening; + assign aw_ready_o = write_happening; //-------------------------------------- // Write response @@ -170,4 +170,5 @@ module idma_axi_stream_write #( .valid_o ( { w_dp_rsp_valid_o, write_req_o.tvalid } ), .ready_i ( { w_dp_rsp_ready_i, write_rsp_i.tready } ) ); + endmodule : idma_axi_stream_write diff --git a/src/backend/src/protocol_managers/init/idma_init_read.sv b/src/backend/src/protocol_managers/init/idma_init_read.sv index 3674d76d..4341d2b8 100644 --- a/src/backend/src/protocol_managers/init/idma_init_read.sv +++ b/src/backend/src/protocol_managers/init/idma_init_read.sv @@ -48,9 +48,9 @@ module idma_init_read #( output logic read_meta_ready_o, /// INIT read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// INIT read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -78,7 +78,7 @@ module idma_init_read #( //-------------------------------------- // Read meta channel //-------------------------------------- - // connect the ar requests to the AXI bus + // connect the ar requests to the INIT read bus assign read_req_o.req_chan = read_meta_req_i.init.req_chan; assign read_req_o.req_valid = read_meta_valid_i; assign read_meta_ready_o = read_rsp_i.req_ready; @@ -119,12 +119,11 @@ module idma_init_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.rsp_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.rsp_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read - assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.rsp_valid & in_ready; - + assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.rsp_valid & in_ready; assign r_chan_ready_o = read_req_o.rsp_ready; assign r_chan_valid_o = read_rsp_i.rsp_valid; diff --git a/src/backend/src/protocol_managers/obi/idma_obi_read.sv b/src/backend/src/protocol_managers/obi/idma_obi_read.sv index 8d6a9f6f..f5060e35 100644 --- a/src/backend/src/protocol_managers/obi/idma_obi_read.sv +++ b/src/backend/src/protocol_managers/obi/idma_obi_read.sv @@ -48,9 +48,9 @@ module idma_obi_read #( output logic read_meta_ready_o, /// OBI read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// OBI read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -119,12 +119,11 @@ module idma_obi_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read - assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.r_valid & in_ready; - + assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.r_valid & in_ready; assign r_chan_ready_o = read_req_o.r_ready; assign r_chan_valid_o = read_rsp_i.r_valid; diff --git a/src/backend/src/protocol_managers/obi/idma_obi_write.sv b/src/backend/src/protocol_managers/obi/idma_obi_write.sv index 2ae4123d..313b0650 100644 --- a/src/backend/src/protocol_managers/obi/idma_obi_write.sv +++ b/src/backend/src/protocol_managers/obi/idma_obi_write.sv @@ -145,7 +145,7 @@ module idma_obi_write #( // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_ready_o = write_happening; - assign aw_ready_o = write_happening; + assign aw_ready_o = write_happening; //-------------------------------------- // Write response diff --git a/src/backend/src/protocol_managers/tilelink/idma_tilelink_read.sv b/src/backend/src/protocol_managers/tilelink/idma_tilelink_read.sv index 1327f7be..f7f8e2ed 100644 --- a/src/backend/src/protocol_managers/tilelink/idma_tilelink_read.sv +++ b/src/backend/src/protocol_managers/tilelink/idma_tilelink_read.sv @@ -57,9 +57,9 @@ module idma_tilelink_read #( output logic read_meta_ready_o, /// TileLink read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// TileLink read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -189,7 +189,7 @@ module idma_tilelink_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.d_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.d_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read diff --git a/src/backend/src/protocol_managers/tilelink/idma_tilelink_write.sv b/src/backend/src/protocol_managers/tilelink/idma_tilelink_write.sv index aa9fb13d..2762baab 100644 --- a/src/backend/src/protocol_managers/tilelink/idma_tilelink_write.sv +++ b/src/backend/src/protocol_managers/tilelink/idma_tilelink_write.sv @@ -192,8 +192,8 @@ module idma_tilelink_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.a.data = buffer_out_i; - assign write_req_o.a.mask = dp_poison_i ? '0 : mask_out; + assign write_req_o.a.data = buffer_out_i; + assign write_req_o.a.mask = dp_poison_i ? '0 : mask_out; end // the w last signal should only be applied to the bus if an actual transfer happens @@ -207,11 +207,11 @@ module idma_tilelink_write #( always_comb begin : proc_write_control // defaults: // beat counter - w_num_beats_d = w_num_beats_q; - w_cnt_valid_d = w_cnt_valid_q; + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; // mask control - first_w = 1'b0; - last_w = 1'b0; + first_w = 1'b0; + last_w = 1'b0; // differentiate between the burst and non-burst case. If a transfer // consists just of one beat the counters are disabled