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FrancescoContiFrancescoConti
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Merge pull request #12 from pulp-platform/ff-regfile
Added FF-based register file.
2 parents 877d676 + 01a68c2 commit 0576d0c

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5 files changed

+130
-21
lines changed

5 files changed

+130
-21
lines changed

‎Bender.yml‎

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@@ -17,6 +17,7 @@ sources:
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- rtl/hwpe_ctrl_interfaces.sv
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- rtl/hwpe_ctrl_package.sv
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# Level 1
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- rtl/hwpe_ctrl_regfile_ff.sv
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- rtl/hwpe_ctrl_regfile_latch.sv
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- rtl/hwpe_ctrl_seq_mult.sv
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- rtl/hwpe_ctrl_uloop.sv

‎rtl/hwpe_ctrl_regfile.sv‎

Lines changed: 5 additions & 3 deletions
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@@ -17,6 +17,7 @@
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module hwpe_ctrl_regfile
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import hwpe_ctrl_package::*;
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#(
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parameter int unsigned REGFILE_SCM = 1,
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parameter int unsigned N_CONTEXT = REGFILE_N_CONTEXT,
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parameter int unsigned ID_WIDTH = 16,
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parameter int unsigned N_IO_REGS = 2,
@@ -101,9 +102,10 @@ module hwpe_ctrl_regfile
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logic [N_CONTEXT-1:0] wren_cxt;
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hwpe_ctrl_regfile_latch_test_wrap #(
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.ADDR_WIDTH(SCM_ADDR_WIDTH),
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.DATA_WIDTH(32)
106-
) i_regfile_latch (
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.REGFILE_SCM ( REGFILE_SCM ),
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.ADDR_WIDTH ( SCM_ADDR_WIDTH ),
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.DATA_WIDTH ( 32 )
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) i_regfile (
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.clk ( clk_i ),
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.rst_n ( rst_ni ),
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.clear ( clear_i | r_clear_first_startup ),

‎rtl/hwpe_ctrl_regfile_ff.sv‎

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@@ -0,0 +1,84 @@
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/*
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* hwpe_ctrl_regfile_latch.sv
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* Francesco Conti <fconti@iis.ee.ethz.ch>
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*
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* Copyright (C) 2014-2018 ETH Zurich, University of Bologna
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* Yvan Tortorella <yvan.tortorella@unibo.it>
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*
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*/
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module hwpe_ctrl_regfile_ff #(
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parameter int unsigned AddrWidth = 5,
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parameter int unsigned DataWidth = 32,
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localparam int unsigned NumWords = 2**AddrWidth,
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localparam int unsigned NumByte = DataWidth/8
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)(
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input logic clk_i ,
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input logic rst_ni ,
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input logic clear_i,
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// Read port
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input logic ReadEnable_i,
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input logic [AddrWidth-1:0] ReadAddr_i ,
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output logic [DataWidth-1:0] ReadData_o ,
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// Write port
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input logic WriteEnable_i,
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input logic [AddrWidth-1:0] WriteAddr_i ,
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input logic [DataWidth-1:0] WriteData_i ,
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input logic [NumByte-1:0] WriteBE_i ,
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// Memory content (false paths!)
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output logic [NumWords-1:0][DataWidth-1:0] MemContent_o
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);
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logic [NumWords-1:0][DataWidth-1:0] data_d, data_q;
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logic clk_int;
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logic enable, clkg_en;
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assign enable = WriteEnable_i & (WriteAddr_i <= NumWords);
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assign clkg_en = enable | clear_i;
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assign ReadData_o = (ReadEnable_i && (ReadAddr_i <= NumWords)) ? data_q[ReadAddr_i] : '0;
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tc_clk_gating i_we_clkg (
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.clk_i ( clk_i ),
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.en_i ( clkg_en ),
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.test_en_i ( 1'b0 ),
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.clk_o ( clk_int )
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);
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for (genvar i = 0; i < NumWords; i++) begin
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for (genvar j = 0; j < NumByte; j++) begin
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assign data_d[i][j*8+:8] = (enable && (WriteAddr_i == i)) ? (WriteData_i[j*8+:8] & {8{WriteBE_i[j]}})
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: data_q[i][j*8+:8];
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end
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end
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always_ff @(posedge clk_int, negedge rst_ni) begin
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if (~rst_ni)
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data_q <= '0;
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else begin
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if (clear_i)
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data_q <= '0;
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else
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data_q <= data_d;
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end
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end
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for (genvar i = 0; i < NumWords; i++) begin
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assign MemContent_o[i] = data_q[i];
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end
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endmodule : hwpe_ctrl_regfile_ff

‎rtl/hwpe_ctrl_regfile_latch_test_wrap.sv‎

Lines changed: 38 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515

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module hwpe_ctrl_regfile_latch_test_wrap
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#(
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parameter int unsigned REGFILE_SCM = 1,
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parameter ADDR_WIDTH = 5,
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parameter DATA_WIDTH = 32,
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parameter NUM_BYTE = DATA_WIDTH/8
@@ -82,23 +83,42 @@ module hwpe_ctrl_regfile_latch_test_wrap
8283
end
8384

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assign Q_T = ReadData;
85-
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hwpe_ctrl_regfile_latch #(
87-
.ADDR_WIDTH ( ADDR_WIDTH ),
88-
.DATA_WIDTH ( DATA_WIDTH ),
89-
.NUM_BYTE ( NUM_BYTE )
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) hwpe_ctrl_regfile_latch_i (
91-
.clk ( clk ),
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.rst_n ( rst_n ),
93-
.clear ( clear ),
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.ReadEnable ( ReadEnable_muxed ),
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.ReadAddr ( ReadAddr_muxed ),
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.ReadData ( ReadData ),
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.WriteEnable ( WriteEnable_muxed ),
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.WriteAddr ( WriteAddr_muxed ),
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.WriteData ( WriteData_muxed ),
100-
.WriteBE ( WriteBE_muxed ),
101-
.MemContent ( MemContent )
102-
);
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if (REGFILE_SCM == 1) begin : gen_scm_regfile
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hwpe_ctrl_regfile_latch #(
89+
.ADDR_WIDTH ( ADDR_WIDTH ),
90+
.DATA_WIDTH ( DATA_WIDTH ),
91+
.NUM_BYTE ( NUM_BYTE )
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) hwpe_ctrl_regfile_latch_i (
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.clk ( clk ),
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.rst_n ( rst_n ),
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.clear ( clear ),
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.ReadEnable ( ReadEnable_muxed ),
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.ReadAddr ( ReadAddr_muxed ),
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.ReadData ( ReadData ),
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.WriteEnable ( WriteEnable_muxed ),
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.WriteAddr ( WriteAddr_muxed ),
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.WriteData ( WriteData_muxed ),
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.WriteBE ( WriteBE_muxed ),
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.MemContent ( MemContent )
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);
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end else begin : gen_ff_regfile
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hwpe_ctrl_regfile_ff #(
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.AddrWidth ( ADDR_WIDTH ),
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.DataWidth ( DATA_WIDTH )
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) hwpe_ctrl_regfile_ff_i (
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.clk_i ( clk ),
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.rst_ni ( rst_n ),
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.clear_i ( clear ),
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.ReadEnable_i ( ReadEnable_muxed ),
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.ReadAddr_i ( ReadAddr_muxed ),
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.ReadData_o ( ReadData ),
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.WriteEnable_i ( WriteEnable_muxed ),
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.WriteAddr_i ( WriteAddr_muxed ),
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.WriteData_i ( WriteData_muxed ),
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.WriteBE_i ( WriteBE_muxed ),
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.MemContent_o ( MemContent )
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);
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end
103123

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endmodule // hwpe_ctrl_regfile_latch

‎rtl/hwpe_ctrl_slave.sv‎

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@@ -17,6 +17,7 @@
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module hwpe_ctrl_slave
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import hwpe_ctrl_package::*;
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#(
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parameter int unsigned REGFILE_SCM = 1,
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parameter int unsigned N_CORES = 4,
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parameter int unsigned N_CONTEXT = 2,
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parameter int unsigned N_EVT = REGFILE_N_EVT,
@@ -240,6 +241,7 @@ module hwpe_ctrl_slave
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assign regfile_flags.running_context = running_context;
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242243
hwpe_ctrl_regfile #(
244+
.REGFILE_SCM ( REGFILE_SCM ),
243245
.N_CONTEXT ( N_CONTEXT ),
244246
.N_IO_REGS ( N_IO_REGS ),
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.N_GENERIC_REGS ( N_GENERIC_REGS ),

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