diff --git a/src/addr_decode_dync.sv b/src/addr_decode_dync.sv index a0be24fb..c1fc84d3 100644 --- a/src/addr_decode_dync.sv +++ b/src/addr_decode_dync.sv @@ -122,7 +122,7 @@ module addr_decode_dync #( end // Assumptions and assertions - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef XSIM // pragma translate_off initial begin : proc_check_parameters diff --git a/src/cb_filter.sv b/src/cb_filter.sv index bccfe1ce..bb300afe 100644 --- a/src/cb_filter.sv +++ b/src/cb_filter.sv @@ -235,7 +235,7 @@ module hash_block #( end end -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF // assertions // pragma translate_off initial begin diff --git a/src/cdc_2phase_clearable.sv b/src/cdc_2phase_clearable.sv index 1d86dad8..d8adf9b6 100644 --- a/src/cdc_2phase_clearable.sv +++ b/src/cdc_2phase_clearable.sv @@ -185,7 +185,7 @@ module cdc_2phase_clearable #( assign dst_clear_pending_o = s_dst_isolate_req; -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF no_valid_i_during_clear_i : assert property ( @(posedge src_clk_i) disable iff (!src_rst_ni) src_clear_i |-> !src_valid_i @@ -257,7 +257,7 @@ module cdc_2phase_src_clearable #( assign async_data_o = data_src_q; // Assertions -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF // pragma translate_off no_clear_and_request: assume property ( @(posedge clk_i) disable iff(~rst_ni) (clear_i |-> ~valid_i)) diff --git a/src/cdc_fifo_gray.sv b/src/cdc_fifo_gray.sv index 6ba477ea..195917ba 100644 --- a/src/cdc_fifo_gray.sv +++ b/src/cdc_fifo_gray.sv @@ -158,7 +158,7 @@ module cdc_fifo_gray #( // Check the invariants. // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF initial assert(LOG_DEPTH > 0); initial assert(SYNC_STAGES >= 2); `endif diff --git a/src/cdc_fifo_gray_clearable.sv b/src/cdc_fifo_gray_clearable.sv index 10257484..1ed4e6d5 100644 --- a/src/cdc_fifo_gray_clearable.sv +++ b/src/cdc_fifo_gray_clearable.sv @@ -255,7 +255,7 @@ module cdc_fifo_gray_clearable #( // Check the invariants. // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF initial assert(LOG_DEPTH > 0); initial assert(SYNC_STAGES >= 2); `endif diff --git a/src/cf_math_pkg.sv b/src/cf_math_pkg.sv index d1270e2d..2d86f2bf 100644 --- a/src/cf_math_pkg.sv +++ b/src/cf_math_pkg.sv @@ -24,7 +24,7 @@ package cf_math_pkg; automatic longint remainder; // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF if (dividend < 0) begin $fatal(1, "Dividend %0d is not a natural number!", dividend); end diff --git a/src/deprecated/fifo_v2.sv b/src/deprecated/fifo_v2.sv index 4782cb1d..326839db 100644 --- a/src/deprecated/fifo_v2.sv +++ b/src/deprecated/fifo_v2.sv @@ -68,7 +68,7 @@ module fifo_v2 #( ); // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF initial begin assert (ALM_FULL_TH <= DEPTH) else $error("ALM_FULL_TH can't be larger than the DEPTH."); assert (ALM_EMPTY_TH <= DEPTH) else $error("ALM_EMPTY_TH can't be larger than the DEPTH."); diff --git a/src/exp_backoff.sv b/src/exp_backoff.sv index 06df6dd2..cf248ef9 100644 --- a/src/exp_backoff.sv +++ b/src/exp_backoff.sv @@ -82,7 +82,7 @@ module exp_backoff #( /////////////////////////////////////////////////////// //pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin // assert wrong parameterizations assert (MaxExp>0) diff --git a/src/fifo_v3.sv b/src/fifo_v3.sv index 411bfbc0..53eed297 100644 --- a/src/fifo_v3.sv +++ b/src/fifo_v3.sv @@ -138,7 +138,7 @@ module fifo_v3 #( end // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); end diff --git a/src/id_queue.sv b/src/id_queue.sv index d45ab58d..833d98ef 100644 --- a/src/id_queue.sv +++ b/src/id_queue.sv @@ -405,7 +405,7 @@ module id_queue #( // Validate parameters. // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: validate_params assert (ID_WIDTH >= 1) else $fatal(1, "The ID must at least be one bit wide!"); diff --git a/src/isochronous_4phase_handshake.sv b/src/isochronous_4phase_handshake.sv index 832bf4cf..d9e5fd53 100644 --- a/src/isochronous_4phase_handshake.sv +++ b/src/isochronous_4phase_handshake.sv @@ -70,7 +70,7 @@ module isochronous_4phase_handshake ( // pragma translate_off // stability guarantees - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF assert property (@(posedge src_clk_i) disable iff (~src_rst_ni) (src_valid_i && !src_ready_o |=> $stable(src_valid_i))) else $error("src_valid_i is unstable"); assert property (@(posedge dst_clk_i) disable iff (~dst_rst_ni) diff --git a/src/isochronous_spill_register.sv b/src/isochronous_spill_register.sv index e254776d..547260bf 100644 --- a/src/isochronous_spill_register.sv +++ b/src/isochronous_spill_register.sv @@ -97,7 +97,7 @@ module isochronous_spill_register #( // pragma translate_off // stability guarantees - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF assert property (@(posedge src_clk_i) disable iff (~src_rst_ni) (src_valid_i && !src_ready_o |=> $stable(src_valid_i))) else $error("src_valid_i is unstable"); assert property (@(posedge src_clk_i) disable iff (~src_rst_ni) diff --git a/src/lfsr.sv b/src/lfsr.sv index d7ea81e2..f1678964 100644 --- a/src/lfsr.sv +++ b/src/lfsr.sv @@ -289,7 +289,7 @@ end //////////////////////////////////////////////////////////////////////// // assertions //////////////////////////////////////////////////////////////////////// -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF // pragma translate_off initial begin // these are the LUT limits diff --git a/src/lfsr_16bit.sv b/src/lfsr_16bit.sv index 0c0e5850..a2319d7a 100644 --- a/src/lfsr_16bit.sv +++ b/src/lfsr_16bit.sv @@ -58,7 +58,7 @@ module lfsr_16bit #( end end - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF //pragma translate_off initial begin assert (WIDTH <= 16) diff --git a/src/lfsr_8bit.sv b/src/lfsr_8bit.sv index f350e3e9..2211fcdc 100644 --- a/src/lfsr_8bit.sv +++ b/src/lfsr_8bit.sv @@ -52,7 +52,7 @@ module lfsr_8bit #( end end -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF //pragma translate_off initial begin assert (WIDTH <= 8) else $fatal(1, "WIDTH needs to be less than 8 because of the 8-bit LFSR"); diff --git a/src/lzc.sv b/src/lzc.sv index b0a7700c..65e8f6c9 100644 --- a/src/lzc.sv +++ b/src/lzc.sv @@ -39,7 +39,7 @@ module lzc #( localparam int unsigned NumLevels = $clog2(WIDTH); - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF // pragma translate_off initial begin assert(WIDTH > 0) else $fatal(1, "input must be at least one bit wide"); @@ -102,7 +102,7 @@ module lzc #( end : gen_lzc // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: validate_params assert (WIDTH >= 1) else $fatal(1, "The WIDTH must at least be one bit wide!"); diff --git a/src/mem_to_banks_detailed.sv b/src/mem_to_banks_detailed.sv index 0e4ba737..b603d979 100644 --- a/src/mem_to_banks_detailed.sv +++ b/src/mem_to_banks_detailed.sv @@ -209,7 +209,7 @@ module mem_to_banks_detailed #( // Assertions // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef SYNTHESIS initial begin assume (DataWidth != 0 && (DataWidth & (DataWidth - 1)) == 0) diff --git a/src/multiaddr_decode.sv b/src/multiaddr_decode.sv index 00d0a361..a764543d 100644 --- a/src/multiaddr_decode.sv +++ b/src/multiaddr_decode.sv @@ -120,7 +120,7 @@ module multiaddr_decode #( end // Assumptions and assertions - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef XSIM // pragma translate_off initial begin : proc_check_parameters diff --git a/src/onehot_to_bin.sv b/src/onehot_to_bin.sv index 05b0365d..58881a53 100644 --- a/src/onehot_to_bin.sv +++ b/src/onehot_to_bin.sv @@ -30,7 +30,7 @@ module onehot_to_bin #( end // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF assert final ($onehot0(onehot)) else $fatal(1, "[onehot_to_bin] More than two bit set in the one-hot signal"); `endif diff --git a/src/plru_tree.sv b/src/plru_tree.sv index fbb50264..4283e5b8 100644 --- a/src/plru_tree.sv +++ b/src/plru_tree.sv @@ -110,7 +110,7 @@ module plru_tree #( end // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin assert (ENTRIES == 2**LogEntries) else $error("Entries must be a power of two"); end diff --git a/src/rr_arb_tree.sv b/src/rr_arb_tree.sv index b5a248c4..31d51f11 100644 --- a/src/rr_arb_tree.sv +++ b/src/rr_arb_tree.sv @@ -110,7 +110,7 @@ module rr_arb_tree #( ); // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef VERILATOR `ifndef XSIM // Default SVA reset @@ -171,7 +171,7 @@ module rr_arb_tree #( end // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF lock: assert property( @(posedge clk_i) disable iff (!rst_ni || flush_i) LockIn |-> req_o && (!gnt_i && !flush_i) |=> idx_o == $past(idx_o)) else @@ -310,7 +310,7 @@ module rr_arb_tree #( end // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef XSIM initial begin : p_assert assert(NumIn) diff --git a/src/rstgen_bypass.sv b/src/rstgen_bypass.sv index bef06f53..24efdc2c 100644 --- a/src/rstgen_bypass.sv +++ b/src/rstgen_bypass.sv @@ -58,7 +58,7 @@ module rstgen_bypass #( end end // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF initial begin : p_assertions if (NumRegs < 1) $fatal(1, "At least one register is required."); end diff --git a/src/spill_register_flushable.sv b/src/spill_register_flushable.sv index 8d264710..5200b860 100644 --- a/src/spill_register_flushable.sv +++ b/src/spill_register_flushable.sv @@ -95,7 +95,7 @@ module spill_register_flushable #( assign data_o = b_full_q ? b_data_q : a_data_q; // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF flush_valid : assert property ( @(posedge clk_i) disable iff (~rst_ni) (flush_i |-> ~valid_i)) else $warning("Trying to flush and feed the spill register simultaneously. You will lose data!"); diff --git a/src/stream_fork.sv b/src/stream_fork.sv index 5b93b7b8..f34d8b3a 100644 --- a/src/stream_fork.sv +++ b/src/stream_fork.sv @@ -123,7 +123,7 @@ module stream_fork #( // of the '1 literal when assigned to a port of parametrized width. // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: p_assertions assert (N_OUP >= 1) else $fatal(1, "Number of outputs must be at least 1!"); end diff --git a/src/stream_fork_dynamic.sv b/src/stream_fork_dynamic.sv index cf348675..6a0e36fa 100644 --- a/src/stream_fork_dynamic.sv +++ b/src/stream_fork_dynamic.sv @@ -86,7 +86,7 @@ module stream_fork_dynamic #( ); // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: p_assertions assert (N_OUP >= 1) else $fatal(1, "N_OUP must be at least 1!"); end diff --git a/src/stream_intf.sv b/src/stream_intf.sv index 5f76a241..5bf7e351 100644 --- a/src/stream_intf.sv +++ b/src/stream_intf.sv @@ -41,7 +41,7 @@ interface STREAM_DV #( // Make sure that the handshake and payload is stable // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF assert property (@(posedge clk_i) (valid && !ready |=> $stable(data))); assert property (@(posedge clk_i) (valid && !ready |=> valid)); `endif diff --git a/src/stream_join_dynamic.sv b/src/stream_join_dynamic.sv index 71f77d67..acf603c5 100644 --- a/src/stream_join_dynamic.sv +++ b/src/stream_join_dynamic.sv @@ -38,7 +38,7 @@ module stream_join_dynamic #( end // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: p_assertions assert (N_INP >= 1) else $fatal(1, "N_INP must be at least 1!"); end diff --git a/src/stream_mux.sv b/src/stream_mux.sv index ae5ec490..31ab5399 100644 --- a/src/stream_mux.sv +++ b/src/stream_mux.sv @@ -36,7 +36,7 @@ module stream_mux #( assign oup_valid_o = inp_valid_i[inp_sel_i]; // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF initial begin: p_assertions assert (N_INP >= 1) else $fatal (1, "The number of inputs must be at least 1!"); end diff --git a/src/stream_omega_net.sv b/src/stream_omega_net.sv index 1194a792..fa75e5f7 100644 --- a/src/stream_omega_net.sv +++ b/src/stream_omega_net.sv @@ -261,7 +261,7 @@ module stream_omega_net #( // Assertions // Make sure that the handshake and payload is stable // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef VERILATOR default disable iff (~rst_ni); `endif diff --git a/src/stream_to_mem.sv b/src/stream_to_mem.sv index 817b748e..46871795 100644 --- a/src/stream_to_mem.sv +++ b/src/stream_to_mem.sv @@ -117,7 +117,7 @@ module stream_to_mem #( // Assertions // pragma translate_off -`ifndef ASSERTS_OFF +`ifndef COMMON_CELLS_ASSERTS_OFF if (BufDepth > 0) begin : gen_buf_asserts assert property (@(posedge clk_i) mem_resp_valid_i |-> buf_ready) else $error("Memory response lost!"); diff --git a/src/stream_xbar.sv b/src/stream_xbar.sv index 0013318d..33b3bbb5 100644 --- a/src/stream_xbar.sv +++ b/src/stream_xbar.sv @@ -165,7 +165,7 @@ module stream_xbar #( // Assertions // Make sure that the handshake and payload is stable // pragma translate_off - `ifndef ASSERTS_OFF + `ifndef COMMON_CELLS_ASSERTS_OFF `ifndef VERILATOR default disable iff (~rst_ni); `endif