From 292bd92614f14e8dfb42c39e52a00cebcc77922f Mon Sep 17 00:00:00 2001
From: Michael Platzer <michael.platzer@axelera.ai>
Date: Fri, 20 Oct 2023 10:44:16 +0200
Subject: [PATCH] Add newlines to avoid line length lint errors

---
 src/rr_arb_tree.sv      |  7 ++++---
 src/stream_omega_net.sv | 21 ++++++++++++++-------
 src/stream_xbar.sv      | 21 ++++++++++++++-------
 3 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/src/rr_arb_tree.sv b/src/rr_arb_tree.sv
index 31d51f11..e0d4f16f 100644
--- a/src/rr_arb_tree.sv
+++ b/src/rr_arb_tree.sv
@@ -173,15 +173,16 @@ module rr_arb_tree #(
         // pragma translate_off
         `ifndef COMMON_CELLS_ASSERTS_OFF
           lock: assert property(
-            @(posedge clk_i) disable iff (!rst_ni || flush_i) LockIn |-> req_o &&
-                             (!gnt_i && !flush_i) |=> idx_o == $past(idx_o)) else
+            @(posedge clk_i) disable iff (!rst_ni || flush_i)
+                LockIn |-> req_o && (!gnt_i && !flush_i) |=> idx_o == $past(idx_o)) else
                 $fatal (1, "Lock implies same arbiter decision in next cycle if output is not \
                             ready.");
 
           logic [NumIn-1:0] req_tmp;
           assign req_tmp = req_q & req_i;
           lock_req: assume property(
-            @(posedge clk_i) disable iff (!rst_ni || flush_i) LockIn |-> lock_d |=> req_tmp == req_q) else
+            @(posedge clk_i) disable iff (!rst_ni || flush_i)
+                LockIn |-> lock_d |=> req_tmp == req_q) else
                 $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is \
                             enabled.");
         `endif
diff --git a/src/stream_omega_net.sv b/src/stream_omega_net.sv
index fa75e5f7..79148f6b 100644
--- a/src/stream_omega_net.sv
+++ b/src/stream_omega_net.sv
@@ -266,25 +266,32 @@ module stream_omega_net #(
     default disable iff (~rst_ni);
     `endif
     for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_sel_assertions
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
           $fatal(1, "Non-existing output is selected!");
     end
 
     if (AxiVldRdy) begin : gen_handshake_assertions
       for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_inp_assertions
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
             $error("data_i is unstable at input: %0d", i);
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
             $error("sel_i is unstable at input: %0d", i);
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
             $error("valid_i at input %0d has been taken away without a ready.", i);
       end
       for (genvar i = 0; unsigned'(i) < NumOut; i++) begin : gen_out_assertions
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
             $error("data_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
             $error("idx_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni)
+            (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
             $error("valid_o at output %0d has been taken away without a ready.", i);
       end
     end
diff --git a/src/stream_xbar.sv b/src/stream_xbar.sv
index 33b3bbb5..167add5d 100644
--- a/src/stream_xbar.sv
+++ b/src/stream_xbar.sv
@@ -170,25 +170,32 @@ module stream_xbar #(
   default disable iff (~rst_ni);
   `endif
   for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_sel_assertions
-    assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
+    assert property (@(posedge clk_i) disable iff (~rst_ni)
+        (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
         $fatal(1, "Non-existing output is selected!");
   end
 
   if (AxiVldRdy) begin : gen_handshake_assertions
     for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_inp_assertions
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
           $error("data_i is unstable at input: %0d", i);
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
           $error("sel_i is unstable at input: %0d", i);
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
           $error("valid_i at input %0d has been taken away without a ready.", i);
     end
     for (genvar i = 0; unsigned'(i) < NumOut; i++) begin : gen_out_assertions
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
           $error("data_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
           $error("idx_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni)
+          (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
           $error("valid_o at output %0d has been taken away without a ready.", i);
     end
   end