Add fusion-compiler script generator

CHANGELOG.md

@@ -6,6 +6,9 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) a
 
 ## Unreleased
 
+### Added
+- Derived fusion-compiler output targer from synopsys.
+
 ## 0.28.1 - 2024-02-22
 ### Added
 - Add `flist-plus` script format for file list with plusargs.

README.md

@@ -292,6 +292,7 @@ Individual commands may also set tool-specific targets:
 - `vcs`
 - `verilator`
 - `synopsys`
+- `fusion-compiler`
 - `riviera`
 - `genus`
 - `vivado`
@@ -300,6 +301,7 @@ Individual commands may also set vendor-specific targets:
 
 - `xilinx`
 - `synopsys`
+- `fusion-compiler`
 
 Individual commands may also set technology-specific targets:
 

src/cmd/script.rs

@@ -50,6 +50,7 @@ pub fn new() -> Command {
                     PossibleValue::new("vcs"),
                     PossibleValue::new("verilator"),
                     PossibleValue::new("synopsys"),
+                    PossibleValue::new("fusion-compiler"),
                     PossibleValue::new("formality"),
                     PossibleValue::new("riviera"),
                     PossibleValue::new("genus"),
@@ -221,6 +222,7 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
             "vcs" => vec!["vcs", "simulation"],
             "verilator" => vec!["verilator", "synthesis"],
             "synopsys" => vec!["synopsys", "synthesis"],
+            "fusion-compiler" => vec!["fusion-compiler", "synthesis"],
             "formality" => vec!["synopsys", "synthesis", "formality"],
             "riviera" => vec!["riviera", "simulation"],
             "genus" => vec!["genus", "synthesis"],
@@ -364,6 +366,13 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
             targets,
             srcs,
         ),
+        "fusion-compiler" => emit_template(
+            sess,
+            include_str!("../script_fmt/fusion_compiler.tera"),
+            matches,
+            targets,
+            srcs,
+        ),
         "formality" => emit_template(
             sess,
             include_str!("../script_fmt/formality_tcl.tera"),

src/script_fmt/fusion_compiler.tera

@@ -0,0 +1,49 @@
+# {{HEADER_AUTOGEN}}
+set search_path_initial $search_path
+{% if compilation_mode == 'separate' %}{#                                                                           Individual block for each source file group
+#}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}{#                                                                                 Add group's include directories
+#}lappend search_path "{{ incdir }}"
+{% endfor %}
+{% if abort_on_error %}if {0 == [{% endif %}{#                                                                      Catch errors immediately
+#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{#    Analyze command for SystemVerilog or VHDL #}
+    {% for define in group.defines %}{#                                                                             Add group's defines
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{#                                                                                 Add group's files
+#}{{ '    ' }}"{{ file  }}" \
+    {% endfor %}]
+{% if abort_on_error %}]} {return 1}{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{#                                                                      Common block for all files
+#}{% for file in all_verilog %}{#                                                                                   Loop over verilog files
+#}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}{#                                                                                   Add all include directories
+#}lappend search_path "{{ incdir }}"
+{% endfor %}
+{% if abort_on_error %}if {0 == [{% endif %}{#                                                                      Catch errors immediately
+#}analyze -format sv \{#                                                                                            Analyze command for SystemVerilog #}
+    {% for define in all_defines %}{#                                                                               Add all defines
+}
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file }}" \{#                                        Add all verilog files #}
+    {% if loop.last %}]
+{% if abort_on_error %}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{#                                                                     Loop over all VHDL files
+#}{% if abort_on_error %}if {0 == [{% endif %}{#                                                                    Catch errors immediately
+#}analyze -format vhdl \{#                                                                                          Analyze command for VHDL #}
+    [list \
+    {% endif %}{{ '    ' }}"{{ file }}" \{#                                        Add all VHDL files #}
+    {% if loop.last %}]
+{% if abort_on_error %}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial