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This issue is similar to #355. When Ara receives a misaligned store instruction, addrgen clears the instruction but fails to communicate this information to vstu. As a result, vstu may reference some information from the previous instruction when executing the next instruction, leading to a bug.
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The text was updated successfully, but these errors were encountered:
Issue
This issue is similar to #355. When Ara receives a misaligned store instruction, addrgen clears the instruction but fails to communicate this information to vstu. As a result, vstu may reference some information from the previous instruction when executing the next instruction, leading to a bug.
Supplementary Pictures
The text was updated successfully, but these errors were encountered: