.gitlab-ci.yml

# Copyright 2020 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#    http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# Author: Paul Scheffler, ETH Zurich
#         Matheus Cavalcante, ETH Zurich

variables:
  GIT_SUBMODULE_STRATEGY: none
  RUST_LOG: 'memora=debug'
  VERILATOR_ROOT: '$CI_PROJECT_DIR/install/verilator'
  QUESTASIM_HOME: '/usr/pack/questa-2020.1-kgf/questasim'
  PATH: '/home/gitlabci/.cargo/bin:/usr/local/bin:/usr/bin:/usr/sbin:/sbin:/usr/local/condor/bin:/usr/sepp/bin:$VERILATOR_ROOT/bin'
  OBJCACHE: ''

workflow:
  rules:
    - if: $CI_MERGE_REQUEST_ID
    - if: $CI_COMMIT_TAG
    - if: $CI_COMMIT_REF_NAME

before_script:
  - env
  - git submodule sync --recursive
  - git submodule foreach --recursive git reset --hard

after_script:
  - env

stages:
  - linting
  - toolchain
  - compile
  - simulate

###################
#  Linting stage  #
###################

check-license:
  stage: linting
  script:
    - python3.6 scripts/licence-checker.py --config scripts/licence-checker.hjson hardware

#####################
#  Toolchain stage  #
#####################

tc-llvm:
  stage: toolchain
  script:
    - |
      if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh lookup tc-llvm; then
        git submodule update --init --recursive -- toolchain/riscv-llvm
        git submodule update --init --recursive -- toolchain/newlib
        mkdir -p /usr/scratch2/dolent1/gitlabci/buildcache/ara
        make toolchain-llvm
        $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert tc-llvm
      fi

tc-gcc:
  stage: toolchain
  script:
    - |
      if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh lookup tc-gcc; then
        git submodule update --init --recursive -- toolchain/riscv-gnu-toolchain
        mkdir -p /usr/scratch2/dolent1/gitlabci/buildcache/ara
        make toolchain-gcc
        $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert tc-gcc
      fi

tc-isa-sim:
  stage: toolchain
  script:
    - |
      if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh lookup tc-isa-sim; then
        git submodule update --init --recursive -- toolchain/riscv-isa-sim
        git submodule foreach --recursive git reset --hard
        mkdir -p /usr/scratch2/dolent1/gitlabci/buildcache/ara
        make riscv-isa-sim
        $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert tc-isa-sim
      fi

tc-verilator:
  stage: toolchain
  script:
    - |
      if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh lookup tc-verilator; then
        export CCACHE_DIR=$CI_PROJECT_DIR/.ccache
        git submodule update --init --recursive -- toolchain/verilator
        mkdir -p /usr/scratch2/dolent1/gitlabci/buildcache/ara
        make verilator
        $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert tc-verilator
      fi

###################
#  Compile stage  #
###################

compile_apps:
  stage: compile
  script:
    - git submodule update --init --recursive -- toolchain/riscv-isa-sim
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-llvm
    - make -C apps
  artifacts:
    paths:
      - apps/bin
  needs: ["tc-llvm"]

compile_riscv_tests:
  stage: compile
  script:
    - git submodule update --init --recursive -- toolchain/riscv-isa-sim
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-llvm
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-gcc
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - make -C apps riscv_tests
  artifacts:
    paths:
      - apps/bin
  needs: ["tc-llvm", "tc-gcc", "tc-isa-sim"]

compile_ara:
  stage: compile
  script:
    # Download Verilator and add missing links
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-verilator
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include
    - ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
    - git submodule update --init --recursive -- hardware
    - make -C hardware apply-patches
    - make -C hardware verilate
  artifacts:
    paths:
      - hardware/build/verilator
      - hardware/bender
  needs: ["tc-verilator", "tc-isa-sim"]

####################
#  Simulate stage  #
####################

hello_world:
  stage: simulate
  script:
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-verilator
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - git submodule update --init --recursive -- hardware
    - make -C hardware apply-patches
    # Run this test on Questa
    - make -C hardware app=${CI_JOB_NAME} simc
  artifacts:
    paths:
      - hardware/build/trace_hart_*.log
      - hardware/build/transcript
  needs: ["tc-llvm", "tc-verilator", "tc-isa-sim", "compile_apps"]
  dependencies:
    - tc-llvm
    - tc-verilator
    - tc-isa-sim
    - compile_apps

imatmul:
  stage: simulate
  script:
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - make -C hardware app=${CI_JOB_NAME} simv
  needs: ["tc-llvm", "tc-isa-sim", "compile_apps", "compile_ara"]
  dependencies:
    - tc-llvm
    - tc-isa-sim
    - compile_apps
    - compile_ara

fmatmul:
  stage: simulate
  script:
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - make -C hardware app=${CI_JOB_NAME} simv
  needs: ["tc-llvm", "tc-isa-sim", "compile_apps", "compile_ara"]
  dependencies:
    - tc-llvm
    - tc-isa-sim
    - compile_apps
    - compile_ara

riscv_tests_simv:
  stage: simulate
  script:
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - make -C hardware -j4 riscv_tests_simv
  needs: ["tc-llvm", "tc-isa-sim", "compile_riscv_tests", "compile_ara"]
  dependencies:
    - tc-llvm
    - tc-isa-sim
    - compile_riscv_tests
    - compile_ara
  artifacts:
    paths:
      - hardware/build/*.trace

riscv_tests_spike:
  stage: simulate
  script:
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-llvm
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-gcc
    - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get tc-isa-sim
    - make -C apps/riscv-tests/isa clean
    - make -C apps riscv_tests_spike
  artifacts:
    paths:
      - apps/riscv-tests/isa/*.dump
      - apps/riscv-tests/isa/*.out32
  needs: ["tc-isa-sim", "tc-llvm", "tc-gcc", "compile_riscv_tests"]
  dependencies:
    - tc-isa-sim
    - tc-llvm
    - tc-gcc
    - compile_riscv_tests