Merge pull request #11 from projf/oserdes-async-enhancements

Oserdes async enhancements

Author: WillGreen

README.md

@@ -60,10 +60,11 @@ The [demo](hdl/demo) directory includes a demo for each supported interface:
 
 You can find the list of required modules for each demo in a comment at the top of its file. You'll also need suitable constraints, such as those from the Project F [hardware support](https://github.com/projf/hardware-support) repo.
 
-There are also two test cards that the demo modules can use:
+There are also three test cards that the demo modules can use:
 
-* **[Test Card](hdl/demo/test_card.v)** - generates a video test card based on provided resolution
-* **[Test Card Simple](hdl/demo/test_card_simple.v)** - generates a simple coloured border based on provided resolution
+* **[Test Card Simple](hdl/demo/test_card_simple.v)** - simple coloured border (1-bit per colour and two shades of grey)
+* **[Test Card Squares](hdl/demo/test_card_squares.v)** - squares and lines of different colours (1-bit per colour)
+* **[Test Card Gradient](hdl/demo/test_card_gradient.v)** - colour gradient (8-bit per colour)
 
 You can adjust the demo resolution by changing the parameters for `display_clocks`, `display_timings`, and `test_card` or `test_card_simple`. Comments in the demos provide settings for tested [resolutions](#display-resolution-support).
 
@@ -122,7 +123,7 @@ The following table shows utilization of the display-controller with the gradien
                        Artix-7
     Interface        LUT     FF
     -----------------------------
-    DVI on FPGA      278      78
+    DVI on FPGA      278      86
     DVI BML 3-bit     49      32
     DVI BML 24-bit   TBC     TBC
     VGA 12-bit        67      32

hdl/demo/test_card_simple.v

@@ -25,7 +25,7 @@ module test_card_simple #(H_RES=640) (
     wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
 
     // Colour Output
-    assign o_red    = {8{b0 | b1 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
-    assign o_green  = {8{b1 | b2 | b3}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
-    assign o_blue   = {8{b3 | b4 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
+    assign o_red    = {8{b0 | b1 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
+    assign o_green  = {8{b1 | b2 | b3}} + {2'b0,{6{b6}}} + {b7, 7'b0};
+    assign o_blue   = {8{b3 | b4 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
 endmodule

hdl/serializer_10to1.v

@@ -15,15 +15,19 @@ module serializer_10to1(
 
     // asynchronous reset
     reg rst_oserdes;            // oserdes reset (active high)
-    reg [2:0] rst_shf;          // reset shift reg
+    (* ASYNC_REG = "TRUE" *) reg [1:0] rst_shf;  // reset shift reg
+
+    initial rst_oserdes = 1'b1; // start of with reset asserted
+    initial rst_shf = 2'b11;    //  and reset shift reg populated
 
     always @(posedge i_clk or posedge i_rst)
     if (i_rst)
-        {rst_oserdes, rst_shf} <= 4'b1111;
+        {rst_oserdes, rst_shf} <= 3'b111;
     else
         {rst_oserdes, rst_shf} <= {rst_shf, 1'b0};
 
-    wire shift1, shift2;  // wires between oserdes
+    // use two OSERDES2 to serialize 10-bit TMDS data
+    wire shift1, shift2;  // wires between oserdes master and slave
 
     OSERDESE2 #(
         .DATA_RATE_OQ("DDR"),   // DDR, SDR

hdl/test/serializer_10to1_tb.v

@@ -26,17 +26,39 @@ module serializer_10to1_tb();
         rst <= 0;
         clk_lock <= 0;
 
-        #2
-        rst <= 1;  // assert async
+        #1.5
+        rst <= 1;  // assert reset async
 
-        #18
+        #18.5
         rst <= 0;
 
         #20
-        clk_lock <=1;
+        clk_lock <= 1;
         tmds_data_1 <= 10'b0110100110;
         tmds_data_2 <= 10'b1001011001;
         tmds_data_3 <= 10'b1100000010;
+
+        #100
+        tmds_data_1 <= 10'b1111111111;
+        tmds_data_2 <= 10'b1010101010;
+        tmds_data_3 <= 10'b0000000000;
+
+        #2
+        clk_lock <= 0;  // simulate loss of clock lock
+
+        #23
+        clk_lock <= 1;
+
+        #125
+        tmds_data_1 <= 10'b0110100110;
+        tmds_data_2 <= 10'b1001011001;
+        tmds_data_3 <= 10'b1100000010;
+
+        #101.25
+        rst <= 1;  // assert reset async
+
+        #11.5
+        rst <= 0;  // de-assert reset async
     end
 
     serializer_10to1 serialize_data_1 (