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GCC: xtensa: backport patches from upstream
this PR supersedes earlephilhower#19, earlephilhower#20, earlephilhower#21 and earlephilhower#25, by backporting from upstream: 06ff8708f0b834cf1b35afa46113c6c973905cad "gcc: xtensa: fix PR target/98285" 64a54505ec8249178b9767d1420354f8eb55de50 "gcc: xtensa: rearrange DI mode constant loading" 40bf68bbe0bdba305fde4ab825a06c085ba486fc "gcc: xtensa: add optimizations for shift operations" 18e86fae2a14f78e70aae06afce6bb9853068bb1 "gcc: xtensa: implement bswapsi2, bswapdi2 and helpers"
1 parent e6a192b commit 064b1f2

12 files changed

+814
-246
lines changed

‎patches/gcc10.1/gcc-repair-TARGET_ADDX.patch

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This file was deleted.

‎patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch

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This file was deleted.

‎patches/gcc10.1/gcc-improve-shift-operations.patch renamed to ‎patches/gcc10.1/gcc-xtensa-add-optimizations-for-shift-operations.patch

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@@ -1,8 +1,26 @@
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From 40bf68bbe0bdba305fde4ab825a06c085ba486fc Mon Sep 17 00:00:00 2001
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From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
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Date: Wed, 16 Dec 2020 12:53:56 -0800
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Subject: [PATCH] gcc: xtensa: add optimizations for shift operations
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2020-12-16 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
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gcc/
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* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
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(*lshrsi3_3x): New patterns.
10+
11+
gcc/testsuite/
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* gcc.target/xtensa/shifts.c: New test.
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---
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gcc/config/xtensa/xtensa.md | 43 ++++++++++++++++++++++++
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gcc/testsuite/gcc.target/xtensa/shifts.c | 31 +++++++++++++++++
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2 files changed, 74 insertions(+)
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create mode 100644 gcc/testsuite/gcc.target/xtensa/shifts.c
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119
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
2-
index 21d60ffa..e82c466d 100644
20+
index 5fbe4ad4af9f..462a7244a35d 100644
321
--- a/gcc/config/xtensa/xtensa.md
422
+++ b/gcc/config/xtensa/xtensa.md
5-
@@ -1050,6 +1050,16 @@
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@@ -1071,6 +1071,16 @@
624
operands[1] = xtensa_copy_incoming_a7 (operands[1]);
725
})
826

@@ -19,7 +37,7 @@ index 21d60ffa..e82c466d 100644
1937
(define_insn "ashlsi3_internal"
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[(set (match_operand:SI 0 "register_operand" "=a,a")
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(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
22-
@@ -1062,6 +1072,17 @@
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@@ -1083,6 +1093,17 @@
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(set_attr "mode" "SI")
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(set_attr "length" "3,6")])
2543

@@ -37,7 +55,7 @@ index 21d60ffa..e82c466d 100644
3755
(define_insn "ashrsi3"
3856
[(set (match_operand:SI 0 "register_operand" "=a,a")
3957
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
40-
@@ -1074,6 +1095,17 @@
58+
@@ -1095,6 +1116,17 @@
4159
(set_attr "mode" "SI")
4260
(set_attr "length" "3,6")])
4361

@@ -55,7 +73,7 @@ index 21d60ffa..e82c466d 100644
5573
(define_insn "lshrsi3"
5674
[(set (match_operand:SI 0 "register_operand" "=a,a")
5775
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
58-
@@ -1093,6 +1125,17 @@
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@@ -1114,6 +1146,17 @@
5977
(set_attr "mode" "SI")
6078
(set_attr "length" "3,6")])
6179

@@ -73,3 +91,40 @@ index 21d60ffa..e82c466d 100644
7391
(define_insn "rotlsi3"
7492
[(set (match_operand:SI 0 "register_operand" "=a,a")
7593
(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
94+
diff --git a/gcc/testsuite/gcc.target/xtensa/shifts.c b/gcc/testsuite/gcc.target/xtensa/shifts.c
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new file mode 100644
96+
index 000000000000..8d7e4a928d3a
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/xtensa/shifts.c
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@@ -0,0 +1,31 @@
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+/* { dg-do compile } */
101+
+/* { dg-options "-O1" } */
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+
103+
+int lshift1(int v)
104+
+{
105+
+ return v << 1;
106+
+}
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+
108+
+int lshift2(int v, int s)
109+
+{
110+
+ return v << (s * 8);
111+
+}
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+
113+
+unsigned int lshift3(unsigned int v, int s)
114+
+{
115+
+ return v << (s * 8);
116+
+}
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+
118+
+int rshift1(int v, int s)
119+
+{
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+ return v >> (s * 8);
121+
+}
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+
123+
+unsigned int rshift2(unsigned int v, int s)
124+
+{
125+
+ return v >> (s * 8);
126+
+}
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+
128+
+/* { dg-final { scan-assembler-not "slli" } } */
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+/* { dg-final { scan-assembler-times "ssa8l" 2 } } */
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+/* { dg-final { scan-assembler-times "ssa8b" 2 } } */

‎patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch

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From 06ff8708f0b834cf1b35afa46113c6c973905cad Mon Sep 17 00:00:00 2001
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From: Max Filippov <jcmvbkbc@gmail.com>
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Date: Sat, 12 Dec 2020 12:14:40 -0800
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Subject: [PATCH] gcc: xtensa: fix PR target/98285
5+
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2020-12-14 Max Filippov <jcmvbkbc@gmail.com>
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gcc/
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* config/xtensa/predicates.md (addsubx_operand): Change accepted
9+
values from 2/4/8 to 1..3.
10+
* config/xtensa/xtensa.md (*addx, *subx): Change RTL pattern
11+
to use 'ashift' instead of 'mult'. Update operands[3] value.
12+
13+
gcc/testsuite/
14+
* gcc.target/xtensa/pr98285.c: New test.
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---
16+
gcc/config/xtensa/predicates.md | 5 +--
17+
gcc/config/xtensa/xtensa.md | 18 +++++---
18+
gcc/testsuite/gcc.target/xtensa/pr98285.c | 54 +++++++++++++++++++++++
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3 files changed, 68 insertions(+), 9 deletions(-)
20+
create mode 100644 gcc/testsuite/gcc.target/xtensa/pr98285.c
21+
22+
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
23+
index 1721640dc79e..eb52b05aafad 100644
24+
--- a/gcc/config/xtensa/predicates.md
25+
+++ b/gcc/config/xtensa/predicates.md
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@@ -25,9 +25,8 @@
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(define_predicate "addsubx_operand"
29+
(and (match_code "const_int")
30+
- (match_test "INTVAL (op) == 2
31+
- || INTVAL (op) == 4
32+
- || INTVAL (op) == 8")))
33+
+ (match_test "INTVAL (op) >= 1
34+
+ && INTVAL (op) <= 3")))
35+
36+
(define_predicate "arith_operand"
37+
(ior (and (match_code "const_int")
38+
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
39+
index 749fe477d562..671c4bea144f 100644
40+
--- a/gcc/config/xtensa/xtensa.md
41+
+++ b/gcc/config/xtensa/xtensa.md
42+
@@ -162,11 +162,14 @@
43+
44+
(define_insn "*addx"
45+
[(set (match_operand:SI 0 "register_operand" "=a")
46+
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
47+
- (match_operand:SI 3 "addsubx_operand" "i"))
48+
+ (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
49+
+ (match_operand:SI 3 "addsubx_operand" "i"))
50+
(match_operand:SI 2 "register_operand" "r")))]
51+
"TARGET_ADDX"
52+
- "addx%3\t%0, %1, %2"
53+
+{
54+
+ operands[3] = GEN_INT (1 << INTVAL (operands[3]));
55+
+ return "addx%3\t%0, %1, %2";
56+
+}
57+
[(set_attr "type" "arith")
58+
(set_attr "mode" "SI")
59+
(set_attr "length" "3")])
60+
@@ -196,11 +199,14 @@
61+
62+
(define_insn "*subx"
63+
[(set (match_operand:SI 0 "register_operand" "=a")
64+
- (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
65+
- (match_operand:SI 3 "addsubx_operand" "i"))
66+
+ (minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
67+
+ (match_operand:SI 3 "addsubx_operand" "i"))
68+
(match_operand:SI 2 "register_operand" "r")))]
69+
"TARGET_ADDX"
70+
- "subx%3\t%0, %1, %2"
71+
+{
72+
+ operands[3] = GEN_INT (1 << INTVAL (operands[3]));
73+
+ return "subx%3\t%0, %1, %2";
74+
+}
75+
[(set_attr "type" "arith")
76+
(set_attr "mode" "SI")
77+
(set_attr "length" "3")])
78+
diff --git a/gcc/testsuite/gcc.target/xtensa/pr98285.c b/gcc/testsuite/gcc.target/xtensa/pr98285.c
79+
new file mode 100644
80+
index 000000000000..2c037d546565
81+
--- /dev/null
82+
+++ b/gcc/testsuite/gcc.target/xtensa/pr98285.c
83+
@@ -0,0 +1,54 @@
84+
+/* { dg-do compile } */
85+
+/* { dg-options "-O2" } */
86+
+
87+
+int mul3(int v)
88+
+{
89+
+ return v * 3;
90+
+}
91+
+
92+
+int mul5(int v)
93+
+{
94+
+ return v * 5;
95+
+}
96+
+
97+
+int mul7(int v)
98+
+{
99+
+ return v * 7;
100+
+}
101+
+
102+
+int mul9(int v)
103+
+{
104+
+ return v * 9;
105+
+}
106+
+
107+
+int mul2sub(int a, int b)
108+
+{
109+
+ return a * 2 - b;
110+
+}
111+
+
112+
+int mul4sub(int a, int b)
113+
+{
114+
+ return a * 4 - b;
115+
+}
116+
+
117+
+short index2(short *p, int i)
118+
+{
119+
+ return p[i];
120+
+}
121+
+
122+
+int index4(int *p, int i)
123+
+{
124+
+ return p[i];
125+
+}
126+
+
127+
+long long index8(long long *p, int i)
128+
+{
129+
+ return p[i];
130+
+}
131+
+
132+
+/* { dg-final { scan-assembler-times "addx2" 2 } } */
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+/* { dg-final { scan-assembler-times "addx4" 2 } } */
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+/* { dg-final { scan-assembler-times "addx8" 2 } } */
135+
+/* { dg-final { scan-assembler-times "subx2" 1 } } */
136+
+/* { dg-final { scan-assembler-times "subx4" 1 } } */
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+/* { dg-final { scan-assembler-times "subx8" 1 } } */

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