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lines changed Original file line number Diff line number Diff line change @@ -27,7 +27,6 @@ genVHDL m = imports $$
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imports = vcat $ [
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text " library IEEE" <> semi,
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text " use IEEE.STD_LOGIC_1164.ALL" <> semi,
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- text " use IEEE.STD_LOGIC_UNSIGNED.ALL" <> semi,
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text " use IEEE.NUMERIC_STD.ALL" <> semi,
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text " use work.all" <> semi
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]
@@ -129,7 +128,7 @@ inst gensym (InitProcessDecl s) = Just $
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where senlist = parens empty
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-- TODO: get multline working
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- inst _ (CommentDecl msg) = Just $
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+ inst _ (CommentDecl msg) = Just $
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(vcat [ text " --" <+> text m | m <- lines msg ])
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inst _ d = Nothing
@@ -172,7 +171,7 @@ stmt (Case d ps def) =
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expr (ExprNum i) = int $ fromIntegral i
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expr (ExprBit x) = quotes (int x)
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-- expr (ExprLit 1 val) = quotes (integer val) -- AJG: 1 element arrays are still arrays.
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- expr (ExprLit size val) = doubleQuotes
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+ expr (ExprLit size val) = doubleQuotes
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$ text
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$ map (\ x -> if x then ' 1' else ' 0' )
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$ map odd
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