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[DAGCombiner] Fold vector subtraction if above threshold to umin
This extends llvm#134235 to vectors.
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2 files changed

+36
-34
lines changed

2 files changed

+36
-34
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4093,6 +4093,26 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
40934093
return N0;
40944094
}
40954095

4096+
// (sub x, ([v]select (ult x, y), 0, y)) -> (umin x, (sub x, y))
4097+
// (sub x, ([v]select (uge x, y), y, 0)) -> (umin x, (sub x, y))
4098+
if (N1.hasOneUse() && hasUMin(VT)) {
4099+
SDValue Y;
4100+
if (sd_match(N1, m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4101+
m_SpecificCondCode(ISD::SETULT)),
4102+
m_Zero(), m_Deferred(Y))) ||
4103+
sd_match(N1, m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4104+
m_SpecificCondCode(ISD::SETUGE)),
4105+
m_Deferred(Y), m_Zero())) ||
4106+
sd_match(N1, m_VSelect(m_SetCC(m_Specific(N0), m_Value(Y),
4107+
m_SpecificCondCode(ISD::SETULT)),
4108+
m_Zero(), m_Deferred(Y))) ||
4109+
sd_match(N1, m_VSelect(m_SetCC(m_Specific(N0), m_Value(Y),
4110+
m_SpecificCondCode(ISD::SETUGE)),
4111+
m_Deferred(Y), m_Zero())))
4112+
return DAG.getNode(ISD::UMIN, DL, VT, N0,
4113+
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
4114+
}
4115+
40964116
if (SDValue NewSel = foldBinOpIntoSelect(N))
40974117
return NewSel;
40984118

@@ -4442,20 +4462,6 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
44424462
sd_match(N1, m_UMaxLike(m_Specific(A), m_Specific(B))))
44434463
return DAG.getNegative(DAG.getNode(ISD::ABDU, DL, VT, A, B), DL, VT);
44444464

4445-
// (sub x, (select (ult x, y), 0, y)) -> (umin x, (sub x, y))
4446-
// (sub x, (select (uge x, y), y, 0)) -> (umin x, (sub x, y))
4447-
if (hasUMin(VT)) {
4448-
SDValue Y;
4449-
if (sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4450-
m_SpecificCondCode(ISD::SETULT)),
4451-
m_Zero(), m_Deferred(Y)))) ||
4452-
sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4453-
m_SpecificCondCode(ISD::SETUGE)),
4454-
m_Deferred(Y), m_Zero()))))
4455-
return DAG.getNode(ISD::UMIN, DL, VT, N0,
4456-
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
4457-
}
4458-
44594465
return SDValue();
44604466
}
44614467

‎llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll‎

Lines changed: 16 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -898,9 +898,8 @@ define <vscale x 2 x i8> @vsub_if_uge_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2
898898
; CHECK-LABEL: vsub_if_uge_nxv2i8:
899899
; CHECK: # %bb.0:
900900
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
901-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
902901
; CHECK-NEXT: vsub.vv v9, v8, v9
903-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
902+
; CHECK-NEXT: vminu.vv v8, v8, v9
904903
; CHECK-NEXT: ret
905904
%cmp = icmp ult <vscale x 2 x i8> %va, %vb
906905
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %vb
@@ -911,9 +910,9 @@ define <vscale x 2 x i8> @vsub_if_uge_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2
911910
define <vscale x 2 x i8> @vsub_if_uge_swapped_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
912911
; CHECK-LABEL: vsub_if_uge_swapped_nxv2i8:
913912
; CHECK: # %bb.0:
914-
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
915-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
916-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
913+
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
914+
; CHECK-NEXT: vsub.vv v9, v8, v9
915+
; CHECK-NEXT: vminu.vv v8, v8, v9
917916
; CHECK-NEXT: ret
918917
%cmp = icmp uge <vscale x 2 x i8> %va, %vb
919918
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %vb, <vscale x 2 x i8> zeroinitializer
@@ -925,9 +924,8 @@ define <vscale x 2 x i16> @vsub_if_uge_nxv2i16(<vscale x 2 x i16> %va, <vscale x
925924
; CHECK-LABEL: vsub_if_uge_nxv2i16:
926925
; CHECK: # %bb.0:
927926
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
928-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
929927
; CHECK-NEXT: vsub.vv v9, v8, v9
930-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
928+
; CHECK-NEXT: vminu.vv v8, v8, v9
931929
; CHECK-NEXT: ret
932930
%cmp = icmp ult <vscale x 2 x i16> %va, %vb
933931
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %vb
@@ -938,9 +936,9 @@ define <vscale x 2 x i16> @vsub_if_uge_nxv2i16(<vscale x 2 x i16> %va, <vscale x
938936
define <vscale x 2 x i16> @vsub_if_uge_swapped_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
939937
; CHECK-LABEL: vsub_if_uge_swapped_nxv2i16:
940938
; CHECK: # %bb.0:
941-
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
942-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
943-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
939+
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
940+
; CHECK-NEXT: vsub.vv v9, v8, v9
941+
; CHECK-NEXT: vminu.vv v8, v8, v9
944942
; CHECK-NEXT: ret
945943
%cmp = icmp uge <vscale x 2 x i16> %va, %vb
946944
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %vb, <vscale x 2 x i16> zeroinitializer
@@ -952,9 +950,8 @@ define <vscale x 2 x i32> @vsub_if_uge_nxv2i32(<vscale x 2 x i32> %va, <vscale x
952950
; CHECK-LABEL: vsub_if_uge_nxv2i32:
953951
; CHECK: # %bb.0:
954952
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
955-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
956953
; CHECK-NEXT: vsub.vv v9, v8, v9
957-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
954+
; CHECK-NEXT: vminu.vv v8, v8, v9
958955
; CHECK-NEXT: ret
959956
%cmp = icmp ult <vscale x 2 x i32> %va, %vb
960957
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %vb
@@ -965,9 +962,9 @@ define <vscale x 2 x i32> @vsub_if_uge_nxv2i32(<vscale x 2 x i32> %va, <vscale x
965962
define <vscale x 2 x i32> @vsub_if_uge_swapped_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
966963
; CHECK-LABEL: vsub_if_uge_swapped_nxv2i32:
967964
; CHECK: # %bb.0:
968-
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
969-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
970-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
965+
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
966+
; CHECK-NEXT: vsub.vv v9, v8, v9
967+
; CHECK-NEXT: vminu.vv v8, v8, v9
971968
; CHECK-NEXT: ret
972969
%cmp = icmp uge <vscale x 2 x i32> %va, %vb
973970
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %vb, <vscale x 2 x i32> zeroinitializer
@@ -979,9 +976,8 @@ define <vscale x 2 x i64> @vsub_if_uge_nxv2i64(<vscale x 2 x i64> %va, <vscale x
979976
; CHECK-LABEL: vsub_if_uge_nxv2i64:
980977
; CHECK: # %bb.0:
981978
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
982-
; CHECK-NEXT: vmsltu.vv v0, v8, v10
983979
; CHECK-NEXT: vsub.vv v10, v8, v10
984-
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
980+
; CHECK-NEXT: vminu.vv v8, v8, v10
985981
; CHECK-NEXT: ret
986982
%cmp = icmp ult <vscale x 2 x i64> %va, %vb
987983
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %vb
@@ -992,9 +988,9 @@ define <vscale x 2 x i64> @vsub_if_uge_nxv2i64(<vscale x 2 x i64> %va, <vscale x
992988
define <vscale x 2 x i64> @vsub_if_uge_swapped_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
993989
; CHECK-LABEL: vsub_if_uge_swapped_nxv2i64:
994990
; CHECK: # %bb.0:
995-
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
996-
; CHECK-NEXT: vmsleu.vv v0, v10, v8
997-
; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t
991+
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
992+
; CHECK-NEXT: vsub.vv v10, v8, v10
993+
; CHECK-NEXT: vminu.vv v8, v8, v10
998994
; CHECK-NEXT: ret
999995
%cmp = icmp uge <vscale x 2 x i64> %va, %vb
1000996
%select = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %vb, <vscale x 2 x i64> zeroinitializer

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