diff --git a/drivers/gpio/gpio_andes_atcgpio100.c b/drivers/gpio/gpio_andes_atcgpio100.c
index f1c7875a0ac8..fd333b5a4d03 100644
--- a/drivers/gpio/gpio_andes_atcgpio100.c
+++ b/drivers/gpio/gpio_andes_atcgpio100.c
@@ -14,6 +14,7 @@
 #include <device.h>
 #include <soc.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/andestech-atcgpio100.h>
 #include <sys/util.h>
 #include <sys/sys_io.h>
 
@@ -140,7 +141,7 @@ static int gpio_atcgpio100_config(const struct device *port,
 		key = k_spin_lock(&data->lock);
 
 		/* Set de-bounce */
-		if (flags & GPIO_INT_DEBOUNCE) {
+		if (flags & ATCGPIO100_GPIO_DEBOUNCE) {
 			/* Default settings: Filter out pulses which are
 			 *  less than 4 de-bounce clock period
 			 */
diff --git a/drivers/gpio/gpio_b91.c b/drivers/gpio/gpio_b91.c
index 954424b83c5b..2eaab62658b7 100644
--- a/drivers/gpio/gpio_b91.c
+++ b/drivers/gpio/gpio_b91.c
@@ -324,11 +324,6 @@ static int gpio_b91_pin_configure(const struct device *dev,
 		return -ENOTSUP;
 	}
 
-	/* Strengths not implemented */
-	if ((flags & GPIO_DS_ALT) != 0) {
-		return -ENOTSUP;
-	}
-
 	/* Set GPIO init state if defined to avoid glitches */
 	if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
 		gpio->output |= BIT(pin);
diff --git a/drivers/gpio/gpio_cc13xx_cc26xx.c b/drivers/gpio/gpio_cc13xx_cc26xx.c
index 6b8e7fb8c312..8897385671e5 100644
--- a/drivers/gpio/gpio_cc13xx_cc26xx.c
+++ b/drivers/gpio/gpio_cc13xx_cc26xx.c
@@ -11,6 +11,7 @@
 #include <device.h>
 #include <errno.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
 
 #include <driverlib/gpio.h>
 #include <driverlib/interrupt.h>
@@ -72,28 +73,21 @@ static int gpio_cc13xx_cc26xx_config(const struct device *port,
 
 	config |= IOC_SLEW_DISABLE | IOC_NO_WAKE_UP;
 
-	config |= (flags & GPIO_INT_DEBOUNCE) ? IOC_HYST_ENABLE :
-							IOC_HYST_DISABLE;
-
-	/*
-	 * The GPIO_DS_ALT_HIGH and GPIO_DS_ALT_LOW flags are for setting
-	 * the highest drive strength for a GPIO in the output HIGH and
-	 * output LOW states, respectively. Since only 1 drive strength
-	 * setting is available for a GPIO (irrespective of output state),
-	 * require both flags to be set for highest drive strength, default
-	 * to low/auto drive strength.
-	 * Not all GPIO support 8ma, but setting that bit will use the highest
-	 * supported drive strength.
-	 */
-	switch (flags & (GPIO_DS_ALT_HIGH | GPIO_DS_ALT_LOW)) {
-	case 0:
+	config |= (flags & CC13XX_CC26XX_GPIO_DEBOUNCE) ?
+		IOC_HYST_ENABLE : IOC_HYST_DISABLE;
+
+	switch (flags & CC13XX_CC26XX_GPIO_DS_MASK) {
+	case CC13XX_CC26XX_GPIO_DS_DFLT:
 		config |= IOC_CURRENT_2MA | IOC_STRENGTH_AUTO;
 		break;
-	case (GPIO_DS_ALT_HIGH | GPIO_DS_ALT_LOW):
+	case CC13XX_CC26XX_GPIO_DS_ALT:
+		/*
+		 * Not all GPIO support 8ma, but setting that bit will use the
+		 * highest supported drive strength.
+		 */
 		config |= IOC_CURRENT_8MA | IOC_STRENGTH_MAX;
 		break;
-	case GPIO_DS_ALT_HIGH:
-	case GPIO_DS_ALT_LOW:
+	default:
 		return -ENOTSUP;
 	}
 
diff --git a/drivers/gpio/gpio_cy8c95xx.c b/drivers/gpio/gpio_cy8c95xx.c
index 4fa3b5059116..4fe1ac743023 100644
--- a/drivers/gpio/gpio_cy8c95xx.c
+++ b/drivers/gpio/gpio_cy8c95xx.c
@@ -105,11 +105,6 @@ static int cy8c95xx_config(const struct device *dev,
 		return -EWOULDBLOCK;
 	}
 
-	/* Strengths not implemented */
-	if ((flags & GPIO_DS_ALT) != 0) {
-		return -ENOTSUP;
-	}
-
 	/* Open-drain not implemented */
 	if ((flags & GPIO_SINGLE_ENDED) != 0U) {
 		return -ENOTSUP;
diff --git a/drivers/gpio/gpio_dw.c b/drivers/gpio/gpio_dw.c
index 76c42376f644..d8e511083b0a 100644
--- a/drivers/gpio/gpio_dw.c
+++ b/drivers/gpio/gpio_dw.c
@@ -10,6 +10,7 @@
 
 #include <kernel.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/snps-designware-gpio.h>
 #include "gpio_dw.h"
 #include "gpio_utils.h"
 
@@ -301,7 +302,7 @@ static inline void dw_pin_config(const struct device *port,
 	 * interrupts according to datasheet.
 	 */
 	if (dw_interrupt_support(config) && (dir_port == SWPORTA_DDR)) {
-		need_debounce = (flags & GPIO_INT_DEBOUNCE);
+		need_debounce = (flags & DW_GPIO_DEBOUNCE);
 		dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, need_debounce);
 	}
 }
diff --git a/drivers/gpio/gpio_esp32.c b/drivers/gpio/gpio_esp32.c
index 5388ab6ea444..02856df95cf6 100644
--- a/drivers/gpio/gpio_esp32.c
+++ b/drivers/gpio/gpio_esp32.c
@@ -19,6 +19,7 @@
 #include <errno.h>
 #include <device.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/espressif-esp32-gpio.h>
 #ifdef CONFIG_SOC_ESP32C3
 #include <drivers/interrupt_controller/intc_esp32c3.h>
 #else
@@ -151,8 +152,8 @@ static int gpio_esp32_config(const struct device *dev,
 		 * to either low or high states. Alternative drive strength is weak-only,
 		 * while any other intermediary combination is considered invalid.
 		 */
-		switch (flags & GPIO_DS_MASK) {
-		case GPIO_DS_DFLT:
+		switch (flags & ESP32_GPIO_DS_MASK) {
+		case ESP32_GPIO_DS_DFLT:
 			if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
 				gpio_ll_set_drive_capability(cfg->gpio_base,
 						io_pin,
@@ -164,7 +165,7 @@ static int gpio_esp32_config(const struct device *dev,
 #endif
 			}
 			break;
-		case GPIO_DS_ALT:
+		case ESP32_GPIO_DS_ALT:
 			if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
 				gpio_ll_set_drive_capability(cfg->gpio_base,
 						io_pin,
diff --git a/drivers/gpio/gpio_fxl6408.c b/drivers/gpio/gpio_fxl6408.c
index 2e395bae9321..f9cf78aa4922 100644
--- a/drivers/gpio/gpio_fxl6408.c
+++ b/drivers/gpio/gpio_fxl6408.c
@@ -26,7 +26,7 @@ LOG_MODULE_REGISTER(fxl6408, CONFIG_FXL6408_LOG_LEVEL);
 
 #define SUPPORTED_FLAGS (GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW |\
 			GPIO_OUTPUT_INIT_HIGH | GPIO_PULL_DOWN | GPIO_PULL_UP |\
-			GPIO_ACTIVE_HIGH | GPIO_ACTIVE_LOW | GPIO_INT_DEBOUNCE)
+			GPIO_ACTIVE_HIGH | GPIO_ACTIVE_LOW)
 
 /** Configuration data*/
 struct gpio_fxl6408_config {
diff --git a/drivers/gpio/gpio_ite_it8xxx2.c b/drivers/gpio/gpio_ite_it8xxx2.c
index ea4165bd1033..b79d6205015c 100644
--- a/drivers/gpio/gpio_ite_it8xxx2.c
+++ b/drivers/gpio/gpio_ite_it8xxx2.c
@@ -7,6 +7,7 @@
 #include <errno.h>
 #include <device.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/ite-it8xxx2-gpio.h>
 #include <dt-bindings/interrupt-controller/ite-intc.h>
 #include <zephyr/types.h>
 #include <sys/util.h>
@@ -379,14 +380,14 @@ static int gpio_ite_configure(const struct device *dev,
 			gpio_1p8v[gpio_config->index][pin].offset);
 	mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
 	if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
-		gpio_flags_t volt = flags & GPIO_VOLTAGE_MASK;
+		gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
 
-		if (volt == GPIO_VOLTAGE_1P8) {
+		if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
 			__ASSERT(!(flags & GPIO_PULL_UP),
 			"Don't enable internal pullup if 1.8V voltage is used");
 			*reg_1p8v |= mask_1p8v;
-		} else if (volt == GPIO_VOLTAGE_3P3 ||
-			   volt == GPIO_VOLTAGE_DEFAULT) {
+		} else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3 ||
+			   volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
 			*reg_1p8v &= ~mask_1p8v;
 		} else {
 			return -EINVAL;
diff --git a/drivers/gpio/gpio_mcux.c b/drivers/gpio/gpio_mcux.c
index 6fd327ce2bdb..38b6410c3b88 100644
--- a/drivers/gpio/gpio_mcux.c
+++ b/drivers/gpio/gpio_mcux.c
@@ -10,6 +10,7 @@
 #include <errno.h>
 #include <device.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/nxp-kinetis-gpio.h>
 #include <soc.h>
 #include <fsl_common.h>
 #include <fsl_port.h>
@@ -98,12 +99,12 @@ static int gpio_mcux_configure(const struct device *dev,
 
 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
 	/* Determine the drive strength */
-	switch (flags & GPIO_DS_MASK) {
-	case GPIO_DS_DFLT:
+	switch (flags & KINETIS_GPIO_DS_MASK) {
+	case KINETIS_GPIO_DS_DFLT:
 		/* Default is low drive strength */
 		mask |= PORT_PCR_DSE_MASK;
 		break;
-	case GPIO_DS_ALT:
+	case KINETIS_GPIO_DS_ALT:
 		/* Alternate is high drive strength */
 		pcr |= PORT_PCR_DSE_MASK;
 		break;
diff --git a/drivers/gpio/gpio_nrfx.c b/drivers/gpio/gpio_nrfx.c
index 9c9aa7e9519d..d0251fcce9e7 100644
--- a/drivers/gpio/gpio_nrfx.c
+++ b/drivers/gpio/gpio_nrfx.c
@@ -8,6 +8,7 @@
 #include <nrfx_gpiote.h>
 #include <string.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/nordic-nrf-gpio.h>
 #include "gpio_utils.h"
 
 struct gpio_nrfx_data {
@@ -38,32 +39,32 @@ static int get_drive(gpio_flags_t flags, nrf_gpio_pin_drive_t *drive)
 {
 	int err = 0;
 
-	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
+	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
 			 GPIO_OPEN_DRAIN)) {
-	case GPIO_DS_DFLT:
+	case NRF_GPIO_DS_DFLT:
 		*drive = NRF_GPIO_PIN_S0S1;
 		break;
-	case GPIO_DS_DFLT_LOW | GPIO_DS_ALT_HIGH:
+	case NRF_GPIO_DS_DFLT_LOW | NRF_GPIO_DS_ALT_HIGH:
 		*drive = NRF_GPIO_PIN_S0H1;
 		break;
-	case GPIO_DS_DFLT_LOW | GPIO_OPEN_DRAIN:
+	case NRF_GPIO_DS_DFLT_LOW | GPIO_OPEN_DRAIN:
 		*drive = NRF_GPIO_PIN_S0D1;
 		break;
 
-	case GPIO_DS_ALT_LOW | GPIO_DS_DFLT_HIGH:
+	case NRF_GPIO_DS_ALT_LOW | NRF_GPIO_DS_DFLT_HIGH:
 		*drive = NRF_GPIO_PIN_H0S1;
 		break;
-	case GPIO_DS_ALT:
+	case NRF_GPIO_DS_ALT:
 		*drive = NRF_GPIO_PIN_H0H1;
 		break;
-	case GPIO_DS_ALT_LOW | GPIO_OPEN_DRAIN:
+	case NRF_GPIO_DS_ALT_LOW | GPIO_OPEN_DRAIN:
 		*drive = NRF_GPIO_PIN_H0D1;
 		break;
 
-	case GPIO_DS_DFLT_HIGH | GPIO_OPEN_SOURCE:
+	case NRF_GPIO_DS_DFLT_HIGH | GPIO_OPEN_SOURCE:
 		*drive = NRF_GPIO_PIN_D0S1;
 		break;
-	case GPIO_DS_ALT_HIGH | GPIO_OPEN_SOURCE:
+	case NRF_GPIO_DS_ALT_HIGH | GPIO_OPEN_SOURCE:
 		*drive = NRF_GPIO_PIN_D0H1;
 		break;
 
diff --git a/drivers/gpio/gpio_pca953x.c b/drivers/gpio/gpio_pca953x.c
index 611dd5f710cb..efc6ec7b2dfd 100644
--- a/drivers/gpio/gpio_pca953x.c
+++ b/drivers/gpio/gpio_pca953x.c
@@ -192,21 +192,6 @@ static int gpio_pca953x_config(const struct device *dev, gpio_pin_t pin,
 		return -EWOULDBLOCK;
 	}
 
-	/* Zephyr currently defines drive strength support based on
-	 * the behavior and capabilities of the Nordic GPIO
-	 * peripheral: strength defaults to low but can be set high,
-	 * and is controlled independently for output levels.
-	 *
-	 * The PCA953X supports only high strength, and does not
-	 * support different strengths for different levels.
-	 *
-	 * Until something more general is available reject any
-	 * attempt to set a non-default drive strength.
-	 */
-	if ((flags & GPIO_DS_ALT) != 0) {
-		return -ENOTSUP;
-	}
-
 	/* Single Ended lines (Open drain and open source) not supported */
 	if ((flags & GPIO_SINGLE_ENDED) != 0) {
 		return -ENOTSUP;
diff --git a/drivers/gpio/gpio_pcal6408a.c b/drivers/gpio/gpio_pcal6408a.c
index 9c0eac3b905b..8d74851f7f76 100644
--- a/drivers/gpio/gpio_pcal6408a.c
+++ b/drivers/gpio/gpio_pcal6408a.c
@@ -139,13 +139,6 @@ static int pcal6408a_pin_configure(const struct device *dev,
 		return -ENOTSUP;
 	}
 
-	/* Drive strength configuration in this device is incompatible with
-	 * the currently available GPIO API flags, hence it is not supported.
-	 */
-	if ((flags & GPIO_DS_ALT) != 0) {
-		return -ENOTSUP;
-	}
-
 	if (k_is_in_isr()) {
 		return -EWOULDBLOCK;
 	}
diff --git a/drivers/gpio/gpio_sam.c b/drivers/gpio/gpio_sam.c
index c083f3c202a1..f50c53c58d14 100644
--- a/drivers/gpio/gpio_sam.c
+++ b/drivers/gpio/gpio_sam.c
@@ -12,6 +12,7 @@
 #include <init.h>
 #include <soc.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/atmel-sam-gpio.h>
 
 #include "gpio_utils.h"
 
@@ -116,7 +117,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 
 #if defined(CONFIG_SOC_SERIES_SAM3X)
 	/* Setup debounce. */
-	if (flags & GPIO_INT_DEBOUNCE) {
+	if (flags & SAM_GPIO_DEBOUNCE) {
 		pio->PIO_DIFSR = mask;
 	} else {
 		pio->PIO_SCIFSR = mask;
@@ -127,7 +128,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 	defined(CONFIG_SOC_SERIES_SAMV71)
 
 	/* Setup debounce. */
-	if (flags & GPIO_INT_DEBOUNCE) {
+	if (flags & SAM_GPIO_DEBOUNCE) {
 		pio->PIO_IFSCER = mask;
 	} else {
 		pio->PIO_IFSCDR = mask;
diff --git a/drivers/gpio/gpio_sam0.c b/drivers/gpio/gpio_sam0.c
index 2dfedde6af84..7e9a06f4869c 100644
--- a/drivers/gpio/gpio_sam0.c
+++ b/drivers/gpio/gpio_sam0.c
@@ -10,6 +10,7 @@
 #include <errno.h>
 #include <device.h>
 #include <drivers/gpio.h>
+#include <dt-bindings/gpio/atmel-sam0-gpio.h>
 #include <soc.h>
 #include <drivers/interrupt_controller/sam0_eic.h>
 
@@ -94,7 +95,7 @@ static int gpio_sam0_config(const struct device *dev, gpio_pin_t pin,
 
 	/* Preserve debounce flag for interrupt configuration. */
 	WRITE_BIT(data->debounce, pin,
-		  ((flags & GPIO_INT_DEBOUNCE) != 0)
+		  ((flags & SAM0_GPIO_DEBOUNCE) != 0)
 		  && (pincfg.bit.INEN != 0));
 
 	/* Write the now-built pin configuration */
diff --git a/drivers/gpio/gpio_sx1509b.c b/drivers/gpio/gpio_sx1509b.c
index 9182b3954fe4..d264cb361b64 100644
--- a/drivers/gpio/gpio_sx1509b.c
+++ b/drivers/gpio/gpio_sx1509b.c
@@ -16,6 +16,7 @@
 #include <init.h>
 #include <drivers/gpio.h>
 #include <drivers/gpio/gpio_sx1509b.h>
+#include <dt-bindings/gpio/semtech-sx1509b.h>
 #include <drivers/i2c.h>
 #include <sys/byteorder.h>
 #include <sys/util.h>
@@ -289,21 +290,6 @@ static int sx1509b_config(const struct device *dev,
 		return -EWOULDBLOCK;
 	}
 
-	/* Zephyr currently defines drive strength support based on
-	 * the behavior and capabilities of the Nordic GPIO
-	 * peripheral: strength defaults to low but can be set high,
-	 * and is controlled independently for output levels.
-	 *
-	 * SX150x defaults to high strength, and does not support
-	 * different strengths for different levels.
-	 *
-	 * Until something more general is available reject any
-	 * attempt to set a non-default drive strength.
-	 */
-	if ((flags & GPIO_DS_ALT) != 0) {
-		return -ENOTSUP;
-	}
-
 	k_sem_take(&drv_data->lock, K_FOREVER);
 
 	if (drv_data->led_drv_enable & BIT(pin)) {
@@ -359,7 +345,7 @@ static int sx1509b_config(const struct device *dev,
 		pins->dir |= BIT(pin);
 	}
 
-	if ((flags & GPIO_INT_DEBOUNCE) != 0) {
+	if ((flags & SX1509B_GPIO_DEBOUNCE) != 0) {
 		debounce->debounce_enable |= BIT(pin);
 	} else {
 		debounce->debounce_enable &= ~BIT(pin);
diff --git a/drivers/lora/sx126x_standalone.c b/drivers/lora/sx126x_standalone.c
index 616bab7bc142..60f46c6319ac 100644
--- a/drivers/lora/sx126x_standalone.c
+++ b/drivers/lora/sx126x_standalone.c
@@ -67,8 +67,7 @@ int sx126x_variant_init(const struct device *dev)
 
 	if (gpio_pin_configure_dt(&sx126x_gpio_reset, GPIO_OUTPUT_ACTIVE) ||
 	    gpio_pin_configure_dt(&sx126x_gpio_busy, GPIO_INPUT) ||
-	    gpio_pin_configure_dt(&sx126x_gpio_dio1,
-				  GPIO_INPUT | GPIO_INT_DEBOUNCE)) {
+	    gpio_pin_configure_dt(&sx126x_gpio_dio1, GPIO_INPUT)) {
 		LOG_ERR("GPIO configuration failed.");
 		return -EIO;
 	}
diff --git a/drivers/lora/sx127x.c b/drivers/lora/sx127x.c
index 0f6e4d29de36..e18d3705f5da 100644
--- a/drivers/lora/sx127x.c
+++ b/drivers/lora/sx127x.c
@@ -369,8 +369,7 @@ void SX127xIoIrqInit(DioIrqHandler **irqHandlers)
 
 		k_work_init(&dev_data.dio_work[i], sx127x_dio_work_handle);
 
-		gpio_pin_configure_dt(&sx127x_dios[i],
-				      GPIO_INPUT | GPIO_INT_DEBOUNCE);
+		gpio_pin_configure_dt(&sx127x_dios[i], GPIO_INPUT);
 
 		gpio_init_callback(&callbacks[i],
 				   sx127x_irq_callback,
diff --git a/include/drivers/gpio.h b/include/drivers/gpio.h
index ec843328b9c6..1d4488f4e65d 100644
--- a/include/drivers/gpio.h
+++ b/include/drivers/gpio.h
@@ -34,16 +34,40 @@ extern "C" {
  * @{
  */
 
+/**
+ * @deprecated Use the GPIO controller/SoC specific `*_GPIO_DEBOUNCE` flag instead.
+ */
+#define GPIO_INT_DEBOUNCE (1U << 8) __DEPRECATED_MACRO
+
+/**
+ * @deprecated Use the GPIO controller/SoC specific `*_GPIO_DS_*` flags instead.
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define GPIO_DS_LOW_POS   9                                      __DEPRECATED_MACRO
+#define GPIO_DS_LOW_MASK  (0x1U << GPIO_DS_LOW_POS)              __DEPRECATED_MACRO
+#define GPIO_DS_HIGH_POS  10                                     __DEPRECATED_MACRO
+#define GPIO_DS_HIGH_MASK (0x1U << GPIO_DS_HIGH_POS)             __DEPRECATED_MACRO
+#define GPIO_DS_MASK      (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK) __DEPRECATED_MACRO
+/** @endcond */
+#define GPIO_DS_DFLT_LOW  (0x0U << GPIO_DS_LOW_POS)              __DEPRECATED_MACRO
+#define GPIO_DS_ALT_LOW   (0x1U << GPIO_DS_LOW_POS)              __DEPRECATED_MACRO
+#define GPIO_DS_DFLT_HIGH (0x0U << GPIO_DS_HIGH_POS)             __DEPRECATED_MACRO
+#define GPIO_DS_ALT_HIGH  (0x1U << GPIO_DS_HIGH_POS)             __DEPRECATED_MACRO
+#define GPIO_DS_DFLT      (GPIO_DS_DFLT_LOW | GPIO_DS_DFLT_HIGH) __DEPRECATED_MACRO
+#define GPIO_DS_ALT       (GPIO_DS_ALT_LOW | GPIO_DS_ALT_HIGH)   __DEPRECATED_MACRO
+/** @} */
+
 /**
  * @name GPIO input/output configuration flags
  * @{
  */
 
 /** Enables pin as input. */
-#define GPIO_INPUT              (1U << 8)
+#define GPIO_INPUT              (1U << 16)
 
 /** Enables pin as output, no change to the output state. */
-#define GPIO_OUTPUT             (1U << 9)
+#define GPIO_OUTPUT             (1U << 17)
 
 /** Disables pin for both input and output. */
 #define GPIO_DISCONNECTED	0
@@ -51,13 +75,13 @@ extern "C" {
 /** @cond INTERNAL_HIDDEN */
 
 /* Initializes output to a low state. */
-#define GPIO_OUTPUT_INIT_LOW    (1U << 10)
+#define GPIO_OUTPUT_INIT_LOW    (1U << 18)
 
 /* Initializes output to a high state. */
-#define GPIO_OUTPUT_INIT_HIGH   (1U << 11)
+#define GPIO_OUTPUT_INIT_HIGH   (1U << 19)
 
 /* Initializes output based on logic level */
-#define GPIO_OUTPUT_INIT_LOGICAL (1U << 12)
+#define GPIO_OUTPUT_INIT_LOGICAL (1U << 20)
 
 /** @endcond */
 
@@ -88,19 +112,19 @@ extern "C" {
  */
 
 /** Disables GPIO pin interrupt. */
-#define GPIO_INT_DISABLE               (1U << 13)
+#define GPIO_INT_DISABLE               (1U << 21)
 
 /** @cond INTERNAL_HIDDEN */
 
 /* Enables GPIO pin interrupt. */
-#define GPIO_INT_ENABLE                (1U << 14)
+#define GPIO_INT_ENABLE                (1U << 22)
 
 /* GPIO interrupt is sensitive to logical levels.
  *
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_LEVELS_LOGICAL        (1U << 15)
+#define GPIO_INT_LEVELS_LOGICAL        (1U << 23)
 
 /* GPIO interrupt is edge sensitive.
  *
@@ -109,7 +133,7 @@ extern "C" {
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_EDGE                  (1U << 16)
+#define GPIO_INT_EDGE                  (1U << 24)
 
 /* Trigger detection when input state is (or transitions to) physical low or
  * logical 0 level.
@@ -117,7 +141,7 @@ extern "C" {
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_LOW_0                 (1U << 17)
+#define GPIO_INT_LOW_0                 (1U << 25)
 
 /* Trigger detection on input state is (or transitions to) physical high or
  * logical 1 level.
@@ -125,7 +149,7 @@ extern "C" {
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_HIGH_1                (1U << 18)
+#define GPIO_INT_HIGH_1                (1U << 26)
 
 #define GPIO_INT_MASK                  (GPIO_INT_DISABLE | \
 					GPIO_INT_ENABLE | \
@@ -201,79 +225,6 @@ extern "C" {
 
 /** @} */
 
-/** Enable GPIO pin debounce.
- *
- * @note Drivers that do not support a debounce feature should ignore
- * this flag rather than rejecting the configuration with -ENOTSUP.
- */
-#define GPIO_INT_DEBOUNCE              (1U << 19)
-
-/**
- * @name GPIO drive strength flags
- * The `GPIO_DS_*` flags are used with `gpio_pin_configure` to specify the drive
- * strength configuration of a GPIO pin.
- *
- * The drive strength of individual pins can be configured
- * independently for when the pin output is low and high.
- *
- * The `GPIO_DS_*_LOW` enumerations define the drive strength of a pin
- * when output is low.
-
- * The `GPIO_DS_*_HIGH` enumerations define the drive strength of a pin
- * when output is high.
- *
- * The interface supports two different drive strengths:
- * `DFLT` - The lowest drive strength supported by the HW
- * `ALT` - The highest drive strength supported by the HW
- *
- * On hardware that supports only one standard drive strength, both
- * `DFLT` and `ALT` have the same behavior.
- * @{
- */
-/** @cond INTERNAL_HIDDEN */
-#define GPIO_DS_LOW_POS 20
-#define GPIO_DS_LOW_MASK (0x3U << GPIO_DS_LOW_POS)
-/** @endcond */
-
-/** Default drive strength standard when GPIO pin output is low.
- */
-#define GPIO_DS_DFLT_LOW (0x0U << GPIO_DS_LOW_POS)
-
-/** Alternative drive strength when GPIO pin output is low.
- * For hardware that does not support configurable drive strength
- * use the default drive strength.
- */
-#define GPIO_DS_ALT_LOW (0x1U << GPIO_DS_LOW_POS)
-
-/** @cond INTERNAL_HIDDEN */
-#define GPIO_DS_HIGH_POS 22
-#define GPIO_DS_HIGH_MASK (0x3U << GPIO_DS_HIGH_POS)
-/** @endcond */
-
-/** Default drive strength when GPIO pin output is high.
- */
-#define GPIO_DS_DFLT_HIGH (0x0U << GPIO_DS_HIGH_POS)
-
-/** Alternative drive strength when GPIO pin output is high.
- * For hardware that does not support configurable drive strengths
- * use the default drive strength.
- */
-#define GPIO_DS_ALT_HIGH (0x1U << GPIO_DS_HIGH_POS)
-
-/** Combined default drive strength.
- */
-#define GPIO_DS_DFLT (GPIO_DS_DFLT_LOW | GPIO_DS_DFLT_HIGH)
-
-/** Combined alternative drive strength.
- */
-#define GPIO_DS_ALT (GPIO_DS_ALT_LOW | GPIO_DS_ALT_HIGH)
-
-/** @cond INTERNAL_HIDDEN */
-#define GPIO_DS_MASK (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK)
-/** @endcond */
-
-/** @} */
-
 /** @cond INTERNAL_HIDDEN */
 #define GPIO_DIR_MASK		(GPIO_INPUT | GPIO_OUTPUT)
 /** @endcond */
@@ -310,11 +261,14 @@ typedef uint8_t gpio_pin_t;
 /**
  * @brief Provides a type to hold GPIO devicetree flags.
  *
- * All GPIO flags that can be expressed in devicetree fit in the low 8
+ * All GPIO flags that can be expressed in devicetree fit in the low 16
  * bits of the full flags field, so use a reduced-size type to record
  * that part of a GPIOS property.
+ *
+ * The lower 8 bits are used for standard flags. The upper 8 bits are reserved
+ * for SoC specific flags.
  */
-typedef uint8_t gpio_dt_flags_t;
+typedef uint16_t gpio_dt_flags_t;
 
 /**
  * @brief Provides a type to hold GPIO configuration flags.
@@ -652,8 +606,6 @@ static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port,
 	enum gpio_int_trig trig;
 	enum gpio_int_mode mode;
 
-	__ASSERT_NO_MSG((flags & GPIO_INT_DEBOUNCE) == 0);
-
 	__ASSERT((flags & (GPIO_INT_DISABLE | GPIO_INT_ENABLE))
 		 != (GPIO_INT_DISABLE | GPIO_INT_ENABLE),
 		 "Cannot both enable and disable interrupts");
@@ -714,8 +666,7 @@ static inline int gpio_pin_interrupt_configure_dt(const struct gpio_dt_spec *spe
  * @param port Pointer to device structure for the driver instance.
  * @param pin Pin number to configure.
  * @param flags Flags for pin configuration: 'GPIO input/output configuration
- *        flags', 'GPIO drive strength flags', 'GPIO pin drive flags', 'GPIO pin
- *        bias flags', GPIO_INT_DEBOUNCE.
+ *        flags', 'GPIO pin drive flags', 'GPIO pin bias flags'.
  *
  * @retval 0 If successful.
  * @retval -ENOTSUP if any of the configuration options is not supported
diff --git a/include/dt-bindings/gpio/andestech-atcgpio100.h b/include/dt-bindings/gpio/andestech-atcgpio100.h
new file mode 100644
index 000000000000..201a0a5f14f8
--- /dev/null
+++ b/include/dt-bindings/gpio/andestech-atcgpio100.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for Andestech Technology
+ * Corporation ATCGPIO100 SoCs.
+ */
+#define ATCGPIO100_GPIO_DEBOUNCE (1U << 8)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_ */
diff --git a/include/dt-bindings/gpio/atmel-sam-gpio.h b/include/dt-bindings/gpio/atmel-sam-gpio.h
new file mode 100644
index 000000000000..c92417639e72
--- /dev/null
+++ b/include/dt-bindings/gpio/atmel-sam-gpio.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for Atmel SAM SoCs.
+ */
+#define SAM_GPIO_DEBOUNCE (1U << 8)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/atmel-sam0-gpio.h b/include/dt-bindings/gpio/atmel-sam0-gpio.h
new file mode 100644
index 000000000000..2f5986ad3245
--- /dev/null
+++ b/include/dt-bindings/gpio/atmel-sam0-gpio.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for Atmel SAM0 SoCs.
+ */
+#define SAM0_GPIO_DEBOUNCE (1U << 8)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/espressif-esp32-gpio.h b/include/dt-bindings/gpio/espressif-esp32-gpio.h
new file mode 100644
index 000000000000..36f824cd2ad5
--- /dev/null
+++ b/include/dt-bindings/gpio/espressif-esp32-gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
+
+/**
+ * @name GPIO drive strength flags
+ *
+ * The drive strength flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable for Espressif
+ * ESP32 SoCs.
+ *
+ * The interface supports two different drive strengths:
+ * `DFLT` - The lowest drive strength supported by the HW
+ * `ALT` - The highest drive strength supported by the HW
+ *
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define ESP32_GPIO_DS_POS 9
+#define ESP32_GPIO_DS_MASK (0x3U << ESP32_GPIO_DS_POS)
+/** @endcond */
+
+/** Default drive strength. */
+#define ESP32_GPIO_DS_DFLT (0x0U << ESP32_GPIO_DS_POS)
+
+/** Alternative drive strength. */
+#define ESP32_GPIO_DS_ALT (0x3U << ESP32_GPIO_DS_POS)
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
index 10cb8660d29a..3e4dbd25f4aa 100644
--- a/include/dt-bindings/gpio/gpio.h
+++ b/include/dt-bindings/gpio/gpio.h
@@ -76,29 +76,26 @@
 
 /** @} */
 
+/* Note: Bits 15 downto 8 are reserved for SoC specific flags. */
+
 /**
- * @name GPIO pin voltage flags
- *
- * The voltage flags are a Zephyr specific extension of the standard GPIO
- * flags specified by the Linux GPIO binding. Only applicable if SoC allows
- * to configure pin voltage per individual pin.
- *
+ * @deprecated Use the GPIO controller/SoC specific `*_GPIO_VOLTAGE_*` flags instead.
  * @{
  */
 
 /** @cond INTERNAL_HIDDEN */
-#define GPIO_VOLTAGE_POS	6
-#define GPIO_VOLTAGE_MASK	(3U << GPIO_VOLTAGE_POS)
+#define GPIO_VOLTAGE_POS        11
+#define GPIO_VOLTAGE_MASK       (3U << GPIO_VOLTAGE_POS)
 /** @endcond */
 
 /** Set pin at the default voltage level */
-#define GPIO_VOLTAGE_DEFAULT	(0U << GPIO_VOLTAGE_POS)
+#define GPIO_VOLTAGE_DEFAULT    (0U << GPIO_VOLTAGE_POS)
 /** Set pin voltage level at 1.8 V */
-#define GPIO_VOLTAGE_1P8	(1U << GPIO_VOLTAGE_POS)
+#define GPIO_VOLTAGE_1P8        (1U << GPIO_VOLTAGE_POS)
 /** Set pin voltage level at 3.3 V */
-#define GPIO_VOLTAGE_3P3	(2U << GPIO_VOLTAGE_POS)
+#define GPIO_VOLTAGE_3P3        (2U << GPIO_VOLTAGE_POS)
 /** Set pin voltage level at 5.0 V */
-#define GPIO_VOLTAGE_5P0	(3U << GPIO_VOLTAGE_POS)
+#define GPIO_VOLTAGE_5P0        (3U << GPIO_VOLTAGE_POS)
 
 /** @} */
 
diff --git a/include/dt-bindings/gpio/ite-it8xxx2-gpio.h b/include/dt-bindings/gpio/ite-it8xxx2-gpio.h
new file mode 100644
index 000000000000..477f3ac22730
--- /dev/null
+++ b/include/dt-bindings/gpio/ite-it8xxx2-gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
+
+/**
+ * @name GPIO pin voltage flags
+ *
+ * The voltage flags are a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding for use with the ITE IT8xxx2 SoCs.
+ *
+ * @{
+ */
+
+/** @cond INTERNAL_HIDDEN */
+#define IT8XXX2_GPIO_VOLTAGE_POS	11
+#define IT8XXX2_GPIO_VOLTAGE_MASK	(3U << IT8XXX2_GPIO_VOLTAGE_POS)
+/** @endcond */
+
+/** Set pin at the default voltage level */
+#define IT8XXX2_GPIO_VOLTAGE_DEFAULT	(0U << IT8XXX2_GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 1.8 V */
+#define IT8XXX2_GPIO_VOLTAGE_1P8	(1U << IT8XXX2_GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 3.3 V */
+#define IT8XXX2_GPIO_VOLTAGE_3P3	(2U << IT8XXX2_GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 5.0 V */
+#define IT8XXX2_GPIO_VOLTAGE_5P0	(3U << IT8XXX2_GPIO_VOLTAGE_POS)
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/nordic-nrf-gpio.h b/include/dt-bindings/gpio/nordic-nrf-gpio.h
new file mode 100644
index 000000000000..a3f385203b01
--- /dev/null
+++ b/include/dt-bindings/gpio/nordic-nrf-gpio.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
+
+/**
+ * @name GPIO drive strength flags
+ *
+ * The drive strength flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable for Nordic
+ * Semiconductor nRF SoCs.
+ *
+ * The drive strength of individual pins can be configured
+ * independently for when the pin output is low and high.
+ *
+ * The `GPIO_DS_*_LOW` enumerations define the drive strength of a pin
+ * when output is low.
+
+ * The `GPIO_DS_*_HIGH` enumerations define the drive strength of a pin
+ * when output is high.
+ *
+ * The interface supports two different drive strengths:
+ * `DFLT` - The lowest drive strength supported by the HW
+ * `ALT` - The highest drive strength supported by the HW
+ *
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define NRF_GPIO_DS_LOW_POS 9
+#define NRF_GPIO_DS_LOW_MASK (0x1U << NRF_GPIO_DS_LOW_POS)
+/** @endcond */
+
+/** Default drive strength standard when GPIO pin output is low.
+ */
+#define NRF_GPIO_DS_DFLT_LOW (0x0U << NRF_GPIO_DS_LOW_POS)
+
+/** Alternative drive strength when GPIO pin output is low.
+ * For hardware that does not support configurable drive strength
+ * use the default drive strength.
+ */
+#define NRF_GPIO_DS_ALT_LOW (0x1U << NRF_GPIO_DS_LOW_POS)
+
+/** @cond INTERNAL_HIDDEN */
+#define NRF_GPIO_DS_HIGH_POS 10
+#define NRF_GPIO_DS_HIGH_MASK (0x1U << NRF_GPIO_DS_HIGH_POS)
+/** @endcond */
+
+/** Default drive strength when GPIO pin output is high.
+ */
+#define NRF_GPIO_DS_DFLT_HIGH (0x0U << NRF_GPIO_DS_HIGH_POS)
+
+/** Alternative drive strength when GPIO pin output is high.
+ * For hardware that does not support configurable drive strengths
+ * use the default drive strength.
+ */
+#define NRF_GPIO_DS_ALT_HIGH (0x1U << NRF_GPIO_DS_HIGH_POS)
+
+/** Combined default drive strength.
+ */
+#define NRF_GPIO_DS_DFLT (NRF_GPIO_DS_DFLT_LOW | NRF_GPIO_DS_DFLT_HIGH)
+
+/** Combined alternative drive strength.
+ */
+#define NRF_GPIO_DS_ALT (NRF_GPIO_DS_ALT_LOW | NRF_GPIO_DS_ALT_HIGH)
+
+/** @cond INTERNAL_HIDDEN */
+#define NRF_GPIO_DS_MASK (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK)
+/** @endcond */
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/nxp-kinetis-gpio.h b/include/dt-bindings/gpio/nxp-kinetis-gpio.h
new file mode 100644
index 000000000000..de1b3534d9fc
--- /dev/null
+++ b/include/dt-bindings/gpio/nxp-kinetis-gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
+
+/**
+ * @name GPIO drive strength flags
+ *
+ * The drive strength flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable for NXP Kinetis
+ * SoCs.
+ *
+ * The interface supports two different drive strengths:
+ * `DFLT` - The lowest drive strength supported by the HW
+ * `ALT` - The highest drive strength supported by the HW
+ *
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define KINETIS_GPIO_DS_POS 9
+#define KINETIS_GPIO_DS_MASK (0x3U << KINETIS_GPIO_DS_POS)
+/** @endcond */
+
+/** Default drive strength. */
+#define KINETIS_GPIO_DS_DFLT (0x0U << KINETIS_GPIO_DS_POS)
+
+/** Alternative drive strength. */
+#define KINETIS_GPIO_DS_ALT (0x3U << KINETIS_GPIO_DS_POS)
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/semtech-sx1509b.h b/include/dt-bindings/gpio/semtech-sx1509b.h
new file mode 100644
index 000000000000..0270425f09e5
--- /dev/null
+++ b/include/dt-bindings/gpio/semtech-sx1509b.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for Semtech SX1509B GPIO
+ * controllers.
+ */
+#define SX1509B_GPIO_DEBOUNCE (1U << 8)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_ */
diff --git a/include/dt-bindings/gpio/snps-designware-gpio.h b/include/dt-bindings/gpio/snps-designware-gpio.h
new file mode 100644
index 000000000000..e06dc962178e
--- /dev/null
+++ b/include/dt-bindings/gpio/snps-designware-gpio.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for SNPS DesignWare GPIO
+ * controllers.
+ */
+#define DW_GPIO_DEBOUNCE (1U << 8)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_ */
diff --git a/include/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h b/include/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h
new file mode 100644
index 000000000000..cf1dc8b63d4c
--- /dev/null
+++ b/include/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2022 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_
+
+/**
+ * @brief Enable GPIO pin debounce.
+ *
+ * The debounce flag is a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding. Only applicable for Texas
+ * Instruments CC1xx/CC26xx SoCs.
+ */
+#define CC13XX_CC26XX_GPIO_DEBOUNCE (1U << 8)
+
+/**
+ * @name GPIO drive strength flags
+ *
+ * The drive strength flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable for Texas
+ * Instruments CC13xx/CC26xx SoCs.
+ *
+ * The interface supports two different drive strengths:
+ * `DFLT` - The lowest drive strength supported by the HW
+ * `ALT` - The highest drive strength supported by the HW
+ *
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define CC13XX_CC26XX_GPIO_DS_POS 9
+#define CC13XX_CC26XX_GPIO_DS_MASK (0x3U << CC13XX_CC26XX_GPIO_DS_POS)
+/** @endcond */
+
+/** Default drive strength. */
+#define CC13XX_CC26XX_GPIO_DS_DFLT (0x0U << CC13XX_CC26XX_GPIO_DS_POS)
+
+/** Alternative drive strength. */
+#define CC13XX_CC26XX_GPIO_DS_ALT (0x3U << CC13XX_CC26XX_GPIO_DS_POS)
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_TI_CC13XX_CC26XX_GPIO_H_ */
diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/app_gpio.c b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/app_gpio.c
index 46b40240896f..525a3cc6af9c 100644
--- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/app_gpio.c
+++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/app_gpio.c
@@ -64,8 +64,7 @@ void app_gpio_init(void)
 
 	button_device[0] = device_get_binding(DT_GPIO_LABEL(SW0_NODE, gpios));
 	gpio_pin_configure(button_device[0], DT_GPIO_PIN(SW0_NODE, gpios),
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE |
-			   DT_GPIO_FLAGS(SW0_NODE, gpios));
+			   GPIO_INPUT | DT_GPIO_FLAGS(SW0_NODE, gpios));
 	gpio_pin_interrupt_configure(button_device[0],
 				     DT_GPIO_PIN(SW0_NODE, gpios),
 				     GPIO_INT_EDGE_TO_ACTIVE);
@@ -76,8 +75,7 @@ void app_gpio_init(void)
 #ifndef ONE_LED_ONE_BUTTON_BOARD
 	button_device[1] = device_get_binding(DT_GPIO_LABEL(SW1_NODE, gpios));
 	gpio_pin_configure(button_device[1], DT_GPIO_PIN(SW1_NODE, gpios),
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE |
-			   DT_GPIO_FLAGS(SW1_NODE, gpios));
+			   GPIO_INPUT | DT_GPIO_FLAGS(SW1_NODE, gpios));
 	gpio_pin_interrupt_configure(button_device[1],
 				     DT_GPIO_PIN(SW1_NODE, gpios),
 				     GPIO_INT_EDGE_TO_ACTIVE);
@@ -87,8 +85,7 @@ void app_gpio_init(void)
 
 	button_device[2] = device_get_binding(DT_GPIO_LABEL(SW2_NODE, gpios));
 	gpio_pin_configure(button_device[2], DT_GPIO_PIN(SW2_NODE, gpios),
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE |
-			   DT_GPIO_FLAGS(SW2_NODE, gpios));
+			   GPIO_INPUT | DT_GPIO_FLAGS(SW2_NODE, gpios));
 	gpio_pin_interrupt_configure(button_device[2],
 				     DT_GPIO_PIN(SW2_NODE, gpios),
 				     GPIO_INT_EDGE_TO_ACTIVE);
@@ -98,8 +95,7 @@ void app_gpio_init(void)
 
 	button_device[3] = device_get_binding(DT_GPIO_LABEL(SW3_NODE, gpios));
 	gpio_pin_configure(button_device[3], DT_GPIO_PIN(SW3_NODE, gpios),
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE |
-			   DT_GPIO_FLAGS(SW3_NODE, gpios));
+			   GPIO_INPUT | DT_GPIO_FLAGS(SW3_NODE, gpios));
 	gpio_pin_interrupt_configure(button_device[3],
 				     DT_GPIO_PIN(SW3_NODE, gpios),
 				     GPIO_INT_EDGE_TO_ACTIVE);
diff --git a/samples/sensor/fxos8700-hid/src/main.c b/samples/sensor/fxos8700-hid/src/main.c
index 61a182854076..e3f578f7fbd4 100644
--- a/samples/sensor/fxos8700-hid/src/main.c
+++ b/samples/sensor/fxos8700-hid/src/main.c
@@ -110,8 +110,7 @@ int callbacks_configure(const struct device *gpio, uint32_t pin, int flags,
 		return -ENXIO;
 	}
 
-	gpio_pin_configure(gpio, pin,
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE | flags);
+	gpio_pin_configure(gpio, pin, GPIO_INPUT | flags);
 	ret = gpio_pin_get(gpio, pin);
 	if (ret < 0) {
 		return ret;
diff --git a/samples/subsys/usb/hid-cdc/src/main.c b/samples/subsys/usb/hid-cdc/src/main.c
index 243c3061dbf6..48afc2ffe9c7 100644
--- a/samples/subsys/usb/hid-cdc/src/main.c
+++ b/samples/subsys/usb/hid-cdc/src/main.c
@@ -531,8 +531,7 @@ int callbacks_configure(const struct device *gpio, uint32_t pin, int flags,
 		return -ENXIO;
 	}
 
-	gpio_pin_configure(gpio, pin,
-			   GPIO_INPUT | GPIO_INT_DEBOUNCE | flags);
+	gpio_pin_configure(gpio, pin, GPIO_INPUT | flags);
 
 	gpio_init_callback(callback, handler, BIT(pin));
 	gpio_add_callback(gpio, callback);
diff --git a/tests/drivers/gpio/gpio_basic_api/src/test_callback_manage.c b/tests/drivers/gpio/gpio_basic_api/src/test_callback_manage.c
index 500fccb16434..fa9e364d5576 100644
--- a/tests/drivers/gpio/gpio_basic_api/src/test_callback_manage.c
+++ b/tests/drivers/gpio/gpio_basic_api/src/test_callback_manage.c
@@ -48,8 +48,7 @@ static int init_callback(const struct device *dev,
 
 	if (rc == 0) {
 		/* 2. configure PIN_IN callback, but don't enable */
-		rc = gpio_pin_configure(dev, PIN_IN,
-					GPIO_INPUT | GPIO_INT_DEBOUNCE);
+		rc = gpio_pin_configure(dev, PIN_IN, GPIO_INPUT);
 	}
 
 	if (rc == 0) {
diff --git a/tests/drivers/gpio/gpio_basic_api/src/test_callback_trigger.c b/tests/drivers/gpio/gpio_basic_api/src/test_callback_trigger.c
index 57f6deddfbb9..1d66944e6314 100644
--- a/tests/drivers/gpio/gpio_basic_api/src/test_callback_trigger.c
+++ b/tests/drivers/gpio/gpio_basic_api/src/test_callback_trigger.c
@@ -54,7 +54,7 @@ static int test_callback(int mode)
 	}
 
 	/* 2. configure PIN_IN callback and trigger condition */
-	rc = gpio_pin_configure(dev, PIN_IN, GPIO_INPUT | GPIO_INT_DEBOUNCE);
+	rc = gpio_pin_configure(dev, PIN_IN, GPIO_INPUT);
 	if (rc != 0) {
 		TC_ERROR("config PIN_IN fail: %d\n", rc);
 		goto err_exit;