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rcar_mmc.c
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/*
* Copyright (c) 2023 EPAM Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rcar_mmc
#include <zephyr/devicetree.h>
#include <zephyr/drivers/disk.h>
#include <zephyr/drivers/sdhc.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/cache.h>
#include <zephyr/drivers/regulator.h>
#include "rcar_mmc_registers.h"
#define PINCTRL_STATE_UHS PINCTRL_STATE_PRIV_START
/**
* @note we don't need any locks here, because SDHC subsystem cares about it
*/
LOG_MODULE_REGISTER(rcar_mmc, CONFIG_LOG_DEFAULT_LEVEL);
#define MMC_POLL_FLAGS_TIMEOUT_US 100000
#define MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US 1
#define MMC_BUS_CLOCK_FREQ 800000000
#ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
#define ALIGN_BUF_DMA __aligned(CONFIG_SDHC_BUFFER_ALIGNMENT)
#else
#define ALIGN_BUF_DMA
#endif
/**
* @brief Renesas MMC host controller driver data
*
*/
struct mmc_rcar_data {
DEVICE_MMIO_RAM; /* Must be first */
struct sdhc_io host_io;
struct sdhc_host_props props;
#ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
struct k_sem irq_xref_fin;
#endif
uint8_t ver;
/* in bytes, possible values are 2, 4 or 8 */
uint8_t width_access_sd_buf0;
uint8_t ddr_mode;
uint8_t restore_cfg_after_reset;
uint8_t is_last_cmd_app_cmd; /* ACMD55 */
#ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
uint8_t manual_retuning;
uint8_t tuning_buf[128] ALIGN_BUF_DMA;
#endif /* CONFIG_RCAR_MMC_SCC_SUPPORT */
uint8_t can_retune;
};
/**
* @brief Renesas MMC host controller driver configuration
*/
struct mmc_rcar_cfg {
DEVICE_MMIO_ROM; /* Must be first */
struct rcar_cpg_clk cpg_clk;
struct rcar_cpg_clk bus_clk;
const struct device *cpg_dev;
const struct pinctrl_dev_config *pcfg;
const struct device *regulator_vqmmc;
const struct device *regulator_vmmc;
uint32_t max_frequency;
#ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
void (*irq_config_func)(const struct device *dev);
#endif
uint8_t non_removable;
uint8_t uhs_support;
uint8_t mmc_hs200_1_8v;
uint8_t mmc_hs400_1_8v;
uint8_t bus_width;
uint8_t mmc_sdr104_support;
};
#ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
static int rcar_mmc_execute_tuning(const struct device *dev);
static int rcar_mmc_retune_if_needed(const struct device *dev, bool request_retune);
#endif
static int rcar_mmc_disable_scc(const struct device *dev);
static uint32_t rcar_mmc_read_reg32(const struct device *dev, uint32_t reg)
{
return sys_read32(DEVICE_MMIO_GET(dev) + reg);
}
static void rcar_mmc_write_reg32(const struct device *dev, uint32_t reg, uint32_t val)
{
sys_write32(val, DEVICE_MMIO_GET(dev) + reg);
}
/* cleanup SD card interrupt flag register and mask their interrupts */
static inline void rcar_mmc_reset_and_mask_irqs(const struct device *dev)
{
struct mmc_rcar_data *data = dev->data;
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, 0);
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1_MASK, ~0);
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CLEAR);
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2_MASK, ~0);
#ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
/* default value of Seq suspend should be 0 */
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, 0xfffffeff);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1, 0x0);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2_MASK, 0xffffffff);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2, 0x0);
#ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
k_sem_reset(&data->irq_xref_fin);
#endif
#endif /* CONFIG_RCAR_MMC_DMA_SUPPORT */
}
/**
* @brief check if MMC is busy
*
* This check should generally be implemented as checking the controller
* state. No MMC commands need to be sent.
*
* @param dev MMC device
* @retval 0 card is not busy
* @retval 1 card is busy
* @retval -EINVAL: the dev pointer is NULL
*/
static int rcar_mmc_card_busy(const struct device *dev)
{
uint32_t reg;
if (!dev) {
return -EINVAL;
}
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
return (reg & RCAR_MMC_INFO2_DAT0) ? 0 : 1;
}
/**
* @brief Check error flags inside INFO2 MMC register
*
* @note in/out parameters should be checked by a caller function
*
* @param dev MMC device
*
* @retval 0 INFO2 register hasn't errors
* @retval -ETIMEDOUT: timed out while tx/rx
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_check_errors(const struct device *dev)
{
uint32_t info2 = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
if (info2 & (RCAR_MMC_INFO2_ERR_TO | RCAR_MMC_INFO2_ERR_RTO)) {
LOG_DBG("timeout error 0x%08x", info2);
return -ETIMEDOUT;
}
if (info2 & (RCAR_MMC_INFO2_ERR_END | RCAR_MMC_INFO2_ERR_CRC | RCAR_MMC_INFO2_ERR_IDX)) {
LOG_DBG("communication out of sync 0x%08x", info2);
return -EILSEQ;
}
if (info2 & (RCAR_MMC_INFO2_ERR_ILA | RCAR_MMC_INFO2_ERR_ILR | RCAR_MMC_INFO2_ERR_ILW)) {
LOG_DBG("illegal access 0x%08x", info2);
return -EIO;
}
return 0;
}
/**
* @brief Poll flag(s) in MMC register and check errors
*
* @note in/out parameters should be checked by a caller function
*
* @param dev MMC device
* @param reg register offset relative to the base address
* @param flag polling flag(s)
* @param state state of flag(s) when we should stop polling
* @param check_errors call @ref rcar_mmc_check_errors function or not
* @param check_dma_errors check if there are DMA errors inside info2
* @param timeout_us timeout in microseconds how long we should poll flag(s)
*
* @retval 0 poll of flag(s) was successful
* @retval -ETIMEDOUT: timed out while tx/rx
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_poll_reg_flags_check_err(const struct device *dev, unsigned int reg,
uint32_t flag, uint32_t state, bool check_errors,
bool check_dma_errors, int64_t timeout_us)
{
int ret;
while ((rcar_mmc_read_reg32(dev, reg) & flag) != state) {
if (timeout_us < 0) {
LOG_DBG("timeout error during polling flag(s) 0x%08x in reg 0x%08x", flag,
reg);
return -ETIMEDOUT;
}
if (check_errors) {
ret = rcar_mmc_check_errors(dev);
if (ret) {
return ret;
}
}
if (check_dma_errors && rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO2)) {
LOG_DBG("%s: an error occurs on the DMAC channel #%u", dev->name,
(reg & RCAR_MMC_DMA_INFO2_ERR_RD) ? 1U : 0U);
return -EIO;
}
k_usleep(MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US);
timeout_us -= MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US;
}
return 0;
}
/* reset DMA MMC controller */
static inline void rcar_mmc_reset_dma(const struct device *dev)
{
uint32_t reg = RCAR_MMC_DMA_RST_DTRAN0 | RCAR_MMC_DMA_RST_DTRAN1;
rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, 0);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_RST, ~reg);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_RST, ~0);
rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, 1);
}
/**
* @brief reset MMC controller state
*
* Used when the MMC has encountered an error. Resetting the MMC controller
* should clear all errors on the MMC, but does not necessarily reset I/O
* settings to boot (this can be done with @ref sdhc_set_io)
*
* @note during reset the clock input is disabled, also this call changes rate
*
* @param dev MMC controller device
* @retval 0 reset succeeded
* @retval -ETIMEDOUT: controller reset timed out
* @retval -EINVAL: the dev pointer is NULL
* @retval -EILSEQ: communication out of sync
* @retval -ENOTSUP: controller does not support I/O
*
* @details List of affected registers and their bits during the soft reset trigger:
* * RCAR_MMC_STOP all bits reset to default (0x0);
* * RCAR_MMC_INFO1 affected bits:
* * RCAR_MMC_INFO1_CMP default state 0;
* * RCAR_MMC_INFO1_RSP default state 0;
* * HPIRES Response Reception Completion (16), default state 0;
* * RCAR_MMC_INFO2 all bits reset 0, except the next:
* * RCAR_MMC_INFO2_DAT0 state unknown after reset;
* * RCAR_MMC_INFO2_SCLKDIVEN default state 1;
* * RCAR_MMC_CLKCTL affected bit(s):
* * RCAR_MMC_CLKCTL_SCLKEN default state 0;
* * RCAR_MMC_OPTION affected bits:
* * WIDTH (15) and WIDTH8 (13) set to 0, which equal to 4-bits bus;
* * Timeout Mode Select (EXTOP - 9) is set to 0;
* * Timeout Mask (TOUTMASK - 8) is set to 0;
* * Timeout Counter (TOP27-TOP24 bits 7-4) is equal to 0b1110;
* * Card Detect Time Counter (CTOP24-CTOP21 bits 3-0) is equal to 0b1110;
* * RCAR_MMC_ERR_STS1 all bits after reset 0, except the next:
* * E13 default state 1 (E12-E14 it is CRC status 0b010);
* * RCAR_MMC_ERR_STS2 all bits after reset 0;
* * IO_INFO1 all bits after reset 0;
* * RCAR_MMC_IF_MODE all bits after reset 0.
*/
static int rcar_mmc_reset(const struct device *dev)
{
int ret = 0;
uint32_t reg;
struct mmc_rcar_data *data;
uint8_t can_retune;
if (!dev) {
return -EINVAL;
}
data = dev->data;
/*
* soft reset of the host
*/
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_SOFT_RST);
reg &= ~RCAR_MMC_SOFT_RST_RSTX;
rcar_mmc_write_reg32(dev, RCAR_MMC_SOFT_RST, reg);
reg |= RCAR_MMC_SOFT_RST_RSTX;
rcar_mmc_write_reg32(dev, RCAR_MMC_SOFT_RST, reg);
rcar_mmc_reset_and_mask_irqs(dev);
/*
* note: DMA reset can be triggered only in case of error in
* DMA Info2 otherwise the SDIP will not accurately operate
*/
#ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
rcar_mmc_reset_dma(dev);
#endif
can_retune = data->can_retune;
if (can_retune) {
rcar_mmc_disable_scc(dev);
}
/* note: be careful soft reset stops SDCLK */
if (data->restore_cfg_after_reset) {
struct sdhc_io ios;
memcpy(&ios, &data->host_io, sizeof(ios));
memset(&data->host_io, 0, sizeof(ios));
data->host_io.power_mode = ios.power_mode;
ret = sdhc_set_io(dev, &ios);
rcar_mmc_write_reg32(dev, RCAR_MMC_STOP, RCAR_MMC_STOP_SEC);
#ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
/* tune if this reset isn't invoked during tuning */
if (can_retune && (ios.timing == SDHC_TIMING_SDR50 ||
ios.timing == SDHC_TIMING_SDR104 ||
ios.timing == SDHC_TIMING_HS200)) {
ret = rcar_mmc_execute_tuning(dev);
}
#endif
return ret;
}
data->ddr_mode = 0;
data->host_io.bus_width = SDHC_BUS_WIDTH4BIT;
data->host_io.timing = SDHC_TIMING_LEGACY;
data->is_last_cmd_app_cmd = 0;
return 0;
}
/**
* @brief SD Clock (SD_CLK) Output Control Enable
*
* @note in/out parameters should be checked by a caller function.
*
* @param dev MMC device
* @param enable
* false: SD_CLK output is disabled. The SD_CLK signal is fixed 0.
* true: SD_CLK output is enabled.
*
* @retval 0 I/O was configured correctly
* @retval -ETIMEDOUT: card busy flag is set during long time
*/
static int rcar_mmc_enable_clock(const struct device *dev, bool enable)
{
int ret;
uint32_t mmc_clk_ctl = rcar_mmc_read_reg32(dev, RCAR_MMC_CLKCTL);
if (enable == true) {
mmc_clk_ctl &= ~RCAR_MMC_CLKCTL_OFFEN;
mmc_clk_ctl |= RCAR_MMC_CLKCTL_SCLKEN;
} else {
mmc_clk_ctl |= RCAR_MMC_CLKCTL_OFFEN;
mmc_clk_ctl &= ~RCAR_MMC_CLKCTL_SCLKEN;
}
/*
* Do not change the values of these bits
* when the CBSY bit in SD_INFO2 is 1
*/
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0, false,
false, MMC_POLL_FLAGS_TIMEOUT_US);
if (ret) {
return -ETIMEDOUT;
}
rcar_mmc_write_reg32(dev, RCAR_MMC_CLKCTL, mmc_clk_ctl);
/* SD spec recommends at least 1 ms of delay */
k_msleep(1);
return 0;
}
/**
* @brief Convert SDHC response to Renesas MMC response
*
* Function performs a conversion from SDHC response to Renesas MMC
* CMD register response.
*
* @note in/out parameters should be checked by a caller function.
*
* @param response_type SDHC response type without SPI flags
*
* @retval positiv number (partial configuration of CMD register) on
* success, negative errno code otherwise
*/
static int32_t rcar_mmc_convert_sd_to_mmc_resp(uint32_t response_type)
{
uint32_t mmc_resp = 0U;
switch (response_type) {
case SD_RSP_TYPE_NONE:
mmc_resp = RCAR_MMC_CMD_RSP_NONE;
break;
case SD_RSP_TYPE_R1:
case SD_RSP_TYPE_R5:
case SD_RSP_TYPE_R6:
case SD_RSP_TYPE_R7:
mmc_resp = RCAR_MMC_CMD_RSP_R1;
break;
case SD_RSP_TYPE_R1b:
case SD_RSP_TYPE_R5b:
mmc_resp = RCAR_MMC_CMD_RSP_R1B;
break;
case SD_RSP_TYPE_R2:
mmc_resp = RCAR_MMC_CMD_RSP_R2;
break;
case SD_RSP_TYPE_R3:
case SD_RSP_TYPE_R4:
mmc_resp = RCAR_MMC_CMD_RSP_R3;
break;
default:
LOG_ERR("unknown response type 0x%08x", response_type);
return -EINVAL;
}
__ASSERT((int32_t)mmc_resp >= 0, "%s: converted response shouldn't be negative", __func__);
return mmc_resp;
}
/**
* @brief Convert response from Renesas MMC to SDHC
*
* Function writes a response to response array of @ref sdhc_command structure
*
* @note in/out parameters should be checked by a caller function.
*
* @param dev MMC device
* @param cmd MMC command
* @param response_type SDHC response type without SPI flags
*
* @retval none
*/
static void rcar_mmc_extract_resp(const struct device *dev, struct sdhc_command *cmd,
uint32_t response_type)
{
if (response_type == SD_RSP_TYPE_R2) {
uint32_t rsp_127_104 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP76);
uint32_t rsp_103_72 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP54);
uint32_t rsp_71_40 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP32);
uint32_t rsp_39_8 = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP10);
cmd->response[0] = (rsp_39_8 & 0xffffff) << 8;
cmd->response[1] =
((rsp_71_40 & 0x00ffffff) << 8) | ((rsp_39_8 & 0xff000000) >> 24);
cmd->response[2] =
((rsp_103_72 & 0x00ffffff) << 8) | ((rsp_71_40 & 0xff000000) >> 24);
cmd->response[3] =
((rsp_127_104 & 0x00ffffff) << 8) | ((rsp_103_72 & 0xff000000) >> 24);
LOG_DBG("Response 2\n\t[0]: 0x%08x\n\t[1]: 0x%08x"
"\n\t[2]: 0x%08x\n\t[3]: 0x%08x",
cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3]);
} else {
cmd->response[0] = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP10);
LOG_DBG("Response %u\n\t[0]: 0x%08x", response_type, cmd->response[0]);
}
}
/* configure CMD register for tx/rx data */
static uint32_t rcar_mmc_gen_data_cmd(struct sdhc_command *cmd, struct sdhc_data *data)
{
uint32_t cmd_reg = RCAR_MMC_CMD_DATA;
switch (cmd->opcode) {
case MMC_SEND_EXT_CSD:
case SD_READ_SINGLE_BLOCK:
case MMC_SEND_TUNING_BLOCK:
case SD_SEND_TUNING_BLOCK:
case SD_SWITCH:
case SD_APP_SEND_NUM_WRITTEN_BLK:
case SD_APP_SEND_SCR:
cmd_reg |= RCAR_MMC_CMD_RD;
break;
case SD_READ_MULTIPLE_BLOCK:
cmd_reg |= RCAR_MMC_CMD_RD;
cmd_reg |= RCAR_MMC_CMD_MULTI;
break;
case SD_WRITE_MULTIPLE_BLOCK:
cmd_reg |= RCAR_MMC_CMD_MULTI;
break;
case SD_WRITE_SINGLE_BLOCK:
/* fall through */
default:
break;
}
if (data->blocks > 1) {
cmd_reg |= RCAR_MMC_CMD_MULTI;
}
return cmd_reg;
}
/**
* @brief Transmit/Receive data to/from MMC using DMA
*
* Sends/Receives data to/from the MMC controller.
*
* @note in/out parameters should be checked by a caller function.
*
* @param dev MMC device
* @param data MMC data buffer for tx/rx
* @param is_read it is read or write operation
*
* @retval 0 tx/rx was successful
* @retval -ENOTSUP: cache flush/invalidate aren't supported
* @retval -ETIMEDOUT: timed out while tx/rx
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_dma_rx_tx_data(const struct device *dev, struct sdhc_data *data, bool is_read)
{
uintptr_t dma_addr;
uint32_t reg;
int ret = 0;
uint32_t dma_info1_poll_flag;
#ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
struct mmc_rcar_data *dev_data = dev->data;
#endif
ret = sys_cache_data_flush_range(data->data, data->blocks * data->block_size);
if (ret < 0) {
LOG_ERR("%s: can't invalidate data cache before write", dev->name);
return ret;
}
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_MODE);
if (is_read) {
dma_info1_poll_flag = RCAR_MMC_DMA_INFO1_END_RD2;
reg |= RCAR_MMC_DMA_MODE_DIR_RD;
} else {
dma_info1_poll_flag = RCAR_MMC_DMA_INFO1_END_WR;
reg &= ~RCAR_MMC_DMA_MODE_DIR_RD;
}
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_MODE, reg);
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_EXTMODE);
reg |= RCAR_MMC_EXTMODE_DMA_EN;
rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, reg);
dma_addr = z_mem_phys_addr(data->data);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_ADDR_L, dma_addr);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_ADDR_H, 0);
#ifdef CONFIG_RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
rcar_mmc_write_reg32(
dev, RCAR_MMC_DMA_INFO2_MASK,
(uint32_t)(is_read ? (~RCAR_MMC_DMA_INFO2_ERR_RD) : (~RCAR_MMC_DMA_INFO2_ERR_WR)));
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO1_MASK);
reg &= ~dma_info1_poll_flag;
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, reg);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_CTL, RCAR_MMC_DMA_CTL_START);
ret = k_sem_take(&dev_data->irq_xref_fin, K_MSEC(data->timeout_ms));
if (ret < 0) {
LOG_ERR("%s: interrupt signal timeout error %d", dev->name, ret);
}
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_DMA_INFO2);
if (reg) {
LOG_ERR("%s: an error occurs on the DMAC channel #%u", dev->name,
(reg & RCAR_MMC_DMA_INFO2_ERR_RD) ? 1U : 0U);
ret = -EIO;
}
#else
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_CTL, RCAR_MMC_DMA_CTL_START);
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_DMA_INFO1, dma_info1_poll_flag,
dma_info1_poll_flag, false, true,
data->timeout_ms * 1000LL);
#endif
if (is_read) {
if (sys_cache_data_invd_range(data->data, data->blocks * data->block_size) < 0) {
LOG_ERR("%s: can't invalidate data cache after read", dev->name);
}
}
/* in case when we get to here and there wasn't IRQ trigger */
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO1_MASK, 0xfffffeff);
rcar_mmc_write_reg32(dev, RCAR_MMC_DMA_INFO2_MASK, ~0);
if (ret == -EIO) {
rcar_mmc_reset_dma(dev);
}
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_EXTMODE);
reg &= ~RCAR_MMC_EXTMODE_DMA_EN;
rcar_mmc_write_reg32(dev, RCAR_MMC_EXTMODE, reg);
return ret;
}
/* read from SD/MMC controller buf0 register */
static inline uint64_t rcar_mmc_read_buf0(const struct device *dev)
{
uint64_t buf0 = 0ULL;
struct mmc_rcar_data *dev_data = dev->data;
uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
mm_reg_t buf0_addr = DEVICE_MMIO_GET(dev) + RCAR_MMC_BUF0;
switch (sd_buf0_size) {
case 8:
buf0 = sys_read64(buf0_addr);
break;
case 4:
buf0 = sys_read32(buf0_addr);
break;
case 2:
buf0 = sys_read16(buf0_addr);
break;
default:
k_panic();
break;
}
return buf0;
}
/* write to SD/MMC controller buf0 register */
static inline void rcar_mmc_write_buf0(const struct device *dev, uint64_t val)
{
struct mmc_rcar_data *dev_data = dev->data;
uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
mm_reg_t buf0_addr = DEVICE_MMIO_GET(dev) + RCAR_MMC_BUF0;
switch (sd_buf0_size) {
case 8:
sys_write64(val, buf0_addr);
break;
case 4:
sys_write32(val, buf0_addr);
break;
case 2:
sys_write16(val, buf0_addr);
break;
default:
k_panic();
break;
}
}
/**
* @brief Transmit/Receive data to/from MMC without DMA
*
* Sends/Receives data to/from the MMC controller.
*
* @note in/out parameters should be checked by a caller function.
*
* @param dev MMC device
* @param data MMC data buffer for tx/rx
* @param is_read it is read or write operation
*
* @retval 0 tx/rx was successful
* @retval -EINVAL: invalid block size
* @retval -ETIMEDOUT: timed out while tx/rx
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_sd_buf_rx_tx_data(const struct device *dev, struct sdhc_data *data,
bool is_read)
{
struct mmc_rcar_data *dev_data = dev->data;
uint32_t block;
int ret = 0;
uint32_t info2_poll_flag = is_read ? RCAR_MMC_INFO2_BRE : RCAR_MMC_INFO2_BWE;
uint8_t sd_buf0_size = dev_data->width_access_sd_buf0;
uint16_t aligned_block_size = ROUND_UP(data->block_size, sd_buf0_size);
uint32_t cmd_reg = 0;
int64_t remaining_timeout_us = data->timeout_ms * 1000LL;
/*
* note: below code should work for all possible block sizes, but
* we need below check, because code isn't tested with smaller
* block sizes.
*/
if ((data->block_size % dev_data->width_access_sd_buf0) ||
(data->block_size < dev_data->width_access_sd_buf0)) {
LOG_ERR("%s: block size (%u) less or not align on SD BUF0 access width (%hhu)",
dev->name, data->block_size, dev_data->width_access_sd_buf0);
return -EINVAL;
}
/*
* JEDEC Standard No. 84-B51
* 6.6.24 Dual Data Rate mode operation:
* Therefore, all single or multiple block data transfer read or write will operate on
* a fixed block size of 512 bytes while the Device remains in dual data rate.
*
* Physical Layer Specification Version 3.01
* 4.12.6 Timing Changes in DDR50 Mode
* 4.12.6.2 Protocol Principles
* * Read and Write data block length size is always 512 bytes (same as SDHC).
*/
if (dev_data->ddr_mode && data->block_size != 512) {
LOG_ERR("%s: block size (%u) isn't equal to 512 in DDR mode", dev->name,
data->block_size);
return -EINVAL;
}
/*
* note: the next restrictions we have according to description of
* transfer data length register from R-Car S4 series User's Manual
*/
if (data->block_size > 512 || data->block_size == 0) {
LOG_ERR("%s: block size (%u) must not be bigger than 512 bytes and equal to zero",
dev->name, data->block_size);
return -EINVAL;
}
cmd_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_CMD);
if (cmd_reg & RCAR_MMC_CMD_MULTI) {
/* CMD12 is automatically issued at multiple block transfer */
if (!(cmd_reg & RCAR_MMC_CMD_NOSTOP) && data->block_size != 512) {
LOG_ERR("%s: illegal block size (%u) for multi-block xref with CMD12",
dev->name, data->block_size);
return -EINVAL;
}
switch (data->block_size) {
case 32:
case 64:
case 128:
case 256:
case 512:
break;
default:
LOG_ERR("%s: illegal block size (%u) for multi-block xref without CMD12",
dev->name, data->block_size);
return -EINVAL;
}
}
if (data->block_size == 1 && dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) {
LOG_ERR("%s: block size can't be equal to 1 with 8-bits bus width", dev->name);
return -EINVAL;
}
for (block = 0; block < data->blocks; block++) {
uint8_t *buf = (uint8_t *)data->data + (block * data->block_size);
uint32_t info2_reg;
uint16_t w_off; /* word offset in a block */
uint64_t start_block_xref_us = k_ticks_to_us_ceil64(k_uptime_ticks());
/* wait until the buffer is filled with data */
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, info2_poll_flag,
info2_poll_flag, true, false,
remaining_timeout_us);
if (ret) {
return ret;
}
/* clear write/read buffer ready flag */
info2_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO2);
info2_reg &= ~info2_poll_flag;
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO2, info2_reg);
for (w_off = 0; w_off < aligned_block_size; w_off += sd_buf0_size) {
uint64_t buf0 = 0ULL;
uint8_t copy_size = MIN(sd_buf0_size, data->block_size - w_off);
if (is_read) {
buf0 = rcar_mmc_read_buf0(dev);
memcpy(buf + w_off, &buf0, copy_size);
} else {
memcpy(&buf0, buf + w_off, copy_size);
rcar_mmc_write_buf0(dev, buf0);
}
}
remaining_timeout_us -=
k_ticks_to_us_ceil64(k_uptime_ticks()) - start_block_xref_us;
if (remaining_timeout_us < 0) {
return -ETIMEDOUT;
}
}
return ret;
}
/**
* @brief Transmit/Receive data to/from MMC
*
* Sends/Receives data to/from the MMC controller.
*
* @note in/out parameters should be checked by a caller function.
*
* @param dev MMC device
* @param data MMC data buffer for tx/rx
* @param is_read it is read or write operation
*
* @retval 0 tx/rx was successful
* @retval -EINVAL: invalid block size
* @retval -ETIMEDOUT: timed out while tx/rx
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_rx_tx_data(const struct device *dev, struct sdhc_data *data, bool is_read)
{
uint32_t info1_reg;
int ret = 0;
#ifdef CONFIG_RCAR_MMC_DMA_SUPPORT
if (!(z_mem_phys_addr(data->data) >> 32)) {
ret = rcar_mmc_dma_rx_tx_data(dev, data, is_read);
} else
#endif
{
ret = rcar_mmc_sd_buf_rx_tx_data(dev, data, is_read);
}
if (ret < 0) {
return ret;
}
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO1, RCAR_MMC_INFO1_CMP,
RCAR_MMC_INFO1_CMP, true, false,
MMC_POLL_FLAGS_TIMEOUT_US);
if (ret) {
return ret;
}
/* clear access end flag */
info1_reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO1);
info1_reg &= ~RCAR_MMC_INFO1_CMP;
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, info1_reg);
return ret;
}
/**
* @brief Send command to MMC
*
* Sends a command to the MMC controller.
*
* @param dev MMC device
* @param cmd MMC command
* @param data MMC data. Leave NULL to send SD command without data.
*
* @retval 0 command was sent successfully
* @retval -ETIMEDOUT: command timed out while sending
* @retval -ENOTSUP: host controller does not support command
* @retval -EIO: I/O error
* @retval -EILSEQ: communication out of sync
*/
static int rcar_mmc_request(const struct device *dev, struct sdhc_command *cmd,
struct sdhc_data *data)
{
int ret = -ENOTSUP;
uint32_t reg;
uint32_t response_type;
bool is_read = true;
int attempts;
struct mmc_rcar_data *dev_data;
if (!dev || !cmd) {
return -EINVAL;
}
dev_data = dev->data;
response_type = cmd->response_type & SDHC_NATIVE_RESPONSE_MASK;
attempts = cmd->retries + 1;
while (ret && attempts-- > 0) {
if (ret != -ENOTSUP) {
rcar_mmc_reset(dev);
#ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
rcar_mmc_retune_if_needed(dev, true);
#endif
}
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_CBSY, 0,
false, false, MMC_POLL_FLAGS_TIMEOUT_US);
if (ret) {
ret = -EBUSY;
continue;
}
rcar_mmc_reset_and_mask_irqs(dev);
rcar_mmc_write_reg32(dev, RCAR_MMC_ARG, cmd->arg);
reg = cmd->opcode;
if (data) {
rcar_mmc_write_reg32(dev, RCAR_MMC_SIZE, data->block_size);
rcar_mmc_write_reg32(dev, RCAR_MMC_SECCNT, data->blocks);
reg |= rcar_mmc_gen_data_cmd(cmd, data);
is_read = (reg & RCAR_MMC_CMD_RD) ? true : false;
}
/* CMD55 is always sended before ACMD */
if (dev_data->is_last_cmd_app_cmd) {
reg |= RCAR_MMC_CMD_APP;
}
ret = rcar_mmc_convert_sd_to_mmc_resp(response_type);
if (ret < 0) {
/* don't need to retry we will always have the same result */
return -EINVAL;
}
reg |= ret;
LOG_DBG("(SD_CMD=%08x, SD_ARG=%08x)", cmd->opcode, cmd->arg);
rcar_mmc_write_reg32(dev, RCAR_MMC_CMD, reg);
/* wait until response end flag is set or errors occur */
ret = rcar_mmc_poll_reg_flags_check_err(dev, RCAR_MMC_INFO1, RCAR_MMC_INFO1_RSP,
RCAR_MMC_INFO1_RSP, true, false,
cmd->timeout_ms * 1000LL);
if (ret) {
continue;
}
/* clear response end flag */
reg = rcar_mmc_read_reg32(dev, RCAR_MMC_INFO1);
reg &= ~RCAR_MMC_INFO1_RSP;
rcar_mmc_write_reg32(dev, RCAR_MMC_INFO1, reg);
rcar_mmc_extract_resp(dev, cmd, response_type);
if (data) {
ret = rcar_mmc_rx_tx_data(dev, data, is_read);
if (ret) {
continue;
}
}
/* wait until the SD bus (CMD, DAT) is free or errors occur */
ret = rcar_mmc_poll_reg_flags_check_err(
dev, RCAR_MMC_INFO2, RCAR_MMC_INFO2_SCLKDIVEN, RCAR_MMC_INFO2_SCLKDIVEN,
true, false, MMC_POLL_FLAGS_TIMEOUT_US);
}
if (ret) {
rcar_mmc_reset(dev);
#ifdef CONFIG_RCAR_MMC_SCC_SUPPORT
rcar_mmc_retune_if_needed(dev, true);
#endif
}
dev_data->is_last_cmd_app_cmd = (cmd->opcode == SD_APP_CMD);
return ret;
}
/* convert sd_voltage to string */
static inline const char *const rcar_mmc_get_signal_voltage_str(enum sd_voltage voltage)
{
static const char *const sig_vol_str[] = {
[0] = "Unset", [SD_VOL_3_3_V] = "3.3V", [SD_VOL_3_0_V] = "3.0V",
[SD_VOL_1_8_V] = "1.8V", [SD_VOL_1_2_V] = "1.2V",
};
if (voltage >= 0 && voltage < ARRAY_SIZE(sig_vol_str)) {
return sig_vol_str[voltage];
} else {
return "Unknown";
}
}
/* convert sdhc_timing_mode to string */
static inline const char *const rcar_mmc_get_timing_str(enum sdhc_timing_mode timing)
{
static const char *const timing_str[] = {
[0] = "Unset",
[SDHC_TIMING_LEGACY] = "LEGACY",
[SDHC_TIMING_HS] = "HS",
[SDHC_TIMING_SDR12] = "SDR12",
[SDHC_TIMING_SDR25] = "SDR25",