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Issues list

On-save regenerating of Verilog/VHDL files enhancement New feature or request good first issue Good for newcomers
#30 opened Nov 13, 2024 by VonTum
"extern" verilog modules, include parameters enhancement New feature or request good first issue Good for newcomers Systementwurf
#25 opened Nov 12, 2024 by VonTum
Resource usage reporting on hover enhancement New feature or request good first issue Good for newcomers
#24 opened Nov 9, 2024 by VonTum
5 tasks
VHDL Backend enhancement New feature or request good first issue Good for newcomers Systementwurf
#23 opened Nov 9, 2024 by VonTum
@IBims1NicerTobi
1
Distinguish between regular comments and doc-comments documentation Improvements or additions to documentation enhancement New feature or request good first issue Good for newcomers
#20 opened Nov 4, 2024 by VonTum
Global constants should have "gen" on hover bug Something isn't working good first issue Good for newcomers
#15 opened Oct 23, 2024 by VonTum
Modules that have at least one domain specified may not include ports not part of a named domain bug Something isn't working good first issue Good for newcomers
#13 opened Oct 20, 2024 by VonTum
Namespaces good first issue Good for newcomers
#12 opened Oct 11, 2024 by VonTum
Implement Multi-Clock enhancement New feature or request good first issue Good for newcomers Request Input These are issues about the design of the language, and thus should be discussed
#7 opened Aug 24, 2024 by VonTum
6 tasks
List of "Guaranteed Optimizations" in SUS good first issue Good for newcomers Request Input These are issues about the design of the language, and thus should be discussed
#4 opened Aug 13, 2024 by VonTum
Split overloaded if construct into if and when for compiletime and runtime conditions good first issue Good for newcomers Systementwurf
#3 opened Aug 12, 2024 by VonTum
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