Fix signal valid when bit stuffing

pbing · pbing · commit 6043db5f1c8b · 2018-10-03T14:20:59.000+02:00
diff --git a/rtl/usb_rx.sv b/rtl/usb_rx.sv
@@ -190,7 +190,7 @@ module usb_rx
      if (reset)
        valid <= 1'b0;
      else
-       valid <= rcv_data & clk_en;
+       valid <= rcv_bit & rcv_data & clk_en;
 endmodule
 
 `resetall
