Merge branch 'develop'

Author: BenoitStef

Changelog.md

@@ -13,6 +13,12 @@
   * Added *psi\_common\_pulse\_gene - Pulse generator
   * Added max min within an array & ratio computation to determine if integer in Math package
 
+## 2.14.0
+*Added Features
+  * Added *psi\_common\_ramp\_gene - Ramp generator 
+  * Added *psi\_common\_pulse\_gene - Pulse generator
+  * Added max min within an array & ratio computation to determine if integer in Math package
+  
 ## 2.13.0
 *Added Features
   * Added *psi\_common\_trigger\_analog* - Generic Analog trigger 

doc/ch10_interfaces/ch10_6_axilite_slave_ipif.md

@@ -11,5 +11,5 @@
 This entity is equal to [psi_common_axi_slave_ipif](./ch10_5_axi_slave_ipif.md) but it does only implement the AXILite protocol (e.g. no bursts, no exclusive access, no pending transfers, etc.). See [psi_common_axi_slave_ipif](./ch10_5_axi_slave_ipif.md) for details.
 
 ***
-[Index](../psi_common_index.md) **|** Previous: [Interfaces > axi slave ipif](./ch10_5_axi_slave_ipif.md) **|**
-Next: [Miscellaneous > delay](../ch11_misc/ch11_1_delay.md)
+[Index](../psi_common_index.md) **|** Previous: [Interfaces > axi slave ipif](../ch10_interfaces/ch10_5_axi_slave_ipif.md) **|**
+Next: [Interfaces > SPI Master cfg](../ch10_interfaces/ch10_7_spi_master_cfg.md)

doc/ch10_interfaces/ch10_7_spi_master_cfg.md

@@ -0,0 +1,66 @@
+<img align="right" src="../psi_logo.png">
+
+***
+# psi_common_spi_master_cfg
+
+- VHDL source: [psi_common_spi_master_cfg.vhd](../../hdl/psi_common_spi_master_cfg.vhd)
+- Testbench: [psi_common_spi_master_cfg_tb.vhd](../../testbench/psi_common_spi_master_cfg_tb/psi_common_spi_master_cfg_tb.vhd)
+
+### Description
+
+**This component allows enlarging dynamically the bit width of the transfer via MaxTransWidth_g generic statement and TransWidth input.**
+
+The description here below is the same as *psi_common_spi_master*
+
+This entity implements a simple SPI master. All common SPI settings are
+settable to ensure the master can be configured for different
+applications.
+
+The clock and data phase is configurable according to the SPI standard
+terminology described in the picture below:
+
+<p align="center"><img src="ch10_1_fig23.png"> </p>
+<p align="center"> CPOL and CPHA meaning </p>
+
+For CPHA = 1, the sampling happens on the second edge (blue) and data is
+applied on the first edge (red). For CPHA = 0 it is the opposite way.
+
+
+
+### Generics
+
+Generics            | Description
+--------------------|---------------------------------------------------
+**ClockDivider\_g** | Ratio between *Clk* and the *SpiSck* frequency
+**MaxTransWidth\_g**| Maximum SPI Transfer width (bits per transfer)
+**CsHighCycles\_g** | Minimal number of *Cs\_n* high cycles between two transfers
+**SpiCPOL\_g**      | SPI clock polarity (see figure above)
+**SpiCPHA\_g**      | SPI sampling edge configuration (see figure above)
+**SlaveCnt\_g**     | Number of slaves to support (number of *Cs\_n* lines)
+**LsbFirst\_g**     | **False** = MSB first transmission, **True** = LSB first transmission
+**MosiIdleState\_g**| Idle state of the MOSI line
+
+### Interfaces
+
+Signal           | Direction | Width           | Description     
+-----------------|-----------|-----------------|-----------------
+ Clk             | Input     | 1               | Clock           
+ Rst             | Input     | 1               | Reset (active high)
+ Start           | Input     | 1               | A high pulse on this line starts the transfer. Note that starting a transaction is  only possible when *Busy* is low.
+ Slave           | Input     | log2(SlaveCnt\_ g) | Slave number to access  
+ Busy            | Output    | 1               | High during a transaction     
+ Done            | Output    | 1               | Pulse that goes high for exactly one clock cycle after a transaction is done and *RdData* is valid        
+ WrData          | Input     | *MaxTransWidth\_g* | Data to send to  slave. Sampled  during *Start = '1'*     
+ TransWidth      | Input  	 | log2ceil(MaxTransWidth\_g)   | indicate the actual vector length to forward/receive
+ RdData          | Output    | *MaxTransWidth\_g* | Data received from slave. Must be sampled during *Done = '1'* or *Busy = '0'*.          
+ SpiSck          | Output    | 1               | SPI clock      
+ SpiMosi         | Output    | 1               | SPI master to slave data signal         
+ SpiMiso         | Input     | 1               | SPI slave to master data signal          
+ SpiCs\_n        | Output    | *SlaveCnt\_g*   | SPI slave select signal (low active)
+
+
+<p align="center"><img src="ch10_1_fig24.png"> </p>
+<p align="center"> Parallel interface signal behavior </p>
+
+***
+[Index](../psi_common_index.md) **|** Previous: [Interfaces > axilite slave ipif](./ch10_6_axilite_slave_ipif.md) **|** Next: [Miscellaneous > delay](../ch11_misc/ch11_1_delay.md)

doc/ch11_misc/ch11.vsd

@@ -40,4 +40,4 @@ busy_o 	| output    |1   	 	 | set to 1 when the block is in process
 str_o  	| output    |1   	 	 |  strobe Output
 dat_o   | output    | length_g   |  data output
 
-[Index](../psi_common_index.md) **|** Previous: [Misc > ramp generator](../ch11_misc/ch11_12_ramp_gene.md)
+[Index](../psi_common_index.md) **|** Previous: [Misc > ramp generator](../ch11_misc/ch11_12_ramp_gene.md) **|** Next: [Misc > parallel to serial](../ch11_misc/ch11_14_par_ser.md)

doc/ch11_misc/ch11_13_pulse_generator_ctrl_static.md

@@ -0,0 +1,43 @@
+<img align="right" src="../psi_logo.png">
+
+***
+# psi_common_par_ser
+
+- VHDL source: [psi_common_par_ser.vhd](../../hdl/psi_common_par_ser.vhd)
+- Testbench:  [psi_common_par_ser_tb.vhd](../../testbench/psi_common_par_ser_tb/psi_common_par_ser_tb.vhd)
+
+### Description
+This component implements a serializer from a vector, the user indicates either the MSB either LSB are forwarded first with MSB_g generic. The serializer can run at full/clock speed  under one condition is that the input data is sampled at N times lower than the serialized bit where N is the vector input length; if a valid input arrives before this time an error flag is aroused.
+Additionally a frame output flag is given at the last serialized bit and a load output is also given at the first output bit. The valid stays high for one clock cycle at each new bit produced.
+
+#### throughput divided by 3 related to clock cycle frequency
+<p align="center"><img src="ch11_14_fig52.png"></p>
+
+#### highest throughput datagram
+<p align="center"><img src="ch11_14_fig53.png"></p>
+
+### Generics
+
+Generics        | Description
+----------------|------------------------------
+**rst\_pol\_g** |reset polarity ('1' or '0')
+**msb\_g** 			|MSB first output if true
+**ratio\_g** 		|slow the serialized dat output with ratio to clock freq
+**length\_g** 	|Width of the data in bits
+
+
+### Interfaces
+
+Signal  |Direction  |Width   |Description
+--------|-----------|--------|---------------------------------
+clk_i  	|Input      |1       |Clock
+rst_i  	|Input      |1       |Reset
+dat_i  	|Input      |length_g|data vector input to serialize
+vld_i   |Input      |1			 |strobe input
+vld_o 	|Input 			|1			 |strobe output
+dat_o 	|Input 	  	|1			 |data bit output
+ld_o    |Input 		  |1 			 |flag load output is high at first output bit
+frm_o  	| output    |1   	   |flag frame output is high at last output bit
+err_o  	| output    |1   	   |error occurs when *vld_i* arrives before the serializing ended
+
+[Index](../psi_common_index.md) **|** Previous: [Misc > Pulse generator ctrl static](../ch11_misc/ch11_13_pulse_generator_ctrl_static.md) **|** Next [Misc > Serial to parallel](../ch11_misc/ch11_15_ser_par.md)

doc/ch11_misc/ch11_14_fig52.png

@@ -0,0 +1,37 @@
+<img align="right" src="../psi_logo.png">
+
+***
+# psi_common_par_ser
+
+- VHDL source: [psi_common_ser_par.vhd](../../hdl/psi_common_ser_par.vhd)
+- Testbench:  [psi_common_ser_par_tb.vhd](../../testbench/psi_common_ser_par_tb/psi_common_ser_par_tb.vhd)
+
+### Description
+This component implements a deserializer, the user indicates either the MSB or LSB are received first with **MSB_g** generic. The deserializer can run at full/clock speed  under one condition is that the input data is sampled at N times lower than the serialized bit where N is the vector input length **ld_i** is used to determine the input sampling frequency; However it is not required to process data. If a load input arrives before this the full de-serializing process has ended up an error flag is aroused.
+
+#### throughput divided by 3 related to clock cycle frequency
+<p align="center"><img src="ch11_15_fig54.png"></p>
+
+### Generics
+
+Generics        | Description
+----------------|------------------------------
+**rst\_pol\_g** |reset polarity ('1' or '0')
+**msb\_g** 			|MSB first output if true
+**length\_g** 	|Width of the data in bits
+
+
+### Interfaces
+
+Signal  |Direction  |Width   |Description
+--------|-----------|--------|---------------------------------
+clk_i  	|Input      |1       |Clock
+rst_i  	|Input      |1       |Reset
+dat_i  	|Input      |1			 |data bit input to de-serialize
+vld_i   |Input      |1			 |strobe input
+vld_o 	|Input 			|1			 |strobe output
+dat_o 	|Input 	  	|length_g|data bit output
+ld_o    |Input 		  |1 			 |flag load output is high at first output bit
+err_o  	| output    |1   	   |error occurs when *ld_i* arrives before the de-serializing ended
+
+[Index](../psi_common_index.md) **|** Previous:  [Misc > Parallel to serial](../ch11_misc/ch11_14_par_ser.md)