BUGFIX: fixed psi_common_prbs_tb

Author: rybaniec-r

README.md

@@ -9,6 +9,7 @@ Benoît Stef [benoit.stef@psi.ch]
 * Daniele Felici [daniele.felici@psi.ch]
 * Patric Bucher [patric.bucher@psi.ch]
 * Rafael Basso [rafael.basso@psi.ch]
+* Radoslaw Rybaniec [radoslaw.rybaniec@psi.ch]
 
 ## License
 This library is published under [PSI HDL Library License](License.txt), which is [LGPL](LGPL2_1.txt) plus some additional exceptions to clarify the LGPL terms in the context of firmware development.

sim/config.tcl

@@ -452,8 +452,6 @@ add_tb_run
 
 create_tb_run "psi_common_prbs_tb"
 tb_run_add_arguments \
-	"-gwidth_g=8 -gseed_g=x\"00000015\"" \
-	"-gwidth_g=8 -gseed_g=x\"00000006\"" \
-	"-gwidth_g=12 -gseed_g=x\"00000F01\"" \
-  "-gwidth_g=12 -gseed_g=x\"00000031\""
-add_tb_run
+	"-gwidth_g=10 -gseed_g=x\"00000015\"" \
+	"-gwidth_g=10 -gseed_g=x\"00000006\""
+add_tb_run

testbench/psi_common_prbs_tb/maximal_length_lfsr.vhd

@@ -1,3 +1,13 @@
+----------------------------------------------------------------------------------
+-- Original VHDL source code Copyright 1995-2021 DOULOS
+----------------------------------------------------------------------------------
+-- Copyright (c) 2023 by Paul Scherrer Institute, Switzerland
+-- All rights reserved.
+-- Authors: Rafael Basso, Radoslaw Rybaniec
+
+-- Added seed input
+----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 
@@ -22,7 +32,7 @@ begin
   begin
     if RISING_EDGE(clock) then
       if reset = '1' then
-        lfsr_reg <= (others => '1');
+        lfsr_reg <= seed;
       else
         if str = '1' then
           lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);

testbench/psi_common_prbs_tb/psi_common_prbs_tb.vhd

@@ -1,7 +1,7 @@
 ----------------------------------------------------------------------------------
 -- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
 -- All rights reserved.
--- Authors: Rafael Basso
+-- Authors: Rafael Basso, Radoslaw Rybaniec
 ----------------------------------------------------------------------------------
 
 ----------------------------------------------------------------------------------
@@ -114,27 +114,20 @@ begin
 
   -- Assertion process : It stores the first CYCLE generated data and then compares it
   -- with the next CYCLE generated data. The same data is expected.
-  assrt_p : process(data)
+  assrt_p : process(clk)
   begin
     if (rst = '0') then
-      if (count < CYCLE - 1) then
-        count <= count + 1;
-      elsif (flag = '0') then
-        flag  <= '1';
-        count <= 0;
-      else
-        done <= '1';
-      end if;
-
-      if (flag = '1') then
-        if width_g < 20 then
-          assert data = mem(count) report "###ERROR### Mismatch on data!" severity error;
-        elsif width_g = 10 then
+      if rising_edge(clk) then
+        if ostrb = '1' then
           StdlvCompareStdlv(data_test, data,"Mismatch data for PRBS-9");
+          count <= count + 1;
+        end if;
+        if count = 1000 then
+          done <= '1';
         end if;
-      else
-        mem(count) <= data;
       end if;
+    else  -- reset
+      count <= 0;
     end if;
   end process;
 
@@ -153,12 +146,18 @@ begin
   -----------------------------------------------------------
   -- TAG : check with doulos 10 bit lfsr version & seed FF
   -----------------------------------------------------------
-  u_test : entity work.maximal_length_lfsr
+  assert N = 10 report "Testbench supports only width_g = 10 bits" severity failure;
+  
+  GEN_LFSR: if N = 10 generate
+    u_test : entity work.maximal_length_lfsr
     port map(
       clock    => clk,
       reset    => rst,
-      seed     => seed(9 downto 0),
+      seed     => seed(N-1 downto 0),
       str      => istrb,
-      data_out => data_test);
 
+      
+      data_out => data_test);
+  end generate GEN_LFSR;
+       
 end behav;