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BenoitStefBenoitStef
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Bugfixes: reset polarity simple cc and async fifo
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‎.gitignore‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,3 +4,6 @@
44
#Pycharm project files
55
**/.idea
66
*.pyc
7+
8+
#Sim
9+
sim/wlf*

‎Changelog.md‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,10 @@
1+
## 3.0.1
2+
* Bugfixes
3+
* pulse_cc add testbench to check reset crossing and correct polarity handling
4+
* modify simple_cc_tb to cope with bugfix in pulse_cc
5+
* correct async fifo to work with reset polarity neg
6+
* add few polarity check in test regression config.tcl
7+
18
## 3.0.0
29
* Cleaning
310
* All codes have been unified for better readibility and all tabs have been removed

‎hdl/psi_common_async_fifo.vhd‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ begin
141141
end if;
142142
end if;
143143
-- Artificially keep InRdy low during reset if required
144-
if (rdy_rst_state_g = '0') and (RstInInt = '1') then
144+
if (rdy_rst_state_g = '0') and (RstInInt = rst_pol_g) then
145145
in_rdy_o <= '0';
146146
end if;
147147

@@ -272,6 +272,10 @@ begin
272272

273273
-- only used for reset crossing and oring
274274
i_rst_cc : entity work.psi_common_pulse_cc
275+
generic map(
276+
a_rst_pol_g => rst_pol_g,
277+
b_rst_pol_g => rst_pol_g
278+
)
275279
port map(
276280
-- Clock Domain A
277281
a_clk_i => in_clk_i,

‎hdl/psi_common_pulse_cc.vhd‎

Lines changed: 54 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ use ieee.numeric_std.all;
2222
entity psi_common_pulse_cc is
2323
generic(num_pulses_g : positive := 1; -- fifo width
2424
a_rst_pol_g : std_logic:= '1'; -- rst polarity port A
25-
b_rst_pol_g : std_logic:='1' ); -- rst polarity port B
25+
b_rst_pol_g : std_logic:= '1'); -- rst polarity port B
2626
port( a_clk_i : in std_logic; -- clock port a input
2727
a_rst_i : in std_logic; -- rst input port a
2828
a_rst_o : out std_logic; -- Clock domain A reset output, active if *a_rst_i* or *b_rst_i* is asserted, de-asserted synchronously to *a_clk_i*
@@ -40,76 +40,104 @@ architecture rtl of psi_common_pulse_cc is
4040

4141
-- Domain A signals
4242
signal RstSyncB2A : std_logic_vector(3 downto 0);
43-
signal RstAI : std_logic;
43+
signal RstAI : std_logic := a_rst_pol_g;
4444
-- Domain B signals
4545
signal RstSyncA2B : std_logic_vector(3 downto 0);
46-
signal RstBI : std_logic;
46+
signal RstBI : std_logic := b_rst_pol_g;
4747
-- Data transmit side
4848
signal ToggleA : std_logic_vector(num_pulses_g - 1 downto 0);
4949
-- Data receive side
5050
signal ToggleSyncB : Pulse_t(2 downto 0);
5151

52-
attribute syn_srlstyle : string;
53-
attribute syn_srlstyle of RstSyncB2A : signal is "registers";
54-
attribute syn_srlstyle of RstSyncA2B : signal is "registers";
55-
attribute syn_srlstyle of ToggleA : signal is "registers";
52+
attribute syn_srlstyle : string;
53+
attribute syn_srlstyle of RstSyncB2A : signal is "registers";
54+
attribute syn_srlstyle of RstSyncA2B : signal is "registers";
55+
attribute syn_srlstyle of ToggleA : signal is "registers";
5656
attribute syn_srlstyle of ToggleSyncB : signal is "registers";
5757

58-
attribute shreg_extract : string;
58+
attribute shreg_extract : string;
5959
attribute shreg_extract of RstSyncB2A : signal is "no";
6060
attribute shreg_extract of RstSyncA2B : signal is "no";
61-
attribute shreg_extract of ToggleA : signal is "no";
62-
attribute shreg_extract of ToggleSyncB : signal is "no";
61+
attribute shreg_extract of ToggleA : signal is "no";
62+
attribute shreg_extract of ToggleSyncB: signal is "no";
6363

64-
attribute ASYNC_REG : string;
65-
attribute ASYNC_REG of RstSyncB2A : signal is "TRUE";
66-
attribute ASYNC_REG of RstSyncA2B : signal is "TRUE";
67-
attribute ASYNC_REG of ToggleA : signal is "TRUE";
68-
attribute ASYNC_REG of ToggleSyncB : signal is "TRUE";
64+
attribute ASYNC_REG : string;
65+
attribute ASYNC_REG of RstSyncB2A : signal is "TRUE";
66+
attribute ASYNC_REG of RstSyncA2B : signal is "TRUE";
67+
attribute ASYNC_REG of ToggleA : signal is "TRUE";
68+
attribute ASYNC_REG of ToggleSyncB : signal is "TRUE";
6969

7070
begin
7171

7272
-- Domain A reset sync
7373
ARstSync_p : process(a_clk_i, b_rst_i)
7474
begin
7575
if b_rst_i = b_rst_pol_g then
76-
RstSyncB2A <= (others => '1');
76+
RstSyncB2A <= (others => b_rst_pol_g);
7777
elsif rising_edge(a_clk_i) then
78-
RstSyncB2A <= RstSyncB2A(RstSyncB2A'left - 1 downto 0) & '0';
78+
RstSyncB2A <= RstSyncB2A(RstSyncB2A'left - 1 downto 0) & not b_rst_pol_g;
7979
end if;
8080
end process;
81+
8182
ARst_p : process(a_clk_i)
8283
begin
8384
if rising_edge(a_clk_i) then
8485
if a_rst_pol_g = '1' then
85-
RstAI <= RstSyncB2A(RstSyncB2A'left) or a_rst_i;
86+
if b_rst_pol_g = '1' then
87+
RstAI <= RstSyncB2A(RstSyncB2A'left) or a_rst_i;
88+
else
89+
RstAI <= RstSyncB2A(RstSyncB2A'left) and a_rst_i;
90+
end if;
8691
else
87-
RstAI <= RstSyncB2A(RstSyncB2A'left) and a_rst_i;
92+
if b_rst_pol_g = '1' then
93+
RstAI <= RstSyncB2A(RstSyncB2A'left) or a_rst_i;
94+
else
95+
RstAI <= RstSyncB2A(RstSyncB2A'left) and a_rst_i;
96+
end if;
8897
end if;
8998
end if;
9099
end process;
91-
a_rst_o <= RstAI;
100+
gene_a_rst_o : if a_rst_pol_g = '1' generate
101+
a_rst_o <= RstAI or a_rst_i;
102+
end generate;
103+
gene_a_rst_o_neg : if a_rst_pol_g = '0' generate
104+
a_rst_o <= RstAI and a_rst_i;
105+
end generate;
92106

93107
-- Domain B reset sync
94108
BRstSync_p : process(b_clk_i, a_rst_i)
95109
begin
96110
if a_rst_i = a_rst_pol_g then
97-
RstSyncA2B <= (others => '1');
111+
RstSyncA2B <= (others => a_rst_pol_g);
98112
elsif rising_edge(b_clk_i) then
99-
RstSyncA2B <= RstSyncA2B(RstSyncA2B'left - 1 downto 0) & '0';
113+
RstSyncA2B <= RstSyncA2B(RstSyncA2B'left - 1 downto 0) & not a_rst_pol_g;
100114
end if;
101115
end process;
116+
102117
BRst_p : process(b_clk_i)
103118
begin
104119
if rising_edge(b_clk_i) then
105120
if b_rst_pol_g = '1' then
106-
RstBI <= RstSyncA2B(RstSyncA2B'left) or b_rst_i;
121+
if a_rst_pol_g = '1' then
122+
RstBI <= RstSyncA2B(RstSyncA2B'left) or b_rst_i;
123+
else
124+
RstBI <= RstSyncA2B(RstSyncA2B'left) and b_rst_i;
125+
end if;
107126
else
108-
RstBI <= RstSyncA2B(RstSyncA2B'left) and b_rst_i;
127+
if a_rst_pol_g = '1' then
128+
RstBI <= RstSyncA2B(RstSyncA2B'left) or b_rst_i;
129+
else
130+
RstBI <= RstSyncA2B(RstSyncA2B'left) and b_rst_i;
131+
end if;
109132
end if;
110133
end if;
111134
end process;
112-
b_rst_o <= RstBI;
135+
gene_b_rst_o : if b_rst_pol_g = '1' generate
136+
b_rst_o <= RstBI or b_rst_i;
137+
end generate;
138+
gene_b_rst_o_neg : if b_rst_pol_g = '0' generate
139+
b_rst_o <= RstBI and b_rst_i;
140+
end generate;
113141

114142
-- Pulse transmit side (A)
115143
PulseA_p : process(a_clk_i)
@@ -136,5 +164,5 @@ begin
136164
end if;
137165
end if;
138166
end process;
167+
139168
end architecture;
140-

‎sim/config.tcl‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,9 +157,23 @@ add_sources "../testbench" {
157157
psi_common_prbs_tb/maximal_length_lfsr.vhd \
158158
psi_common_prbs_tb/psi_common_prbs_tb.vhd \
159159
psi_common_pwm_tb/psi_common_pwm_tb.vhd \
160+
psi_common_pulse_cc_tb/psi_common_pulse_cc_tb.vhd \
160161
} -tag tb
161162

162163
#TB Runs
164+
165+
create_tb_run "psi_common_pulse_cc_tb"
166+
tb_run_add_arguments \
167+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='1' -gb_rst_pol_g='1' -ga_rst_before_g=true" \
168+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='0' -gb_rst_pol_g='0' -ga_rst_before_g=true" \
169+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='1' -gb_rst_pol_g='0' -ga_rst_before_g=true" \
170+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='0' -gb_rst_pol_g='1' -ga_rst_before_g=true" \
171+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='1' -gb_rst_pol_g='1' -ga_rst_before_g=false" \
172+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='0' -gb_rst_pol_g='0' -ga_rst_before_g=false" \
173+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='1' -gb_rst_pol_g='0' -ga_rst_before_g=false" \
174+
"-ga_freq_clk_g=100.0E6 -gb_freq_clk_g=50.0E6 -gnum_pulses_g=1 -ga_rst_pol_g='0' -gb_rst_pol_g='1' -ga_rst_before_g=false"
175+
add_tb_run
176+
163177
create_tb_run "psi_common_min_max_sum_tb"
164178
tb_run_add_arguments \
165179
"-gclock_cycle_g=100 -gsigned_data_g=true -gdata_length_g=16 -gaccu_length_g=64" \
@@ -245,6 +259,7 @@ add_tb_run
245259
create_tb_run "psi_common_async_fifo_tb"
246260
tb_run_add_arguments \
247261
"-gafull_on_g=true -gaempty_on_g=true -gdepth_g=32 -gram_behavior_g=RBW -grdy_rst_state_g=1" \
262+
"-gafull_on_g=true -gaempty_on_g=true -gdepth_g=32 -gram_behavior_g=RBW -grdy_rst_state_g=1 -grst_pol_g='0'" \
248263
"-gafull_on_g=true -gaempty_on_g=true -gdepth_g=32 -gram_behavior_g=RBW -grdy_rst_state_g=0" \
249264
"-gafull_on_g=false -gaempty_on_g=false -gdepth_g=128 -gram_behavior_g=RBW" \
250265
"-gafull_on_g=false -gaempty_on_g=false -gdepth_g=128 -gram_behavior_g=WBR"

‎testbench/psi_common_async_fifo_tb/psi_common_async_fifo_tb.vhd‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@ entity psi_common_async_fifo_tb is
2222
aempty_on_g : boolean := true;
2323
depth_g : natural := 32;
2424
ram_behavior_g : string := "RBW";
25-
rdy_rst_state_g : integer range 0 to 1 := 1
25+
rdy_rst_state_g : integer range 0 to 1 := 1;
26+
rst_pol_g : std_logic := '1'
2627
);
2728
end entity psi_common_async_fifo_tb;
2829

@@ -50,9 +51,9 @@ architecture sim of psi_common_async_fifo_tb is
5051
-- Interface Signals
5152
-------------------------------------------------------------------------
5253
signal in_clk_i : std_logic := '0';
53-
signal in_rst_i : std_logic := '1';
54+
signal in_rst_i : std_logic := rst_pol_g;
5455
signal out_clk_i : std_logic := '0';
55-
signal out_rst_i : std_logic := '1';
56+
signal out_rst_i : std_logic := rst_pol_g;
5657
signal in_dat_i : std_logic_vector(DataWidth_c - 1 downto 0) := (others => '0');
5758
signal in_vld_i : std_logic := '0';
5859
signal in_rdy_o : std_logic := '0';
@@ -84,7 +85,8 @@ begin
8485
aempty_on_g => aempty_on_g,
8586
aempty_level_g => AlmEmptyLevel_c,
8687
ram_behavior_g => ram_behavior_g,
87-
rdy_rst_state_g => int_to_std_logic(rdy_rst_state_g)
88+
rdy_rst_state_g => int_to_std_logic(rdy_rst_state_g),
89+
rst_pol_g => rst_pol_g
8890
)
8991
port map(
9092
-- Control Ports
@@ -149,8 +151,8 @@ begin
149151
-- *** Reset Tests ***
150152
print(">> Reset");
151153
-- Reset
152-
in_rst_i <= '1';
153-
out_rst_i <= '1';
154+
in_rst_i <= rst_pol_g;
155+
out_rst_i <= rst_pol_g;
154156
-- check if ready state during reset is correct
155157
wait for 20 ns; -- reset must be transferred to other clock domain
156158
wait until rising_edge(in_clk_i);
@@ -159,9 +161,9 @@ begin
159161

160162
-- Remove reset
161163
wait until rising_edge(in_clk_i);
162-
in_rst_i <= '0';
164+
in_rst_i <= not rst_pol_g;
163165
wait until rising_edge(out_clk_i);
164-
out_rst_i <= '0';
166+
out_rst_i <= not rst_pol_g;
165167
wait for 100 ns;
166168

167169
-- Check Reset State

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