Add ramp & pulse generator (#23)

* BUGFIX: Remove VHDL-2008 statement in psi_common_tdm_par

* FEATURE: Added string->real conversion to psi_common_math_pkg

* DEVEL: Implemented choose for t_areal

* FEATURE: Selectable MOSI state furing CSn high time

Fully backwards compatible and required to control some A/D convertes (e.g. AD4010)

* FEATURE: Added dynamic shift (psi_common_dyn_sft.vhd) (#20)

Co-authored-by: Oliver Bründler <oliver.bruendler@enclustra.com>

* Devel/trigger generator (#18)

* DEVEL: psi_coomon_trigger_generator.vhd added

* DEVEL: the trigger can be disamed in continuous mode

* CLEANUP: minor modif on trigger_generator

* DEVEL: trigger_generator_tb added. DOCU: trigger_generator doc added

* BUGFIX: code improvements after comments, DOCU: format improved

* FEATURE: analog and digital trigger created.

* DOCU: documentation updated

* BUGFIX: trigger analog and digital tb fixed for run.tcl

* DEVEL: description added and _c postfix changed in _dff in triggers vhdl files

* BUGFIX: fixed a bug in config.tcl that prevents starting simulations

* IMPROVEMENT: Use attributes to always use SRLs in SRL mode for psi_common_delay

* FEATURE: ramp & pulse generator + new math function

Co-authored-by: Oliver Bründler <oliver.bruendler@enclustra.com>
Co-authored-by: Oliver Bründler <oli.bruendler@gmx.ch>
Co-authored-by: FD82 <59609467+FD82@users.noreply.github.com>

Author: 4 people

doc/ch10_interfaces/ch10_2_i2c_master.md

@@ -3,7 +3,7 @@
 ***
 # psi_common_ic2_master
 
-- VHDL source: [psi_common_i2c_master.vhd](../../hdl/psi_common_i2c_master_tb.vhd)
+- VHDL source: [psi_common_i2c_master.vhd](../../hdl/psi_common_i2c_master.vhd)
 - Testbench: [psi_common_i2c_master_tb.vhd](../../testbench/psi_common_i2c_master_tb/psi_common_i2c_master_tb.vhd)
 
 ### Description

doc/ch11_misc/ch11.vsd

@@ -31,4 +31,4 @@ InData |Input |_Width_g_ |Data Input
 OutVld |Output |1 |AXI-S handshaking signal for output
 OutData |Output |_Width\_g_ |Data Output
 
-[Index](../psi_common_index.md) **|** Previous: [Misc > trigger digital](../ch11_misc/ch11_10_trigger_digital.md)
+[Index](../psi_common_index.md) **|** Previous: [Misc > trigger digital](../ch11_misc/ch11_10_trigger_digital.md) **|** Next: [Misc > ramp generator](../ch11_misc/ch11_12_ramp_gene.md)

doc/ch11_misc/ch11_11_dyn_sft.md

@@ -0,0 +1,38 @@
+<img align="right" src="../psi_logo.png">
+
+***
+# psi_common_pulse_generator
+
+- VHDL source: [psi_common_ramp_gene.vhd](../../hdl/psi_common_ramp_gene.vhd)
+- Testbench:  [psi_common_ramp_gene_tb.vhd](../../testbench/psi_common_ramp_gene_tb/psi_common_ramp_gene_tb.vhd)
+
+### Description
+This component implements a ramp generator where the user can set the target level to reach and the step number prior to reach this level. It can from a certain value either continue ramping up either ramping down as the figure below shows. The direction is selected with the next value to reach, if current value is higher than previous one then it ramps up and opposite.
+
+<p align="center"><img src="ch11_12_fig50.png"></p>
+
+### Generics
+
+
+Generics        | Description
+----------------|-------------------------------------------------
+**rst\_pol\_g** |reset polarity ('1' or '0')
+**width\_g** 		|Width of the data in bits
+
+
+### Interfaces
+
+Signal  |Direction  |Width   |Description
+--------|-----------|--------|---------------------------------
+clk_i  			|Input      |1       |Clock
+rst_i  			|Input      |1       |Reset
+str_i  	    |Input      |1  		 |strobe input
+tgt_lvl_i   |Input      | width_g| set the level to reach (usign)
+ramp_inc_i 	|Input 			| width_g| ramp increment
+ramp_cmd_i 	|Input 	  	|1 			 | initiate a ramp up or down
+init_cmd_i  |Input 		  |1 			 | stop pulse and set output to zero
+sts_o  			| output    | 2   	 | status indicator of the internal sequencer   
+str_o  			| output    | 1   	 |  strobe Output
+puls_o  		| output    | width_g   |  data output
+
+[Index](../psi_common_index.md) **|** Previous: [Misc > dynamic shifter](../ch11_misc/ch11_11_dyn_sft.md) **|** Next: [Misc > Pulse generator ctrl static](../ch11_misc/ch11_13_pulse_generator_ctrl_static.md)

doc/ch11_misc/ch11_12_fig50.png

@@ -0,0 +1,43 @@
+<img align="right" src="../psi_logo.png">
+
+***
+# psi_common_pulse_generator_ctrl_static
+
+- VHDL source: [psi_common_pulse_generator_ctrl_static.vhd](../../hdl/psi_common_pulse_generator_ctrl_static.vhd)
+- Testbench:  [psi_common_pulse_generator_ctrl_static_tb.vhd](../../testbench/psi_common_pulse_generator_ctrl_static_tb/psi_common_pulse_generator_ctrl_static_tb.vhd)
+
+### Description
+This component implements a pulse generator with static parameters via generics. It create pulses from 0 to the max value defined by the vector data length. The user can set the rising time, the flat top duration and the falling time. The component is responsive to the trigger input (_edge detection_), however if the signal is left to '1' then the block will perform consecutive pulses with the selected parameters. Another parameter allow to define the time duration when a pulse returns to 0.
+During a full cycle, from ramping up, flat top, ramping down and return 0 for the time duration set the component is busy and will not react to another trigger input.
+
+<p align="center"><img src="ch11_13_fig51.png"></p>
+
+### Generics
+
+
+Generics          | Description
+------------------|-------------------------------------------------
+**rst_pol_g** 		| reset polarity ('1' or '0')
+**length_g** 			| data vector length in bits
+**clk_freq_g**    | Clock frequency in Hz
+**str_freq_g**    | Strobe output || increment strobe in Hz
+**nb_step_up_g**  | ramp up param step in str
+**nb_step_dw_g**  | ramp down param step in str
+**nb_step_flh_g** | flat level param step in str
+**nb_step_fll_g** | low level param step in str    
+
+
+### Interfaces
+
+Signal  |Direction  |Width   |Description
+--------|-----------|--------|---------------------------------
+clk_i  	|Input      |1       |Clock
+rst_i  	|Input      |1       |Reset
+str_i   |Input      |1  		 |strobe input
+trig_i  |Input      |1			 | set the level to reach (usgin)
+stop_i  |Input 		  |1 			 | stop pulse and set output to zero
+busy_o 	| output    |1   	 	 | set to 1 when the block is in process
+str_o  	| output    |1   	 	 |  strobe Output
+dat_o   | output    | length_g   |  data output
+
+[Index](../psi_common_index.md) **|** Previous: [Misc > ramp generator](../ch11_misc/ch11_12_ramp_gene.md)

doc/ch11_misc/ch11_12_ramp_gene.md

@@ -19,6 +19,6 @@ This package contains record definitions to allow representing a complete AXI in
 
 ## 2.4	psi_common_math_pkg
 
-This package contains various mathematical functions (e.g. log2). The functions are meant for calculating compile-time constants (i.e. constans, port-widths, etc.). They can potentially be synthesized as combinatorial functions but this is neither guaranteed nor will it lead to optimal results.
+This package contains various mathematical functions (e.g. log2). The functions are meant for calculating compile-time constants (i.e. constants, port-widths, etc.). They can potentially be synthesized as combinatorial functions but this is neither guaranteed nor will it lead to optimal results.
 
 [Index](../psi_common_index.md) **|** Previous: [Introduction](../ch1_introduction/ch1_introduction.md)  **|** Next: [Memories > sdp ram](../ch3_memories/ch3_1_sdp_ram.md)

doc/ch11_misc/ch11_13_fig51.png

@@ -138,6 +138,9 @@
 
 [11.11 psi\_common\_dyn\_sft](ch11_misc/ch11_11_dyn_sft.md)
 
+[11.12 psi\_common\_ramp_\_gene](ch11_misc/ch11_12_ramp_gene.md)
+
+[11.13 psi\_common\_pulse_\_generator_\ctrl_\_static](ch11_misc/ch11_12_pulse_generator_ctrl_static.md)
 ### Others
 
 [presentation](presentation/psi_common_presentation.pdf)

doc/ch11_misc/ch11_13_pulse_generator_ctrl_static.md

@@ -88,8 +88,10 @@ Generic Watchdog 						| [psi_common_watchdog.vhd](../hdl/psi_common_watchdog.vh
 Don't optimize (Xilinx) allows evaluating synthesis  | [psi_common_dont_opt.vhd](../hdl/psi_common_dont_opt.vhd)   | [link](ch11_misc/ch11_7_dont_opt.md)  
 Generic Debouncer  					| [psi_common_debouncer.vhd](../hdl/psi_common_debouncer.vhd)  | [link](ch11_misc/ch11_8_debouncer.md)  
 Analog Trigger Generator  	| [psi_common_trigger_analog.vhd](../hdl/psi_trigger_analog.vhd)  | [link](ch11_misc/ch11_9_trigger_analog.md)  
-Digital Trigger Generator  	| [psi_common_trigger_digital.vhd](../hdl/psi_trigger_digital.vhd)  | [link](ch11_misc/ch11_10_trigger_digital.md) 
-Dynamic Shifter             | [psi_common_dyn_sft.vhd](../hdl/psi_common_dyn_sft.vhd)     | [link](ch11_misc/ch11_11_dyn_sft.md) 
+Digital Trigger Generator  	| [psi_common_trigger_digital.vhd](../hdl/psi_trigger_digital.vhd)  | [link](ch11_misc/ch11_10_trigger_digital.md)
+Dynamic Shifter             | [psi_common_dyn_sft.vhd](../hdl/psi_common_dyn_sft.vhd)     | [link](ch11_misc/ch11_11_dyn_sft.md)
+Pulse/Ramp generator        | [psi_common_ramp_gene.vhd](../hdl/psi_common_ramp_gene.vhd)     | [link](ch11_misc/ch11_12_ramp_gene.md)   
+Pulse generator ctrl static | [psi_common_pulse_generator_ctrl_static.vhd](../hdl/psi_common_pulse_generator_ctrl_static.vhd)     | [link](ch11_misc/ch11_13_pulse_generator_ctrl_static.md)    |   |  
 ***
 
 ### Packages