Ngspice simulation of Verilog-A semiconductor device models compiled with OpenVAF

[amalbanerjee]

I have been using SPICE for the last two decades(HSpice, PSpice, LTSpice and in particular Ngspice). I currently have Ngspice 40 running on a Fedora 38 computer. I have also downloaded the OpenVAF compiler for Linux and it runs fine. I have written Verilog-A device models for the BJT(simple Gummel Poon and I also used the HiCum L2 model), MOSFET, three different GaN
HEMT models(pure Angelov, ASM, etc.,)
After compiling the Verilog-A models with the OpenVAF compiler, I get the ***.osdi binary file, which is used from inside a
simple text Ngspice netlist file for simulation.
I have noticed that while DC sweep analysis(e.g., Ids-Vgs @ constant Vds for a FET, or Ice-Vce @ constant Vbe for a BJT)
generates the curves I am interested in looking at, AC(small signal analysis) always generates flat lines, no matter what
device I might be testing(BJT, FET). I have raised the issue on the Ngspice users' forum but did not receive any useful
answer.
Could you please suggest what I might be doing wrong ? I would be glad to supply the text Verilog-A and Ngspice netlist
files. Thanks in advance for your help.