Initial cosmo hp implementation

Author: nathanaelhuffman

hdl/ip/vhd/axi_blocks/axil_interconnect_2k8.vhd

@@ -133,14 +133,14 @@ begin
         -- default no transaction state for all responders
         for i in 0 to config_array'length - 1 loop
             responders_write_address_valid(i) <= '0';
-            responders_write_address_addr(i) <= initiator_write_address_addr(responders_write_address_addr(i)'length - 1 downto 0);
+            responders_write_address_addr(i) <= (others => '0');
             responders_write_data_valid(i) <= '0';
-            responders_write_data_data(i) <= initiator_write_data_data;
-            responders_write_data_strb(i) <= initiator_write_data_strb;
+            responders_write_data_data(i) <= (others => '0');
+            responders_write_data_strb(i) <= (others => '0');
             responders_write_response_ready(i) <= '0';
 
             responders_read_address_valid(i) <= '0';
-            responders_read_address_addr(i) <= initiator_read_address_addr(responders_read_address_addr(i)'length - 1 downto 0);
+            responders_read_address_addr(i) <= (others => '0');
             responders_read_data_ready(i) <= '0';
 
         end loop;

hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_pkg.vhd

@@ -23,6 +23,7 @@ package pca9506_pkg is
     );
 
     type pca9506_pin_t is array (0 to 4) of std_logic_vector(7 downto 0);
+    type multiple_pca9506_pin_t is array (natural range <>) of pca9506_pin_t;
 
     function get_irq_pend(
         cur_reg: io_type;

hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd

@@ -50,10 +50,10 @@ end entity;
 architecture rtl of pca9545ish_function is
     function is_valid(
         data : std_logic_vector(7 downto 0);
-        allowed_to_enable : std_logic) return boolean is
+        enable_allowed : std_logic) return boolean is
     begin
         -- allow only writes of 0 even when we're not allowed to enable
-        if allowed_to_enable = '0' and data /= 0 then
+        if enable_allowed = '0' and data /= 0 then
             return false;
         end if;
         -- only allow clear and one-hot bits 0-2

hdl/ip/vhd/info/info_2k8.vhd

@@ -114,8 +114,8 @@ begin
             hubris_compat <= unpack(resize(hubris_compat_pins, 32));
             if wready then
                 case to_integer(awaddr) is
-                    when FPGA_CHECKSUM_OFFSET => checksum <= unpack(wdata);
-                    when SCRATCHPAD_OFFSET => scratchpad <= unpack(wdata);
+                    when FPGA_CHECKSUM_OFFSET => checksum <= write_byte_enable(checksum, wdata, wstrb);
+                    when SCRATCHPAD_OFFSET => scratchpad <= write_byte_enable(scratchpad, wdata, wstrb);
                     when others => null;
                 end case;
             end if;

hdl/projects/cosmo_hp/BUCK

@@ -1,9 +1,29 @@
 load("//tools:hdl.bzl", "vhdl_unit")
 load("//tools:yosys.bzl", "ice40_bitstream")
 
+
+vhdl_unit(
+    name = "hp_subsystem_top",
+    srcs = glob(["hp_subsystem/*.vhd"]),
+    deps = [
+        "//hdl/ip/vhd/i2c/io_expanders/PCA9506ish:pca9506_top",
+    ],
+    standard = "2008",
+)
+
 vhdl_unit(
     name = "cosmo_hp_top",
     srcs = glob(["*.vhd"]),
+    deps = [
+        ":hp_subsystem_top",
+        "//hdl/ip/vhd/synchronizers:async_reset_bridge",
+        "//hdl/ip/vhd/i2c/io_expanders/PCA9506ish:pca9506_top",
+        "//hdl/ip/vhd/i2c/muxes/PCA9545ish:pca9545ish_top",
+        "//hdl/ip/vhd/i2c/target:i2c_phy_consolidator",
+        "//hdl/ip/vhd/spi/axi_controller:spi_axi_controller",
+        "//hdl/ip/vhd/axi_blocks:axil_interconnect_2k8",
+        "//hdl/ip/vhd/info:info_2k8",
+    ],
     standard = "2008",
 )
 

hdl/projects/cosmo_hp/cosmo_hp.pcf

@@ -68,7 +68,6 @@ set_io --warn-no-port fpga1_to_fpga2_io[2] E3
 set_io --warn-no-port fpga1_to_fpga2_io[3] H5
 set_io --warn-no-port fpga1_to_fpga2_io[4] E2
 set_io --warn-no-port fpga1_to_fpga2_io[5] G3
-set_io --warn-no-port fpga2_creset_l_r N11
 set_io --warn-no-port fpga2_spare_v3p3[0] E4
 set_io --warn-no-port fpga2_spare_v3p3[1] B2
 set_io --warn-no-port fpga2_spare_v3p3[2] F5
@@ -150,3 +149,4 @@ set_io --warn-no-port spi_sp_mux_to_fpga2_sck R11
 set_io --warn-no-port uart_fpga2_to_sp_dat N4
 set_io --warn-no-port uart_sp_to_fpga2_dat R1
 set_io --warn-no-port v12_mcio_a0hp_pg H6
+set_frequency clk_50mhz_fpga2 50