77bluespec_verilog ('IgnitionTargetSidecar' ,
88 top = 'IgnitionTargetSidecar.bsv' ,
99 modules = [
10- 'mkSidecarRevATargetWithResetButton' ,
11- 'mkSidecarRevATargetWithPowerButton' ,
1210 'mkSidecarRevBTargetWithResetButton' ,
1311 'mkSidecarRevBTargetWithPowerButton' ,
1412 'mkSidecarRevBTarget' ,
@@ -18,48 +16,6 @@ bluespec_verilog('IgnitionTargetSidecar',
1816 '//hdl/ip/bsv/ignition:TargetWrapper' ,
1917 ])
2018
21- # Rev A targets
22-
23- yosys_design ('ignition_target_rev_a_reset_button_top' ,
24- top_module = 'mkSidecarRevATargetWithResetButton' ,
25- sources = [
26- ':IgnitionTargetSidecar#mkSidecarRevATargetWithResetButton' ,
27- '//vnd/bluespec:Verilog.v#Verilog.v' ,
28- '../../../ip/bsv/InitialReset.v' ,
29- ],
30- deps = [
31- ':IgnitionTargetSidecar' ,
32- '//vnd/bluespec:Verilog.v' ,
33- ])
34-
35- nextpnr_ice40_bitstream ('ignition_target_sidecar_rev_a_reset_button' ,
36- env = 'ignition_target' ,
37- design = ':ignition_target_rev_a_reset_button_top#' \
38- 'ignition_target_rev_a_reset_button_top.json' ,
39- deps = [
40- ':ignition_target_rev_a_reset_button_top' ,
41- ])
42-
43- yosys_design ('ignition_target_rev_a_power_button_top' ,
44- top_module = 'mkSidecarRevATargetWithPowerButton' ,
45- sources = [
46- ':IgnitionTargetSidecar#mkSidecarRevATargetWithPowerButton' ,
47- '//vnd/bluespec:Verilog.v#Verilog.v' ,
48- '../../../ip/bsv/InitialReset.v' ,
49- ],
50- deps = [
51- ':IgnitionTargetSidecar' ,
52- '//vnd/bluespec:Verilog.v' ,
53- ])
54-
55- nextpnr_ice40_bitstream ('ignition_target_sidecar_rev_a_power_button' ,
56- env = 'ignition_target' ,
57- design = ':ignition_target_rev_a_power_button_top#' \
58- 'ignition_target_rev_a_power_button_top.json' ,
59- deps = [
60- ':ignition_target_rev_a_power_button_top' ,
61- ])
62-
6319# Rev B, C targets
6420
6521yosys_design ('ignition_target_rev_b_reset_button_top' ,
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