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muhammadhamza15muhammadhamza15
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Merge pull request #24 from muhammadhamza15/mhamza_dev
adding ifndef synthesis macro to specify blocks
2 parents 2b8b19e + 8c103e2 commit ff9923c

18 files changed

+293
-250
lines changed

‎models_internal/verilog/CARRY.v

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -17,17 +17,18 @@ module CARRY (
1717

1818
assign {COUT, O} = {P ? CIN : G, P ^ CIN};
1919

20-
specify
21-
22-
if (P == 1'b1)
23-
(CIN => COUT) = (0, 0);
24-
if (P == 1'b0)
25-
(G => COUT) = (0, 0);
20+
`ifndef SYNTHESIS
21+
specify
2622

27-
( P, CIN *> O ) = (0, 0);
23+
if (P == 1'b1)
24+
(CIN => COUT) = (0, 0);
25+
if (P == 1'b0)
26+
(G => COUT) = (0, 0);
2827

29-
endspecify
28+
( P, CIN *> O ) = (0, 0);
29+
30+
endspecify
31+
`endif // `ifndef SYNTHESIS
3032

31-
3233
endmodule
3334
`endcelldefine

‎models_internal/verilog/CLK_BUF.v

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,12 @@ module CLK_BUF (
1414

1515
assign O = I ;
1616

17-
specify
18-
(I => O) = (0, 0);
19-
endspecify
17+
`ifndef SYNTHESIS
18+
specify
19+
(I => O) = (0, 0);
20+
endspecify
21+
`endif // `ifndef SYNTHESIS
22+
2023

2124

2225
endmodule

‎models_internal/verilog/DFFNRE.v

Lines changed: 50 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -22,57 +22,60 @@ module DFFNRE (
2222
else if (E)
2323
Q <= D;
2424

25-
wire C_D_SDFCHK;
26-
wire C_nD_SDFCHK;
27-
wire nC_D_SDFCHK;
28-
wire nC_nD_SDFCHK;
29-
wire R_D_SDFCHK;
30-
wire R_nD_SDFCHK;
31-
wire R_SDFCHK;
32-
wire D_SDFCHK;
25+
`ifndef SYNTHESIS
26+
wire C_D_SDFCHK;
27+
wire C_nD_SDFCHK;
28+
wire nC_D_SDFCHK;
29+
wire nC_nD_SDFCHK;
30+
wire R_D_SDFCHK;
31+
wire R_nD_SDFCHK;
32+
wire R_SDFCHK;
33+
wire D_SDFCHK;
3334

34-
assign C_D_SDFCHK = C & D;
35-
assign C_nD_SDFCHK = C & !D;
36-
assign nC_D_SDFCHK = !C & D;
37-
assign nC_nD_SDFCHK = !C & !D;
38-
assign R_D_SDFCHK = R & D;
39-
assign R_nD_SDFCHK = R & !D;
40-
assign R_SDFCHK = R;
41-
assign D_SDFCHK = D;
35+
assign C_D_SDFCHK = C & D;
36+
assign C_nD_SDFCHK = C & !D;
37+
assign nC_D_SDFCHK = !C & D;
38+
assign nC_nD_SDFCHK = !C & !D;
39+
assign R_D_SDFCHK = R & D;
40+
assign R_nD_SDFCHK = R & !D;
41+
assign R_SDFCHK = R;
42+
assign D_SDFCHK = D;
4243

4344

44-
specify
45-
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
46-
(negedge R => (Q+:1'b0)) = (0, 0);
47-
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
48-
(negedge R => (Q+:1'b0)) = (0, 0);
49-
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
50-
(negedge R => (Q+:1'b0)) = (0, 0);
51-
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
52-
(negedge R => (Q+:1'b0)) = (0, 0);
53-
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
54-
(negedge R => (Q+:1'b0)) = (0, 0);
55-
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
56-
(negedge R => (Q+:1'b0)) = (0, 0);
57-
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
58-
(negedge R => (Q+:1'b0)) = (0, 0);
59-
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
60-
(negedge R => (Q+:1'b0)) = (0, 0);
61-
(negedge C => (Q+:D)) = (0, 0);
45+
specify
46+
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
47+
(negedge R => (Q+:1'b0)) = (0, 0);
48+
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
49+
(negedge R => (Q+:1'b0)) = (0, 0);
50+
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
51+
(negedge R => (Q+:1'b0)) = (0, 0);
52+
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
53+
(negedge R => (Q+:1'b0)) = (0, 0);
54+
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
55+
(negedge R => (Q+:1'b0)) = (0, 0);
56+
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
57+
(negedge R => (Q+:1'b0)) = (0, 0);
58+
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
59+
(negedge R => (Q+:1'b0)) = (0, 0);
60+
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
61+
(negedge R => (Q+:1'b0)) = (0, 0);
62+
(negedge C => (Q+:D)) = (0, 0);
6263

63-
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
64-
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
65-
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
66-
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
67-
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
68-
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
69-
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
70-
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
64+
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
65+
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
66+
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
67+
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
68+
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
69+
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
70+
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
71+
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
72+
73+
$setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
74+
$setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
75+
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
76+
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
77+
endspecify
78+
`endif // `ifndef SYNTHESIS
7179

72-
$setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
73-
$setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
74-
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
75-
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
76-
endspecify
7780
endmodule
7881
`endcelldefine

‎models_internal/verilog/DFFRE.v

Lines changed: 51 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -22,58 +22,61 @@ module DFFRE (
2222
else if (E)
2323
Q <= D;
2424

25-
wire C_D_SDFCHK;
26-
wire C_nD_SDFCHK;
27-
wire nC_D_SDFCHK;
28-
wire nC_nD_SDFCHK;
29-
wire R_D_SDFCHK;
30-
wire R_nD_SDFCHK;
31-
wire R_SDFCHK;
32-
wire D_SDFCHK;
25+
`ifndef SYNTHESIS
26+
wire C_D_SDFCHK;
27+
wire C_nD_SDFCHK;
28+
wire nC_D_SDFCHK;
29+
wire nC_nD_SDFCHK;
30+
wire R_D_SDFCHK;
31+
wire R_nD_SDFCHK;
32+
wire R_SDFCHK;
33+
wire D_SDFCHK;
3334

34-
assign C_D_SDFCHK = C & D;
35-
assign C_nD_SDFCHK = C & !D;
36-
assign nC_D_SDFCHK = !C & D;
37-
assign nC_nD_SDFCHK = !C & !D;
38-
assign R_D_SDFCHK = R & D;
39-
assign R_nD_SDFCHK = R & !D;
40-
assign R_SDFCHK = R;
41-
assign D_SDFCHK = D;
35+
assign C_D_SDFCHK = C & D;
36+
assign C_nD_SDFCHK = C & !D;
37+
assign nC_D_SDFCHK = !C & D;
38+
assign nC_nD_SDFCHK = !C & !D;
39+
assign R_D_SDFCHK = R & D;
40+
assign R_nD_SDFCHK = R & !D;
41+
assign R_SDFCHK = R;
42+
assign D_SDFCHK = D;
4243

4344

44-
specify
45-
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
46-
(negedge R => (Q+:1'b0)) = (0, 0);
47-
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
48-
(negedge R => (Q+:1'b0)) = (0, 0);
49-
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
50-
(negedge R => (Q+:1'b0)) = (0, 0);
51-
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
52-
(negedge R => (Q+:1'b0)) = (0, 0);
53-
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
54-
(negedge R => (Q+:1'b0)) = (0, 0);
55-
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
56-
(negedge R => (Q+:1'b0)) = (0, 0);
57-
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
58-
(negedge R => (Q+:1'b0)) = (0, 0);
59-
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
60-
(negedge R => (Q+:1'b0)) = (0, 0);
61-
(posedge C => (Q+:D)) = (0, 0);
45+
specify
46+
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
47+
(negedge R => (Q+:1'b0)) = (0, 0);
48+
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
49+
(negedge R => (Q+:1'b0)) = (0, 0);
50+
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
51+
(negedge R => (Q+:1'b0)) = (0, 0);
52+
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
53+
(negedge R => (Q+:1'b0)) = (0, 0);
54+
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
55+
(negedge R => (Q+:1'b0)) = (0, 0);
56+
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
57+
(negedge R => (Q+:1'b0)) = (0, 0);
58+
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
59+
(negedge R => (Q+:1'b0)) = (0, 0);
60+
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
61+
(negedge R => (Q+:1'b0)) = (0, 0);
62+
(posedge C => (Q+:D)) = (0, 0);
6263

63-
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
64-
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
65-
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
66-
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
67-
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
68-
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
69-
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
70-
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
64+
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
65+
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
66+
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
67+
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
68+
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
69+
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
70+
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
71+
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
7172

72-
$setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
73-
$setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
74-
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
75-
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
76-
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
77-
endspecify
73+
$setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
74+
$setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
75+
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
76+
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
77+
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
78+
endspecify
79+
`endif // `ifndef SYNTHESIS
80+
7881
endmodule
7982
`endcelldefine

‎models_internal/verilog/FCLK_BUF.v

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,11 @@ module FCLK_BUF (
1414

1515
assign O = I ;
1616

17-
specify
18-
(I => O) = (0, 0);
19-
endspecify
17+
`ifndef SYNTHESIS
18+
specify
19+
(I => O) = (0, 0);
20+
endspecify
21+
`endif // `ifndef SYNTHESIS
2022

2123

2224
endmodule

‎models_internal/verilog/I_BUF.v

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,13 @@ module I_BUF #(
2525

2626
assign O = EN ? I : 1'b0;
2727

28-
specify
29-
if (EN == 1'b1)
30-
(I => O) = (0, 0);
31-
endspecify
28+
`ifndef SYNTHESIS
29+
specify
30+
if (EN == 1'b1)
31+
(I => O) = (0, 0);
32+
endspecify
33+
`endif // `ifndef SYNTHESIS
34+
3235
initial begin
3336
case(WEAK_KEEPER)
3437
"NONE" ,

‎models_internal/verilog/I_BUF_DS.v

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,12 @@ module I_BUF_DS #(
3737
endcase
3838
end
3939

40-
specify
41-
if (EN == 1'b1)
42-
( I_P, I_N *> O ) = (0, 0);
43-
endspecify
40+
`ifndef SYNTHESIS
41+
specify
42+
if (EN == 1'b1)
43+
( I_P, I_N *> O ) = (0, 0);
44+
endspecify
45+
`endif // `ifndef SYNTHESIS
4446

4547
initial begin
4648
case(WEAK_KEEPER)

‎models_internal/verilog/O_BUF.v

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,12 @@ module O_BUF
2020

2121
assign O = I ;
2222

23-
specify
24-
(I => O) = (0, 0);
25-
endspecify initial begin
23+
`ifndef SYNTHESIS
24+
specify
25+
(I => O) = (0, 0);
26+
endspecify
27+
`endif // `ifndef SYNTHESIS
28+
initial begin
2629

2730
case(IOSTANDARD)
2831
"DEFAULT" ,

‎models_internal/verilog/O_BUF_DS.v

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,13 @@ module O_BUF_DS
2121
assign O_P = I;
2222
assign O_N = ~I;
2323

24-
specify
25-
(I => O_P) = (0, 0);
26-
(I => O_N) = (0, 0);
27-
endspecify
24+
`ifndef SYNTHESIS
25+
specify
26+
(I => O_P) = (0, 0);
27+
(I => O_N) = (0, 0);
28+
endspecify
29+
`endif // `ifndef SYNTHESIS
30+
2831

2932
initial begin
3033

‎models_internal/verilog/inc/CARRY.inc.v

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11

22
assign {COUT, O} = {P ? CIN : G, P ^ CIN};
33

4-
specify
5-
6-
if (P == 1'b1)
7-
(CIN => COUT) = (0, 0);
8-
if (P == 1'b0)
9-
(G => COUT) = (0, 0);
4+
`ifndef SYNTHESIS
5+
specify
106

11-
( P, CIN *> O ) = (0, 0);
7+
if (P == 1'b1)
8+
(CIN => COUT) = (0, 0);
9+
if (P == 1'b0)
10+
(G => COUT) = (0, 0);
1211

13-
endspecify
12+
( P, CIN *> O ) = (0, 0);
1413

15-
14+
endspecify
15+
`endif // `ifndef SYNTHESIS

‎models_internal/verilog/inc/CLK_BUF.inc.v

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11

22
assign O = I ;
33

4-
specify
5-
(I => O) = (0, 0);
6-
endspecify
4+
`ifndef SYNTHESIS
5+
specify
6+
(I => O) = (0, 0);
7+
endspecify
8+
`endif // `ifndef SYNTHESIS
9+
710

811

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