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muhammadhamza15muhammadhamza15
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Merge pull request #47 from muhammadhamza15/main
Simulation Models Update
2 parents e581cdf + 470a8e3 commit d8715d2

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8 files changed

+124
-112
lines changed

8 files changed

+124
-112
lines changed

‎etc/bb.mako

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,9 @@ def gen_param_string(pdict):
4848
4949
if 'default' in pdict[param]:
5050
default = pdict[param]['default']
51+
if 'type' in pdict[param]:
52+
if pdict[param]['type'] == "real": # convert the real values to int for blackbox as float/real are not synthesizable
53+
default = int(default)
5154
if is_real_param(pdict[param]) or is_vector_param(pdict[param]):
5255
# integers and vectors don't need quotes
5356
param_str = f" parameter {vector_str}{param} = {default}"

‎models_customer/verilog/DSP19X2.v

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -376,30 +376,31 @@ module DSP19X2 #(
376376
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
377377
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
378378

379-
380-
// If ACC_FIR is greater than 21, result is invalid
381-
always @(ACC_FIR)
382-
if (ACC_FIR > 21)
383-
begin
384-
$fatal(1,"WARNING: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
385-
end
386-
// If SHIFT_RIGHT is greater than 31, result is invalid
387-
always @(SHIFT_RIGHT)
388-
if (SHIFT_RIGHT > 31)
389-
begin
390-
$fatal(1,"WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
391-
end
392-
393-
always@(*)
394-
begin
395-
case(DSP_MODE)
396-
"MULTIPLY_ACCUMULATE": begin
397-
if(FEEDBACK>1)
398-
$fatal(1,"\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
379+
`ifndef SYNTHESIS
380+
// If ACC_FIR is greater than 21, result is invalid
381+
always @(ACC_FIR)
382+
if (ACC_FIR > 21)
383+
begin
384+
$fatal(1,"\nERROR: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
385+
end
386+
// If SHIFT_RIGHT is greater than 31, result is invalid
387+
always @(SHIFT_RIGHT)
388+
if (SHIFT_RIGHT > 31)
389+
begin
390+
$fatal(1,"\nERROR: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
399391
end
400-
endcase
401392

402-
end
393+
always@(*)
394+
begin
395+
case(DSP_MODE)
396+
"MULTIPLY_ACCUMULATE": begin
397+
if(FEEDBACK>1)
398+
$fatal(1,"\nERROR: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
399+
end
400+
endcase
401+
402+
end
403+
`endif // `ifndef SYNTHESIS
403404

404405
initial begin
405406
case(DSP_MODE)

‎models_customer/verilog/DSP38.v

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -294,21 +294,23 @@ module DSP38 #(
294294

295295
assign Z = (OUTPUT_REG_EN == "TRUE")?z_out_reg:z_out;
296296

297-
// If ACC_FIR is greater than 43, result is invalid
298-
always @(ACC_FIR)
299-
if (ACC_FIR > 43)
300-
$fatal(1,"\nWARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
301-
302-
always@(*)
303-
begin
304-
case(DSP_MODE)
305-
"MULTIPLY_ACCUMULATE": begin
306-
if(FEEDBACK>1)
307-
$fatal(1,"\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
308-
end
309-
endcase
310-
311-
end
297+
`ifndef SYNTHESIS
298+
// If ACC_FIR is greater than 43, result is invalid
299+
always @(ACC_FIR)
300+
if (ACC_FIR > 43)
301+
$fatal(1,"\nERROR: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
302+
303+
always@(*)
304+
begin
305+
case(DSP_MODE)
306+
"MULTIPLY_ACCUMULATE": begin
307+
if(FEEDBACK>1)
308+
$fatal(1,"\nERROR: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
309+
end
310+
endcase
311+
312+
end
313+
`endif // `ifndef SYNTHESIS
312314

313315
initial begin
314316
case(DSP_MODE)

‎models_internal/verilog/DSP19X2.v

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -376,30 +376,31 @@ module DSP19X2 #(
376376
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
377377
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
378378

379-
380-
// If ACC_FIR is greater than 21, result is invalid
381-
always @(ACC_FIR)
382-
if (ACC_FIR > 21)
383-
begin
384-
$fatal(1,"WARNING: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
385-
end
386-
// If SHIFT_RIGHT is greater than 31, result is invalid
387-
always @(SHIFT_RIGHT)
388-
if (SHIFT_RIGHT > 31)
389-
begin
390-
$fatal(1,"WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
391-
end
392-
393-
always@(*)
394-
begin
395-
case(DSP_MODE)
396-
"MULTIPLY_ACCUMULATE": begin
397-
if(FEEDBACK>1)
398-
$fatal(1,"\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
379+
`ifndef SYNTHESIS
380+
// If ACC_FIR is greater than 21, result is invalid
381+
always @(ACC_FIR)
382+
if (ACC_FIR > 21)
383+
begin
384+
$fatal(1,"\nERROR: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
385+
end
386+
// If SHIFT_RIGHT is greater than 31, result is invalid
387+
always @(SHIFT_RIGHT)
388+
if (SHIFT_RIGHT > 31)
389+
begin
390+
$fatal(1,"\nERROR: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
399391
end
400-
endcase
401392

402-
end
393+
always@(*)
394+
begin
395+
case(DSP_MODE)
396+
"MULTIPLY_ACCUMULATE": begin
397+
if(FEEDBACK>1)
398+
$fatal(1,"\nERROR: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
399+
end
400+
endcase
401+
402+
end
403+
`endif // `ifndef SYNTHESIS
403404

404405
initial begin
405406
case(DSP_MODE)

‎models_internal/verilog/DSP38.v

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -294,21 +294,23 @@ module DSP38 #(
294294

295295
assign Z = (OUTPUT_REG_EN == "TRUE")?z_out_reg:z_out;
296296

297-
// If ACC_FIR is greater than 43, result is invalid
298-
always @(ACC_FIR)
299-
if (ACC_FIR > 43)
300-
$fatal(1,"\nWARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
301-
302-
always@(*)
303-
begin
304-
case(DSP_MODE)
305-
"MULTIPLY_ACCUMULATE": begin
306-
if(FEEDBACK>1)
307-
$fatal(1,"\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
308-
end
309-
endcase
310-
311-
end
297+
`ifndef SYNTHESIS
298+
// If ACC_FIR is greater than 43, result is invalid
299+
always @(ACC_FIR)
300+
if (ACC_FIR > 43)
301+
$fatal(1,"\nERROR: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
302+
303+
always@(*)
304+
begin
305+
case(DSP_MODE)
306+
"MULTIPLY_ACCUMULATE": begin
307+
if(FEEDBACK>1)
308+
$fatal(1,"\nERROR: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
309+
end
310+
endcase
311+
312+
end
313+
`endif // `ifndef SYNTHESIS
312314

313315
initial begin
314316
case(DSP_MODE)

‎models_internal/verilog/inc/DSP19X2.inc.v

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -334,28 +334,29 @@
334334
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
335335
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
336336

337-
338-
// If ACC_FIR is greater than 21, result is invalid
339-
always @(ACC_FIR)
340-
if (ACC_FIR > 21)
341-
begin
342-
$fatal(1,"WARNING: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
343-
end
344-
// If SHIFT_RIGHT is greater than 31, result is invalid
345-
always @(SHIFT_RIGHT)
346-
if (SHIFT_RIGHT > 31)
347-
begin
348-
$fatal(1,"WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
349-
end
350-
351-
always@(*)
352-
begin
353-
case(DSP_MODE)
354-
"MULTIPLY_ACCUMULATE": begin
355-
if(FEEDBACK>1)
356-
$fatal(1,"\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
337+
`ifndef SYNTHESIS
338+
// If ACC_FIR is greater than 21, result is invalid
339+
always @(ACC_FIR)
340+
if (ACC_FIR > 21)
341+
begin
342+
$fatal(1,"\nERROR: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
343+
end
344+
// If SHIFT_RIGHT is greater than 31, result is invalid
345+
always @(SHIFT_RIGHT)
346+
if (SHIFT_RIGHT > 31)
347+
begin
348+
$fatal(1,"\nERROR: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
357349
end
358-
endcase
359350

360-
end
351+
always@(*)
352+
begin
353+
case(DSP_MODE)
354+
"MULTIPLY_ACCUMULATE": begin
355+
if(FEEDBACK>1)
356+
$fatal(1,"\nERROR: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
357+
end
358+
endcase
359+
360+
end
361+
`endif // `ifndef SYNTHESIS
361362

‎models_internal/verilog/inc/DSP38.inc.v

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -260,19 +260,21 @@
260260

261261
assign Z = (OUTPUT_REG_EN == "TRUE")?z_out_reg:z_out;
262262

263-
// If ACC_FIR is greater than 43, result is invalid
264-
always @(ACC_FIR)
265-
if (ACC_FIR > 43)
266-
$fatal(1,"\nWARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
267-
268-
always@(*)
269-
begin
270-
case(DSP_MODE)
271-
"MULTIPLY_ACCUMULATE": begin
272-
if(FEEDBACK>1)
273-
$fatal(1,"\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
274-
end
275-
endcase
276-
277-
end
263+
`ifndef SYNTHESIS
264+
// If ACC_FIR is greater than 43, result is invalid
265+
always @(ACC_FIR)
266+
if (ACC_FIR > 43)
267+
$fatal(1,"\nERROR: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
268+
269+
always@(*)
270+
begin
271+
case(DSP_MODE)
272+
"MULTIPLY_ACCUMULATE": begin
273+
if(FEEDBACK>1)
274+
$fatal(1,"\nERROR: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
275+
end
276+
endcase
277+
278+
end
279+
`endif // `ifndef SYNTHESIS
278280

‎models_internal/verilog_blackbox/cell_sim_blackbox.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
`celldefine
88
(* blackbox *)
99
module BOOT_CLOCK #(
10-
parameter PERIOD = 25.0 // Clock period for simulation purposes (nS)
10+
parameter PERIOD = 25 // Clock period for simulation purposes (nS)
1111
) (
1212
output reg O
1313
);

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