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muhammadhamza15muhammadhamza15
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Merge pull request #76 from muhammadhamza15/mhamza_dev
Mhamza dev
2 parents 36e3a7b + fbe78d2 commit b0f9cd8

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‎models_internal/verilog/CARRY_BREAK.v

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
`timescale 1ns/1ps
2+
`celldefine
3+
//
4+
// CARRY_BREAK simulation model
5+
// CARRY_BREAK describes an implementation of the regular CARRY module where we break the COUT -> next CIN link
6+
//
7+
// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
8+
//
9+
10+
module CARRY_BREAK (
11+
input P, // Partial data input
12+
input G, // Partial data input
13+
input CIN, // Carry in
14+
output O, // Data output
15+
output COUT // Carry out
16+
);
17+
18+
wire cout;
19+
wire still_cout;
20+
21+
// Reminder of CARRY functions: COUT and O
22+
//
23+
// assign {COUT, O} = {P ? CIN : G, P ^ CIN};
24+
25+
CARRY carry_break ( // This one replaces the original CARRY cell
26+
.CIN(CIN),
27+
.COUT(cout), // try to break this COUT net
28+
.G(G),
29+
.O(O),
30+
.P(P)
31+
);
32+
33+
// We break the CI -> CO chain and pass the COUT net 'cout" through the
34+
// 'O' pin (carry sum) of a new CARRY to become a regular data 'still_cout'.
35+
//
36+
CARRY cout_to_data (
37+
.CIN(cout),
38+
.G(1'h0),
39+
.O(still_cout), // still_cout = P ^ CIN = 1'h0 ^ cout = cout
40+
.P(1'h0)
41+
);
42+
43+
// Carry cell 'data_to_cout' reads in the 'still_cout' data and drives it
44+
// through the 'COUT' pin to restart a CO -> CI new carry chain.
45+
//
46+
CARRY data_to_cout (
47+
.COUT(COUT),
48+
.G(still_cout),
49+
.P(1'h0)
50+
);
51+
52+
endmodule
53+
`endcelldefine

‎models_internal/verilog/DLY_SEL_DECODER.v

Lines changed: 38 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -84,87 +84,86 @@ begin
8484
end
8585

8686

87-
8887
`ifndef SYNTHESIS
8988
`ifdef TIMED_SIM
9089
specparam T1 = 0.4;
9190

9291
specify
9392
if (DLY_ADDR == 5'd0)
94-
(DLY_LOAD => DLY0_CNTRL) = T1;
95-
(DLY_ADJ => DLY0_CNTRL) = T1;
93+
(DLY_LOAD *> DLY0_CNTRL) = T1;
94+
(DLY_ADJ *> DLY0_CNTRL) = T1;
9695
(DLY_INCDEC => DLY0_CNTRL) = T1;
9796
if (DLY_ADDR == 5'd1)
98-
(DLY_LOAD => DLY1_CNTRL) = T1;
99-
(DLY_ADJ => DLY1_CNTRL) = T1;
97+
(DLY_LOAD *> DLY1_CNTRL) = T1;
98+
(DLY_ADJ *> DLY1_CNTRL) = T1;
10099
(DLY_INCDEC => DLY1_CNTRL) = T1;
101100
if (DLY_ADDR == 5'd2)
102-
(DLY_LOAD => DLY2_CNTRL) = T1;
103-
(DLY_ADJ => DLY2_CNTRL) = T1;
101+
(DLY_LOAD *> DLY2_CNTRL) = T1;
102+
(DLY_ADJ *> DLY2_CNTRL) = T1;
104103
(DLY_INCDEC => DLY2_CNTRL) = T1;
105104
if (DLY_ADDR == 5'd3)
106-
(DLY_LOAD => DLY3_CNTRL) = T1;
107-
(DLY_ADJ => DLY3_CNTRL) = T1;
105+
(DLY_LOAD *> DLY3_CNTRL) = T1;
106+
(DLY_ADJ *> DLY3_CNTRL) = T1;
108107
(DLY_INCDEC => DLY3_CNTRL) = T1;
109108
if (DLY_ADDR == 5'd4)
110-
(DLY_LOAD => DLY4_CNTRL) = T1;
111-
(DLY_ADJ => DLY4_CNTRL) = T1;
109+
(DLY_LOAD *> DLY4_CNTRL) = T1;
110+
(DLY_ADJ *> DLY4_CNTRL) = T1;
112111
(DLY_INCDEC => DLY4_CNTRL) = T1;
113112
if (DLY_ADDR == 5'd5)
114-
(DLY_LOAD => DLY5_CNTRL) = T1;
115-
(DLY_ADJ => DLY5_CNTRL) = T1;
113+
(DLY_LOAD *> DLY5_CNTRL) = T1;
114+
(DLY_ADJ *> DLY5_CNTRL) = T1;
116115
(DLY_INCDEC => DLY5_CNTRL) = T1;
117116
if (DLY_ADDR == 5'd6)
118-
(DLY_LOAD => DLY6_CNTRL) = T1;
119-
(DLY_ADJ => DLY6_CNTRL) = T1;
117+
(DLY_LOAD *> DLY6_CNTRL) = T1;
118+
(DLY_ADJ *> DLY6_CNTRL) = T1;
120119
(DLY_INCDEC => DLY6_CNTRL) = T1;
121120
if (DLY_ADDR == 5'd7)
122-
(DLY_LOAD => DLY7_CNTRL) = T1;
123-
(DLY_ADJ => DLY7_CNTRL) = T1;
121+
(DLY_LOAD *> DLY7_CNTRL) = T1;
122+
(DLY_ADJ *> DLY7_CNTRL) = T1;
124123
(DLY_INCDEC => DLY7_CNTRL) = T1;
125124
if (DLY_ADDR == 5'd8)
126-
(DLY_LOAD => DLY8_CNTRL) = T1;
127-
(DLY_ADJ => DLY8_CNTRL) = T1;
125+
(DLY_LOAD *> DLY8_CNTRL) = T1;
126+
(DLY_ADJ *> DLY8_CNTRL) = T1;
128127
(DLY_INCDEC => DLY8_CNTRL) = T1;
129128
if (DLY_ADDR == 5'd9)
130-
(DLY_LOAD => DLY9_CNTRL) = T1;
131-
(DLY_ADJ => DLY9_CNTRL) = T1;
129+
(DLY_LOAD *> DLY9_CNTRL) = T1;
130+
(DLY_ADJ *> DLY9_CNTRL) = T1;
132131
(DLY_INCDEC => DLY9_CNTRL) = T1;
133132
if (DLY_ADDR == 5'd10)
134-
(DLY_LOAD => DLY10_CNTRL) = T1;
135-
(DLY_ADJ => DLY10_CNTRL) = T1;
133+
(DLY_LOAD *> DLY10_CNTRL) = T1;
134+
(DLY_ADJ *> DLY10_CNTRL) = T1;
136135
(DLY_INCDEC => DLY10_CNTRL) = T1;
137136
if (DLY_ADDR == 5'd12)
138-
(DLY_LOAD => DLY12_CNTRL) = T1;
139-
(DLY_ADJ => DLY12_CNTRL) = T1;
137+
(DLY_LOAD *> DLY12_CNTRL) = T1;
138+
(DLY_ADJ *> DLY12_CNTRL) = T1;
140139
(DLY_INCDEC => DLY12_CNTRL) = T1;
141140
if (DLY_ADDR == 5'd13)
142-
(DLY_LOAD => DLY13_CNTRL) = T1;
143-
(DLY_ADJ => DLY13_CNTRL) = T1;
141+
(DLY_LOAD *> DLY13_CNTRL) = T1;
142+
(DLY_ADJ *> DLY13_CNTRL) = T1;
144143
(DLY_INCDEC => DLY13_CNTRL) = T1;
145144
if (DLY_ADDR == 5'd14)
146-
(DLY_LOAD => DLY14_CNTRL) = T1;
147-
(DLY_ADJ => DLY14_CNTRL) = T1;
145+
(DLY_LOAD *> DLY14_CNTRL) = T1;
146+
(DLY_ADJ *> DLY14_CNTRL) = T1;
148147
(DLY_INCDEC => DLY14_CNTRL) = T1;
149148
if (DLY_ADDR == 5'd15)
150-
(DLY_LOAD => DLY15_CNTRL) = T1;
151-
(DLY_ADJ => DLY15_CNTRL) = T1;
149+
(DLY_LOAD *> DLY15_CNTRL) = T1;
150+
(DLY_ADJ *> DLY15_CNTRL) = T1;
152151
(DLY_INCDEC => DLY15_CNTRL) = T1;
153152
if (DLY_ADDR == 5'd16)
154-
(DLY_LOAD => DLY16_CNTRL) = T1;
155-
(DLY_ADJ => DLY16_CNTRL) = T1;
153+
(DLY_LOAD *> DLY16_CNTRL) = T1;
154+
(DLY_ADJ *> DLY16_CNTRL) = T1;
156155
(DLY_INCDEC => DLY16_CNTRL) = T1;
157156
if (DLY_ADDR == 5'd17)
158-
(DLY_LOAD => DLY17_CNTRL) = T1;
159-
(DLY_ADJ => DLY17_CNTRL) = T1;
157+
(DLY_LOAD *> DLY17_CNTRL) = T1;
158+
(DLY_ADJ *> DLY17_CNTRL) = T1;
160159
(DLY_INCDEC => DLY17_CNTRL) = T1;
161160
if (DLY_ADDR == 5'd18)
162-
(DLY_LOAD => DLY18_CNTRL) = T1;
163-
(DLY_ADJ => DLY18_CNTRL) = T1;
161+
(DLY_LOAD *> DLY18_CNTRL) = T1;
162+
(DLY_ADJ *> DLY18_CNTRL) = T1;
164163
(DLY_INCDEC => DLY18_CNTRL) = T1;
165164
if (DLY_ADDR == 5'd19)
166-
(DLY_LOAD => DLY19_CNTRL) = T1;
167-
(DLY_ADJ => DLY19_CNTRL) = T1;
165+
(DLY_LOAD *> DLY19_CNTRL) = T1;
166+
(DLY_ADJ *> DLY19_CNTRL) = T1;
168167
(DLY_INCDEC => DLY19_CNTRL) = T1;
169168

170169
endspecify

‎models_internal/verilog/DLY_VALUE_MUX.v

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@ end
8989
(DLY_TAP9_VAL => DLY_TAP_VALUE) = T1;
9090
if (DLY_ADDR == 5'd10)
9191
(DLY_TAP10_VAL => DLY_TAP_VALUE) = T1;
92+
if (DLY_ADDR == 5'd11)
93+
(DLY_TAP11_VAL => DLY_TAP_VALUE) = T1;
9294
if (DLY_ADDR == 5'd12)
9395
(DLY_TAP12_VAL => DLY_TAP_VALUE) = T1;
9496
if (DLY_ADDR == 5'd13)

‎models_internal/verilog/LUT2.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ module LUT2 #(
2323
specparam T1 = 0.5;
2424

2525
specify
26-
(A => Y) = (T1);
26+
(A *> Y) = (T1);
2727
endspecify
2828
`endif // `ifdef TIMED_SIM
2929
`endif // `ifndef SYNTHESIS

‎models_internal/verilog/LUT3.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ module LUT3 #(
2525
specparam T1 = 0.5;
2626

2727
specify
28-
(A => Y) = (T1);
28+
(A *> Y) = (T1);
2929
endspecify
3030
`endif // `ifdef TIMED_SIM
3131
`endif // `ifndef SYNTHESIS

‎models_internal/verilog/LUT4.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ module LUT4 #(
2727
specparam T1 = 0.5;
2828

2929
specify
30-
(A => Y) = (T1);
30+
(A *> Y) = (T1);
3131
endspecify
3232
`endif // `ifdef TIMED_SIM
3333
`endif // `ifndef SYNTHESIS

‎models_internal/verilog/LUT5.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ module LUT5 #(
2626
specparam T1 = 0.5;
2727

2828
specify
29-
(A => Y) = (T1);
29+
(A *> Y) = (T1);
3030
endspecify
3131
`endif // `ifdef TIMED_SIM
3232
`endif // `ifndef SYNTHESIS

‎models_internal/verilog/inc/CARRY_BREAK.inc.v

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
2+
wire cout;
3+
wire still_cout;
4+
5+
// Reminder of CARRY functions: COUT and O
6+
//
7+
// assign {COUT, O} = {P ? CIN : G, P ^ CIN};
8+
9+
CARRY carry_break ( // This one replaces the original CARRY cell
10+
.CIN(CIN),
11+
.COUT(cout), // try to break this COUT net
12+
.G(G),
13+
.O(O),
14+
.P(P)
15+
);
16+
17+
// We break the CI -> CO chain and pass the COUT net 'cout" through the
18+
// 'O' pin (carry sum) of a new CARRY to become a regular data 'still_cout'.
19+
//
20+
CARRY cout_to_data (
21+
.CIN(cout),
22+
.G(1'h0),
23+
.O(still_cout), // still_cout = P ^ CIN = 1'h0 ^ cout = cout
24+
.P(1'h0)
25+
);
26+
27+
// Carry cell 'data_to_cout' reads in the 'still_cout' data and drives it
28+
// through the 'COUT' pin to restart a CO -> CI new carry chain.
29+
//
30+
CARRY data_to_cout (
31+
.COUT(COUT),
32+
.G(still_cout),
33+
.P(1'h0)
34+
);

‎models_internal/verilog/inc/CARRY_BREAK.pro.v

Whitespace-only changes.

‎models_internal/verilog/inc/DLY_SEL_DECODER.inc.v

Lines changed: 38 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -49,87 +49,86 @@ begin
4949
end
5050

5151

52-
5352
`ifndef SYNTHESIS
5453
`ifdef TIMED_SIM
5554
specparam T1 = 0.4;
5655

5756
specify
5857
if (DLY_ADDR == 5'd0)
59-
(DLY_LOAD => DLY0_CNTRL) = T1;
60-
(DLY_ADJ => DLY0_CNTRL) = T1;
58+
(DLY_LOAD *> DLY0_CNTRL) = T1;
59+
(DLY_ADJ *> DLY0_CNTRL) = T1;
6160
(DLY_INCDEC => DLY0_CNTRL) = T1;
6261
if (DLY_ADDR == 5'd1)
63-
(DLY_LOAD => DLY1_CNTRL) = T1;
64-
(DLY_ADJ => DLY1_CNTRL) = T1;
62+
(DLY_LOAD *> DLY1_CNTRL) = T1;
63+
(DLY_ADJ *> DLY1_CNTRL) = T1;
6564
(DLY_INCDEC => DLY1_CNTRL) = T1;
6665
if (DLY_ADDR == 5'd2)
67-
(DLY_LOAD => DLY2_CNTRL) = T1;
68-
(DLY_ADJ => DLY2_CNTRL) = T1;
66+
(DLY_LOAD *> DLY2_CNTRL) = T1;
67+
(DLY_ADJ *> DLY2_CNTRL) = T1;
6968
(DLY_INCDEC => DLY2_CNTRL) = T1;
7069
if (DLY_ADDR == 5'd3)
71-
(DLY_LOAD => DLY3_CNTRL) = T1;
72-
(DLY_ADJ => DLY3_CNTRL) = T1;
70+
(DLY_LOAD *> DLY3_CNTRL) = T1;
71+
(DLY_ADJ *> DLY3_CNTRL) = T1;
7372
(DLY_INCDEC => DLY3_CNTRL) = T1;
7473
if (DLY_ADDR == 5'd4)
75-
(DLY_LOAD => DLY4_CNTRL) = T1;
76-
(DLY_ADJ => DLY4_CNTRL) = T1;
74+
(DLY_LOAD *> DLY4_CNTRL) = T1;
75+
(DLY_ADJ *> DLY4_CNTRL) = T1;
7776
(DLY_INCDEC => DLY4_CNTRL) = T1;
7877
if (DLY_ADDR == 5'd5)
79-
(DLY_LOAD => DLY5_CNTRL) = T1;
80-
(DLY_ADJ => DLY5_CNTRL) = T1;
78+
(DLY_LOAD *> DLY5_CNTRL) = T1;
79+
(DLY_ADJ *> DLY5_CNTRL) = T1;
8180
(DLY_INCDEC => DLY5_CNTRL) = T1;
8281
if (DLY_ADDR == 5'd6)
83-
(DLY_LOAD => DLY6_CNTRL) = T1;
84-
(DLY_ADJ => DLY6_CNTRL) = T1;
82+
(DLY_LOAD *> DLY6_CNTRL) = T1;
83+
(DLY_ADJ *> DLY6_CNTRL) = T1;
8584
(DLY_INCDEC => DLY6_CNTRL) = T1;
8685
if (DLY_ADDR == 5'd7)
87-
(DLY_LOAD => DLY7_CNTRL) = T1;
88-
(DLY_ADJ => DLY7_CNTRL) = T1;
86+
(DLY_LOAD *> DLY7_CNTRL) = T1;
87+
(DLY_ADJ *> DLY7_CNTRL) = T1;
8988
(DLY_INCDEC => DLY7_CNTRL) = T1;
9089
if (DLY_ADDR == 5'd8)
91-
(DLY_LOAD => DLY8_CNTRL) = T1;
92-
(DLY_ADJ => DLY8_CNTRL) = T1;
90+
(DLY_LOAD *> DLY8_CNTRL) = T1;
91+
(DLY_ADJ *> DLY8_CNTRL) = T1;
9392
(DLY_INCDEC => DLY8_CNTRL) = T1;
9493
if (DLY_ADDR == 5'd9)
95-
(DLY_LOAD => DLY9_CNTRL) = T1;
96-
(DLY_ADJ => DLY9_CNTRL) = T1;
94+
(DLY_LOAD *> DLY9_CNTRL) = T1;
95+
(DLY_ADJ *> DLY9_CNTRL) = T1;
9796
(DLY_INCDEC => DLY9_CNTRL) = T1;
9897
if (DLY_ADDR == 5'd10)
99-
(DLY_LOAD => DLY10_CNTRL) = T1;
100-
(DLY_ADJ => DLY10_CNTRL) = T1;
98+
(DLY_LOAD *> DLY10_CNTRL) = T1;
99+
(DLY_ADJ *> DLY10_CNTRL) = T1;
101100
(DLY_INCDEC => DLY10_CNTRL) = T1;
102101
if (DLY_ADDR == 5'd12)
103-
(DLY_LOAD => DLY12_CNTRL) = T1;
104-
(DLY_ADJ => DLY12_CNTRL) = T1;
102+
(DLY_LOAD *> DLY12_CNTRL) = T1;
103+
(DLY_ADJ *> DLY12_CNTRL) = T1;
105104
(DLY_INCDEC => DLY12_CNTRL) = T1;
106105
if (DLY_ADDR == 5'd13)
107-
(DLY_LOAD => DLY13_CNTRL) = T1;
108-
(DLY_ADJ => DLY13_CNTRL) = T1;
106+
(DLY_LOAD *> DLY13_CNTRL) = T1;
107+
(DLY_ADJ *> DLY13_CNTRL) = T1;
109108
(DLY_INCDEC => DLY13_CNTRL) = T1;
110109
if (DLY_ADDR == 5'd14)
111-
(DLY_LOAD => DLY14_CNTRL) = T1;
112-
(DLY_ADJ => DLY14_CNTRL) = T1;
110+
(DLY_LOAD *> DLY14_CNTRL) = T1;
111+
(DLY_ADJ *> DLY14_CNTRL) = T1;
113112
(DLY_INCDEC => DLY14_CNTRL) = T1;
114113
if (DLY_ADDR == 5'd15)
115-
(DLY_LOAD => DLY15_CNTRL) = T1;
116-
(DLY_ADJ => DLY15_CNTRL) = T1;
114+
(DLY_LOAD *> DLY15_CNTRL) = T1;
115+
(DLY_ADJ *> DLY15_CNTRL) = T1;
117116
(DLY_INCDEC => DLY15_CNTRL) = T1;
118117
if (DLY_ADDR == 5'd16)
119-
(DLY_LOAD => DLY16_CNTRL) = T1;
120-
(DLY_ADJ => DLY16_CNTRL) = T1;
118+
(DLY_LOAD *> DLY16_CNTRL) = T1;
119+
(DLY_ADJ *> DLY16_CNTRL) = T1;
121120
(DLY_INCDEC => DLY16_CNTRL) = T1;
122121
if (DLY_ADDR == 5'd17)
123-
(DLY_LOAD => DLY17_CNTRL) = T1;
124-
(DLY_ADJ => DLY17_CNTRL) = T1;
122+
(DLY_LOAD *> DLY17_CNTRL) = T1;
123+
(DLY_ADJ *> DLY17_CNTRL) = T1;
125124
(DLY_INCDEC => DLY17_CNTRL) = T1;
126125
if (DLY_ADDR == 5'd18)
127-
(DLY_LOAD => DLY18_CNTRL) = T1;
128-
(DLY_ADJ => DLY18_CNTRL) = T1;
126+
(DLY_LOAD *> DLY18_CNTRL) = T1;
127+
(DLY_ADJ *> DLY18_CNTRL) = T1;
129128
(DLY_INCDEC => DLY18_CNTRL) = T1;
130129
if (DLY_ADDR == 5'd19)
131-
(DLY_LOAD => DLY19_CNTRL) = T1;
132-
(DLY_ADJ => DLY19_CNTRL) = T1;
130+
(DLY_LOAD *> DLY19_CNTRL) = T1;
131+
(DLY_ADJ *> DLY19_CNTRL) = T1;
133132
(DLY_INCDEC => DLY19_CNTRL) = T1;
134133

135134
endspecify

‎models_internal/verilog/inc/DLY_VALUE_MUX.inc.v

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,8 @@ end
5656
(DLY_TAP9_VAL => DLY_TAP_VALUE) = T1;
5757
if (DLY_ADDR == 5'd10)
5858
(DLY_TAP10_VAL => DLY_TAP_VALUE) = T1;
59+
if (DLY_ADDR == 5'd11)
60+
(DLY_TAP11_VAL => DLY_TAP_VALUE) = T1;
5961
if (DLY_ADDR == 5'd12)
6062
(DLY_TAP12_VAL => DLY_TAP_VALUE) = T1;
6163
if (DLY_ADDR == 5'd13)

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