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muhammadhamza15muhammadhamza15
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Merge pull request #58 from AllahWasya/main
updated BRAM 36K and 18K models and FIFO 36K tb
2 parents 6f78ba5 + b60f8b0 commit 71b9b04

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5 files changed

+117
-63
lines changed

5 files changed

+117
-63
lines changed

‎models_internal/verilog/TDP_RAM18KX2.v

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,6 @@ module TDP_RAM18KX2 #(
6363
output reg [1:0] RPARITY_B2 = {2{1'b0}} // Read parity port B, RAM 2
6464
);
6565

66-
6766
//RAM1
6867
localparam A1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A1);
6968
localparam A1_WRITE_ADDR_WIDTH = calc_depth(A1_DATA_WRITE_WIDTH);
@@ -168,13 +167,13 @@ module TDP_RAM18KX2 #(
168167
`endif
169168
end
170169
end
171-
else
170+
else begin
172171
`ifndef FIFO
173172
// verilator lint_off BLKANDNBLK
174173
RPARITY_A1 <= 2'bx;
175174
// verilator lint_on BLKANDNBLK
176175
`endif
177-
176+
end
178177
always @(posedge CLK_B1)
179178
if (WEN_B1) begin
180179
for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin
@@ -211,12 +210,13 @@ module TDP_RAM18KX2 #(
211210
`endif
212211
end
213212
end
214-
else
213+
else begin
215214
`ifndef FIFO
216215
// verilator lint_off BLKANDNBLK
217216
RPARITY_B1 <= 2'bx;
218217
// verilator lint_on BLKANDNBLK
219218
`endif
219+
end
220220
end
221221
endgenerate
222222

@@ -280,12 +280,13 @@ module TDP_RAM18KX2 #(
280280
#collision_window;
281281
collision_a_read_flag = 0;
282282
end
283-
else
283+
else begin
284284
`ifndef FIFO
285285
// verilator lint_off BLKANDNBLK
286286
RDATA_A1 <= 16'bx;
287287
// verilator lint_on BLKANDNBLK
288288
`endif
289+
end
289290

290291
always @(posedge CLK_B1)
291292
if (WEN_B1) begin
@@ -333,13 +334,13 @@ module TDP_RAM18KX2 #(
333334
#collision_window;
334335
collision_b_read_flag = 0;
335336
end
336-
else
337+
else begin
337338
`ifndef FIFO
338339
// verilator lint_off BLKANDNBLK
339340
RDATA_B1 <= 16'bx;
340341
// verilator lint_on BLKANDNBLK
341342
`endif
342-
343+
end
343344
// Collision checking
344345
always @(posedge collision_a_write_flag) begin
345346
if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin
@@ -479,12 +480,13 @@ module TDP_RAM18KX2 #(
479480
`endif
480481
end
481482
end
482-
else
483+
else begin
483484
`ifndef FIFO
484485
// verilator lint_off BLKANDNBLK
485486
RPARITY_A2 <= 2'bx;
486487
// verilator lint_on BLKANDNBLK
487488
`endif
489+
end
488490

489491
always @(posedge CLK_B2)
490492
if (WEN_B2) begin
@@ -522,12 +524,13 @@ module TDP_RAM18KX2 #(
522524
`endif
523525
end
524526
end
525-
else
527+
else begin
526528
`ifndef FIFO
527529
// verilator lint_off BLKANDNBLK
528530
RPARITY_B2 <= 2'bx;
529531
// verilator lint_on BLKANDNBLK
530532
`endif
533+
end
531534
end
532535
endgenerate
533536

@@ -591,13 +594,13 @@ module TDP_RAM18KX2 #(
591594
#collision_window;
592595
collision_a2_read_flag = 0;
593596
end
594-
else
595-
`ifndef FIFO
597+
else begin
598+
`ifndef FIFO
596599
// verilator lint_off BLKANDNBLK
597600
RDATA_A2 <= 16'bx;
598601
// verilator lint_on BLKANDNBLK
599602
`endif
600-
603+
end
601604
always @(posedge CLK_B2)
602605
if (WEN_B2) begin
603606
for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin
@@ -644,12 +647,13 @@ module TDP_RAM18KX2 #(
644647
#collision_window;
645648
collision_b2_read_flag = 0;
646649
end
647-
else
650+
else begin
648651
`ifndef FIFO
649652
// verilator lint_off BLKANDNBLK
650653
RDATA_B2 <= 16'bx;
651654
// verilator lint_on BLKANDNBLK
652655
`endif
656+
end
653657

654658
// Collision checking
655659
always @(posedge collision_a2_write_flag) begin

‎models_internal/verilog/TDP_RAM36K.v

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -140,13 +140,14 @@ module TDP_RAM36K #(
140140
`endif
141141
end
142142
end
143-
else
144-
`ifndef FIFO
143+
else begin
144+
`ifndef FIFO
145+
145146
// verilator lint_off BLKANDNBLK
146147
RPARITY_A <= 4'bx;
147148
// verilator lint_on BLKANDNBLK
148149
`endif
149-
150+
end
150151

151152
always @(posedge CLK_B)
152153
if (WEN_B) begin
@@ -185,12 +186,13 @@ module TDP_RAM36K #(
185186
`endif
186187
end
187188
end
188-
else
189+
else begin
189190
`ifndef FIFO
190191
// verilator lint_off BLKANDNBLK
191192
RPARITY_B <= 4'bx;
192193
// verilator lint_on BLKANDNBLK
193194
`endif
195+
end
194196
end
195197
endgenerate
196198

@@ -253,12 +255,13 @@ module TDP_RAM36K #(
253255
#collision_window;
254256
collision_a_read_flag = 0;
255257
end
256-
else
258+
else begin
257259
`ifndef FIFO
258260
// verilator lint_off BLKANDNBLK
259261
RDATA_A <= 32'bx;
260262
// verilator lint_on BLKANDNBLK
261263
`endif
264+
end
262265

263266
always @(posedge CLK_B)
264267
if (WEN_B) begin
@@ -304,13 +307,13 @@ module TDP_RAM36K #(
304307
#collision_window;
305308
collision_b_read_flag = 0;
306309
end
307-
else
310+
else begin
308311
`ifndef FIFO
309312
// verilator lint_off BLKANDNBLK
310313
RDATA_B <= 32'bx;
311314
// verilator lint_on BLKANDNBLK
312315
`endif
313-
316+
end
314317

315318
/*
316319
always @(posedge CLK_B)
@@ -478,8 +481,7 @@ module TDP_RAM36K #(
478481

479482
initial
480483
$timeformat(-9,0," ns", 5);
481-
482-
initial begin
484+
initial begin
483485
case(WRITE_WIDTH_A)
484486
1 ,
485487
2 ,

‎models_internal/verilog/inc/TDP_RAM18KX2.inc.v

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11

2-
32
//RAM1
43
localparam A1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A1);
54
localparam A1_WRITE_ADDR_WIDTH = calc_depth(A1_DATA_WRITE_WIDTH);
@@ -104,13 +103,13 @@
104103
`endif
105104
end
106105
end
107-
else
106+
else begin
108107
`ifndef FIFO
109108
// verilator lint_off BLKANDNBLK
110109
RPARITY_A1 <= 2'bx;
111110
// verilator lint_on BLKANDNBLK
112111
`endif
113-
112+
end
114113
always @(posedge CLK_B1)
115114
if (WEN_B1) begin
116115
for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin
@@ -147,12 +146,13 @@
147146
`endif
148147
end
149148
end
150-
else
149+
else begin
151150
`ifndef FIFO
152151
// verilator lint_off BLKANDNBLK
153152
RPARITY_B1 <= 2'bx;
154153
// verilator lint_on BLKANDNBLK
155154
`endif
155+
end
156156
end
157157
endgenerate
158158

@@ -216,12 +216,13 @@
216216
#collision_window;
217217
collision_a_read_flag = 0;
218218
end
219-
else
219+
else begin
220220
`ifndef FIFO
221221
// verilator lint_off BLKANDNBLK
222222
RDATA_A1 <= 16'bx;
223223
// verilator lint_on BLKANDNBLK
224224
`endif
225+
end
225226

226227
always @(posedge CLK_B1)
227228
if (WEN_B1) begin
@@ -269,13 +270,13 @@
269270
#collision_window;
270271
collision_b_read_flag = 0;
271272
end
272-
else
273+
else begin
273274
`ifndef FIFO
274275
// verilator lint_off BLKANDNBLK
275276
RDATA_B1 <= 16'bx;
276277
// verilator lint_on BLKANDNBLK
277278
`endif
278-
279+
end
279280
// Collision checking
280281
always @(posedge collision_a_write_flag) begin
281282
if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin
@@ -415,12 +416,13 @@
415416
`endif
416417
end
417418
end
418-
else
419+
else begin
419420
`ifndef FIFO
420421
// verilator lint_off BLKANDNBLK
421422
RPARITY_A2 <= 2'bx;
422423
// verilator lint_on BLKANDNBLK
423424
`endif
425+
end
424426

425427
always @(posedge CLK_B2)
426428
if (WEN_B2) begin
@@ -458,12 +460,13 @@
458460
`endif
459461
end
460462
end
461-
else
463+
else begin
462464
`ifndef FIFO
463465
// verilator lint_off BLKANDNBLK
464466
RPARITY_B2 <= 2'bx;
465467
// verilator lint_on BLKANDNBLK
466468
`endif
469+
end
467470
end
468471
endgenerate
469472

@@ -527,13 +530,13 @@
527530
#collision_window;
528531
collision_a2_read_flag = 0;
529532
end
530-
else
531-
`ifndef FIFO
533+
else begin
534+
`ifndef FIFO
532535
// verilator lint_off BLKANDNBLK
533536
RDATA_A2 <= 16'bx;
534537
// verilator lint_on BLKANDNBLK
535538
`endif
536-
539+
end
537540
always @(posedge CLK_B2)
538541
if (WEN_B2) begin
539542
for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin
@@ -580,12 +583,13 @@
580583
#collision_window;
581584
collision_b2_read_flag = 0;
582585
end
583-
else
586+
else begin
584587
`ifndef FIFO
585588
// verilator lint_off BLKANDNBLK
586589
RDATA_B2 <= 16'bx;
587590
// verilator lint_on BLKANDNBLK
588591
`endif
592+
end
589593

590594
// Collision checking
591595
always @(posedge collision_a2_write_flag) begin

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