Merge pull request #60 from baberali-pro/soc_fpga_intf_model_tb

removing dma design

Author: muhammadhamza15

models_internal/verilog/SOC_FPGA_INTF_DMA.v

@@ -14,18 +14,5 @@ module SOC_FPGA_INTF_DMA (
   input DMA_RST_N // DMA reset
 );
 
-
-reg [3:0] dma_ack;
-assign DMA_ACK = dma_ack;
-
-always@(posedge DMA_CLK) begin
-  if(!DMA_RST_N) begin
-    dma_ack <= 4'b0;
-  end 
-  else begin
-    dma_ack <= DMA_REQ;
-  end
-end
-
 endmodule
 `endcelldefine

models_internal/verilog/inc/SOC_FPGA_INTF_DMA.inc.v

@@ -1,13 +0,0 @@
-
-
-reg [3:0] dma_ack;
-assign DMA_ACK = dma_ack;
-
-always@(posedge DMA_CLK) begin
-  if(!DMA_RST_N) begin
-    dma_ack <= 4'b0;
-  end 
-  else begin
-    dma_ack <= DMA_REQ;
-  end
-end