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1 parent a069f1e commit af18805Copy full SHA for af18805
tlv_lib/tiny_tapeout_lib.tlv
@@ -61,7 +61,7 @@
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endmodule
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'])
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\SV
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- m4_include_lib(['https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/9ae5675b73c9d0084220968f027ac1fd84cebec7/tlv_lib/fpga_includes.tlv'])
+ m4_include_lib(['https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlv_lib/fpga_includes.tlv'])
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// Map TT I/Os to Virtual Lab.
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\TLV tt_connections()
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