Added CITATION.cff and minor updates.

Author: stevehoover

CITATION.cff

@@ -0,0 +1,23 @@
+title: "Virtual FPGA Lab"
+authors:
+  - family-names: "Hoover"
+    given-names: "Steven"
+    orcid: "0000-0001-5844-2889"
+    affiliation: "Redwood EDA, LLC"
+contributors:
+  - family-names: "Bala"
+    given-names: "Dhinesh"
+date-released: "2018-08-14"
+repository-code: "https://github.com/os-fpga/Virtual-FPGA-Lab"
+url: "https://github.com/os-fpga/Virtual-FPGA-Lab"
+abstract: >
+  The Virtual FPGA Lab is a virtual environment for FPGA development using the Makerchip
+  IDE. It uses Makerchip's Visual Debug feature to provide a visual representation of the
+  workbench (the FPGA board and peripherals), showing how the logic affects I/Os, such as
+  LEDs and 7-segment displays.
+keywords:
+  - FPGA
+  - Digital Twin
+  - Open-source
+  - Web Platform
+license: "MIT"

README.md

@@ -13,6 +13,8 @@ This document introduces the Virtual FPGA Lab. Separate documents will help you
 
   - [FPGA training using this platform](https://github.com/stevehoover/GettingStartedWithFPGAs)
   - [Exporting to your FPGA board (if supported)](fpga/readme.md)
+  - TL-Verilog info: [for humans](https://tl-x.org) [for LLMs](https://gitlab.com/rweda/Makerchip-public)
+
 
 
 ## What are FPGAs?
@@ -297,6 +299,7 @@ In our efforts, we've come across the following related projects. (Appearance on
 
 
 ## Sponsors
+
 This work has been sponsored through the OSFPGA Foundation and Google Summer of Code (GSoC) 2021(with the Free and Open Source Silicon Foundation (FOSSi) as a GSoC umbrella organization), with mentorship from Redwood EDA, LLC, and with training support from VLSI System Design.
 <p>
     <img src="https://user-images.githubusercontent.com/64545984/152572571-1e10d2fa-acc6-4048-8d73-1be63267b778.png" alt="gsoc-logo" height="80"><span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>

fpga/readme.md

@@ -3,8 +3,7 @@
 ## Installation and Overview of SandPiper
 
 * [SandPiper](https://www.redwoodeda.com/products) is a code generator that generates readable, well-structured, Verilog or SystemVerilog\ code from the given TL-Verilog code.
-* [SandPiper SaaS Edition](https://pypi.org/project/sandpiper-saas/) runs as a microservice in the cloud to support easy open-source development. Install Sanpiper SaaS Edition for this project. 
-* To run locally, SandPiper Education Edition can be requested from [RedwoodEDA](https://www.redwoodeda.com/products)
+* [SandPiper SaaS Edition](https://pypi.org/project/sandpiper-saas/) runs as a microservice in the cloud to support easy open-source development. Install Sanpiper SaaS Edition for this project.
 
 ## Steps to run FPGA setup
 

tlv_lib/fpga_includes.tlv

@@ -931,11 +931,12 @@
       // 4: ICEBREAKER_ID
       // 5: NEXYS_ID
       // 6: CLEAR_ID
-      // 7: TINY_TAPEOUT_ID
-      m4+board(/board, /fpga, 7, *,
+      // 7: TINY_TAPEOUT_ID  // (Currently only in the "tt" branch.)
+      m5_var(board, 2)
+      m4+board(/board, /fpga, m5_board, *,
                ['top: 0, left: 0, width: 7000, height: 7000'],
                riscv_main)  // riscv_main or simple_main.
-      m5+tt_input_labels_viz(['"UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED"'])
+      m5_if_eq(m5_board, 7, ['m5+tt_input_labels_viz(['"UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED"'])'])
 
       /// TODO: RGB LEDs and external 7-Segment remain to be cleaned up.
       ///m4+ifelse(m4_fpga_io_rgb_leds_defined, 1,