QSPI access issue on ICICLE kit HSS v2022.09 and ICICLEkitreference design v2022.09

[OrlyShdema]

Hi ,
Need your advise regarding the qspi access issue as seen in the hss (V2022.09).
All checked in the icicle board by my customer.

We use the mss configurator to enable the qspi (bank 2+4), routed to the Icicle microbus socket (J44+J8).

1.   The '.config' configured to use the qspi (attached).
   

2.   The mss configurator xml added to the project (attached): /hart-software-services/boards/mpfs-icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_mss_cfg.xml.
   

3.   The SoftConsole hss project cleaned and rebuilt.
   

I run the hss (loadit from Softconsole, not from the eNVM) and checked the transactions on the qspi bus. The clock and data monitored by scope, all stuck in '1' and no toggling.
I noticed that although register 0x214 configured in the xml, hw_mssio_mux.h generated correctly, there is no change in the register configuration (which still configured to the default spi) pls. see attached captre1.
As far as I understand, the MSS doesn't configured according to the mss configuration.

I returned to the HSS version 2021.11.
In this version the mss is configured to the qspi by default (xml register 0x214), and it also configure the register correctly: (see capture2)
I only enable the qspi in the .config.
In this version I can read the flash ID..

it seems like somthing was chsged on v2022.09that cause the MSS io Registers not to be correctly configured.

Pls. advise.

ATT81140.zip
ICICLE_MSS_mss_cfg.zip

[sanjeevb-bansal]

The following flash memory devices are officially supported on PolarFire SoC both in HSS and baremetal:

Manufacturer	Part No.	Type	Density
Winbond	W25N01GV	NAND	1Gb (128MB)
Micron*	MT25QL256	NOR	256Mb (32MB)

The procedure is outlined here for Icicle kit:-
https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-generic/booting-from-qspi/booting-from-qspi.md

This issue doesn't seem to be the HSS boot loader, looks like the I/O's are not configured correctly. Can you pls test it first test using the bare metal example given below:-

https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples/tree/main/driver-examples/mss/mss-qspi

We might need to have a call with you for correctly configuring IO's using the MSS configurator. I noticed that you have created a Microchip Tech Support case no. 01157427. If this issue still persist, let's get your issue resolved thru a Webex call in the case portal.