TLB flush:Why is the TLB flushed when the CR3 register is set?

[ZDeHn]

I've been engaged in some TLB optimization work based on gem5 recently. By configuring the CPUID in X86ISA.py, I've made the current timing CPU support the PCID function. During the debugging and application process, the PCID function seems to operate without any problems. However, there's one thing that's really puzzling me: if the current CPU supports PCID, is it still necessary to flush the TLB when setting the CR3 register? If flushing isn't required, how will the old TLB entries be refreshed when a process exits?

case misc_reg::Cr3: static_cast<MMU *>(tc->getMMUPtr())->flushNonGlobal();

[powerjg]

This is a requirement of the x86 ISA. Since the TLB is "tagged" by virtual address, when the process being executed changes you have to flush the TLB. If PCID is enabled, then you may be able to get away without flushing the TLB, but I would have to go back a re-read the x86 ISA description to figure out the details.

Also, we don't fully support PCID. If you boot linux, PCID is not enabled.