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    71 repositories

    • VeeR-EL2-RISC-V-Core

      Public
      SystemVerilog
      •
      Apache License 2.0
      •74•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • VexRiscV

      Public
      An FPGA Friendly 32-Bit RISC-V CPU Implementation
      Assembly
      •
      MIT License
      •411•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • NEORV32-RISC-V-Processor

      Public
      32-Bit RISC-V Soft-Core CPU
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •219•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •20•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • CORE-V-CVA6-RISC-V-CPU

      Public
      Application Class 6-Stage RISC-V CPU Capable of Booting Linux
      Assembly
      •
      Other
      •675•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • Cheshire

      Public
      A Minimal Linux-Capable 64-Bit RISC-V SoC Built Around CVA6
      Verilog
      •
      Other
      •39•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • PULP-Ara

      Public
      A 64-Bit Vector Unit, Compatible With the RISC-V Vector Extension Version 1.0, Working as a Coprocessor to CORE-V's CVA6 Core
      C
      •
      Other
      •126•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • Spatz

      Public
      Spatz is a Compact RISC-V-Based Vector Processor Meant for High-Performance, Small Computing Clusters
      C
      •
      Apache License 2.0
      •14•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • CORE-V-Wally

      Public
      Configurable RISC-V Processor Associated With RISC-V System-on-Chip Design Textbook. Contains a 5-Stage Pipeline, Support for A, B, C, D, F, M and Q extensions, and Optional Caches, BP, FPU, VM/MMU, AHB, RAMs, and Peripherals
      C
      •
      Other
      •177•0•0•0•Updated Sep 18, 2024Sep 18, 2024

    • Snitch-Cluster

      Public
      An Energy-Efficient RISC-V Floating-Point Compute Cluster.
      C
      •
      Apache License 2.0
      •48•0•0•0•Updated Sep 10, 2024Sep 10, 2024

    • bcc

      Public
      BCC - Tools for BPF-based Linux IO analysis, networking, monitoring, and more
      C
      •
      Apache License 2.0
      •3.9k•0•0•0•Updated Sep 8, 2024Sep 8, 2024

    • kernel-hardening-checker

      Public
      A tool for checking the security hardening options of the Linux kernel
      Python
      •
      GNU General Public License v3.0
      •152•0•0•0•Updated Sep 4, 2024Sep 4, 2024

    • UVM-Core

      Public
      SystemVerilog
      •
      Apache License 2.0
      •19•0•0•0•Updated Sep 3, 2024Sep 3, 2024

    • PULP-CVFPU

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •113•0•0•0•Updated Aug 29, 2024Aug 29, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •26•0•0•0•Updated Aug 28, 2024Aug 28, 2024

    • CORE-V-High-Performance-L1-D-Cache

      Public
      Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache
      SystemVerilog
      •
      Other
      •18•0•0•0•Updated Aug 20, 2024Aug 20, 2024

    • CORE-V-CV32E40S-RISC-V-CPU

      Public
      4-Stage, In-Order, Secure RISC-V Core Based on the CV32E40P
      SystemVerilog
      •
      Other
      •22•0•0•0•Updated Aug 16, 2024Aug 16, 2024

    • CORE-V-CV32E40X-RISC-V-CPU

      Public
      4-Stage, In-Order, Compute RISC-V Core Based on the CV32E40P
      SystemVerilog
      •
      Other
      •49•0•0•0•Updated Aug 8, 2024Aug 8, 2024

    • AXI-From-PULP-Platform

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •256•0•0•0•Updated Jul 31, 2024Jul 31, 2024

    • SystemC

      Public
      SystemC Reference Implementation
      C++
      •
      Apache License 2.0
      •152•0•0•0•Updated Jul 31, 2024Jul 31, 2024

    • XilinxBoardStore

      Public
      Python
      •
      Other
      •271•0•0•0•Updated Jul 30, 2024Jul 30, 2024

    • CORE-V-LLVM

      Public
      Other
      •18•0•0•0•Updated Jul 26, 2024Jul 26, 2024

    • CORE-V-CV32E40P-RISC-V-CPU

      Public
      In-Order 4-Stage RISC-V RV32IMFCXpulp CPU Based on RI5CY from PULP-Platform
      SystemVerilog
      •
      Other
      •412•0•0•0•Updated Jul 19, 2024Jul 19, 2024

    • CORE-V-GCC

      Public
      C++
      •
      GNU General Public License v2.0
      •23•0•0•0•Updated Jul 19, 2024Jul 19, 2024

    • RISC-V-IOMMU-Specification

      Public
      C
      •
      Creative Commons Attribution 4.0 International
      •16•0•0•0•Updated Jul 15, 2024Jul 15, 2024

    • SystemC-Common-Practices

      Public
      SystemC Common Practices (SCP)
      C++
      •
      Apache License 2.0
      •13•0•0•0•Updated Jul 12, 2024Jul 12, 2024

    • VexIIRiscV

      Public
      Like VexRiscV, but, Harder, Better, Faster, Stronger
      Scala
      •
      MIT License
      •10•0•0•0•Updated Jul 11, 2024Jul 11, 2024

    • GHDL

      Public
      VHDL 2008/93/87 Simulator
      VHDL
      •
      GNU General Public License v2.0
      •360•0•0•0•Updated Jul 11, 2024Jul 11, 2024

    • Chisel

      Public
      A Modern Hardware Design Language
      Scala
      •
      Apache License 2.0
      •590•0•0•0•Updated Jul 10, 2024Jul 10, 2024

    • RISC-V-DV

      Public
      Random Instruction Generator for RISC-V Processor Verification
      Python
      •
      Apache License 2.0
      •322•0•0•0•Updated Jul 10, 2024Jul 10, 2024