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[GR-53463] Update to LLVM 18.
PullRequest: graal/17522
2 parents 8da6491 + cfe3356 commit 1ba933e

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‎espresso/mx.espresso/suite.py‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
#
2-
# Copyright (c) 2017, 2023, Oracle and/or its affiliates. All rights reserved.
2+
# Copyright (c) 2017, 2024, Oracle and/or its affiliates. All rights reserved.
33
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
#
55
# This code is free software; you can redistribute it and/or modify it
@@ -289,6 +289,8 @@
289289
"ldflags": [
290290
"-Wl,-soname,libjvm.so",
291291
"-Wl,--version-script,<path:espresso:com.oracle.truffle.espresso.mokapot>/mapfile-vers",
292+
# newer LLVM versions default to --no-undefined-version
293+
"-Wl,--undefined-version",
292294
],
293295
"toolchain": "sulong:SULONG_BOOTSTRAP_TOOLCHAIN",
294296
},
@@ -299,6 +301,8 @@
299301
"ldflags": [
300302
"-Wl,-soname,libjvm.so",
301303
"-Wl,--version-script,<path:espresso:com.oracle.truffle.espresso.mokapot>/mapfile-vers",
304+
# newer LLVM versions default to --no-undefined-version
305+
"-Wl,--undefined-version",
302306
],
303307
"toolchain": "sulong:SULONG_BOOTSTRAP_TOOLCHAIN",
304308
},

‎sdk/llvm-patches/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,5 +3,5 @@ LLVM Upstream Patches
33

44
This directory contains patches which were used to build this
55
LLVM distribution but are not yet upstream or have been backported
6-
to LLVM 16. To build this LLVM distribution yourself, apply the patches
7-
on top of an LLVM [16.0.1](https://github.com/llvm/llvm-project/tree/llvmorg-16.0.1) source tree.
6+
to LLVM 18. To build this LLVM distribution yourself, apply the patches
7+
on top of an LLVM [18.1.3](https://github.com/llvm/llvm-project/tree/llvmorg-18.1.3) source tree.

‎sdk/llvm-patches/native-image/0001-GR-17692-Statepoints-Support-for-compressed-pointers.patch‎

Lines changed: 0 additions & 428 deletions
This file was deleted.

‎sdk/llvm-patches/native-image/0002-GR-23578-AArch64-Introduce-option-to-force-placement.patch‎ renamed to ‎sdk/llvm-patches/native-image/0001-GR-23578-AArch64-Introduce-option-to-force-placement.patch‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
1-
From fd62b39067475f734e00eddda5096ade9095aaa4 Mon Sep 17 00:00:00 2001
1+
From 73ff46f9f97161d099d22ed46d89148a868a5960 Mon Sep 17 00:00:00 2001
22
From: Loic Ottet <loic.ottet@oracle.com>
33
Date: Tue, 8 Sep 2020 13:03:06 +0200
4-
Subject: [PATCH 2/4] [GR-23578][AArch64] Introduce option to force placement
4+
Subject: [PATCH 1/4] [GR-23578][AArch64] Introduce option to force placement
55
of the frame record on top of the stack frame
66

77
---
88
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 7 +++++++
99
1 file changed, 7 insertions(+)
1010

1111
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
12-
index 299892ad4ede..b323ad5cc9f1 100644
12+
index 48e1c1bc7302..9742e5a93b30 100644
1313
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
1414
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
1515
@@ -39,6 +39,11 @@ using namespace llvm;
@@ -24,7 +24,7 @@ index 299892ad4ede..b323ad5cc9f1 100644
2424
AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
2525
: AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
2626
AArch64_MC::initLLVMToCVRegMapping(this);
27-
@@ -118,6 +123,8 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
27+
@@ -131,6 +136,8 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
2828
return CSR_AArch64_AAPCS_X18_SaveList;
2929
if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
3030
return CSR_AArch64_SVE_AAPCS_SaveList;
@@ -34,5 +34,5 @@ index 299892ad4ede..b323ad5cc9f1 100644
3434
}
3535

3636
--
37-
2.38.4
37+
2.42.0
3838

‎sdk/llvm-patches/native-image/0002-RISCV-NFC-Add-generateMCInstSeq-in-RISCVMatInt-84462.patch‎

Lines changed: 141 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,141 @@
1+
From 3dcd12b7e6d7487de4df1f66f01cab6afe8a5e79 Mon Sep 17 00:00:00 2001
2+
From: Sacha Coppey <sacha.coppey@oracle.com>
3+
Date: Fri, 22 Mar 2024 18:08:13 +0100
4+
Subject: [PATCH 2/4] [RISCV][NFC] Add generateMCInstSeq in RISCVMatInt
5+
(#84462)
6+
7+
This allows to avoid duplicating the code handling the instructions
8+
outputted by `generateInstSeq` when emitting `MCInst`s.
9+
10+
(cherry picked from commit d2f8ba7d6dc7251815f1431cf8715053576615f4)
11+
---
12+
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 31 ++-------------
13+
.../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 38 +++++++++++++++++++
14+
.../Target/RISCV/MCTargetDesc/RISCVMatInt.h | 5 +++
15+
3 files changed, 47 insertions(+), 27 deletions(-)
16+
17+
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
18+
index f6e8386aff45..aee63275a1a3 100644
19+
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
20+
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
21+
@@ -3081,34 +3081,11 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
22+
23+
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
24+
MCStreamer &Out) {
25+
- RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Value, getSTI());
26+
-
27+
- MCRegister SrcReg = RISCV::X0;
28+
- for (const RISCVMatInt::Inst &Inst : Seq) {
29+
- switch (Inst.getOpndKind()) {
30+
- case RISCVMatInt::Imm:
31+
- emitToStreamer(Out,
32+
- MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addImm(Inst.getImm()));
33+
- break;
34+
- case RISCVMatInt::RegX0:
35+
- emitToStreamer(
36+
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
37+
- RISCV::X0));
38+
- break;
39+
- case RISCVMatInt::RegReg:
40+
- emitToStreamer(
41+
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
42+
- SrcReg));
43+
- break;
44+
- case RISCVMatInt::RegImm:
45+
- emitToStreamer(
46+
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addImm(
47+
- Inst.getImm()));
48+
- break;
49+
- }
50+
+ SmallVector<MCInst, 8> Seq;
51+
+ RISCVMatInt::generateMCInstSeq(Value, getSTI(), DestReg, Seq);
52+
53+
- // Only the first instruction has X0 as its source.
54+
- SrcReg = DestReg;
55+
+ for (MCInst &Inst : Seq) {
56+
+ emitToStreamer(Out, Inst);
57+
}
58+
}
59+
60+
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
61+
index 4358a5b878e6..c3bae152993e 100644
62+
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
63+
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
64+
@@ -9,6 +9,7 @@
65+
#include "RISCVMatInt.h"
66+
#include "MCTargetDesc/RISCVMCTargetDesc.h"
67+
#include "llvm/ADT/APInt.h"
68+
+#include "llvm/MC/MCInstBuilder.h"
69+
#include "llvm/Support/MathExtras.h"
70+
using namespace llvm;
71+
72+
@@ -436,6 +437,43 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
73+
return Res;
74+
}
75+
76+
+void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
77+
+ MCRegister DestReg, SmallVectorImpl<MCInst> &Insts) {
78+
+ RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
79+
+
80+
+ MCRegister SrcReg = RISCV::X0;
81+
+ for (RISCVMatInt::Inst &Inst : Seq) {
82+
+ switch (Inst.getOpndKind()) {
83+
+ case RISCVMatInt::Imm:
84+
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
85+
+ .addReg(DestReg)
86+
+ .addImm(Inst.getImm()));
87+
+ break;
88+
+ case RISCVMatInt::RegX0:
89+
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
90+
+ .addReg(DestReg)
91+
+ .addReg(SrcReg)
92+
+ .addReg(RISCV::X0));
93+
+ break;
94+
+ case RISCVMatInt::RegReg:
95+
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
96+
+ .addReg(DestReg)
97+
+ .addReg(SrcReg)
98+
+ .addReg(SrcReg));
99+
+ break;
100+
+ case RISCVMatInt::RegImm:
101+
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
102+
+ .addReg(DestReg)
103+
+ .addReg(SrcReg)
104+
+ .addImm(Inst.getImm()));
105+
+ break;
106+
+ }
107+
+
108+
+ // Only the first instruction has X0 as its source.
109+
+ SrcReg = DestReg;
110+
+ }
111+
+}
112+
+
113+
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
114+
unsigned &ShiftAmt, unsigned &AddOpc) {
115+
int64_t LoVal = SignExtend64<32>(Val);
116+
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
117+
index 780f685463f3..e87e0f325647 100644
118+
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
119+
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
120+
@@ -10,6 +10,7 @@
121+
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
122+
123+
#include "llvm/ADT/SmallVector.h"
124+
+#include "llvm/MC/MCRegister.h"
125+
#include "llvm/MC/MCSubtargetInfo.h"
126+
#include <cstdint>
127+
128+
@@ -48,6 +49,10 @@ using InstSeq = SmallVector<Inst, 8>;
129+
// instruction selection.
130+
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);
131+
132+
+// Helper to generate the generateInstSeq instruction sequence using MCInsts
133+
+void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
134+
+ MCRegister DestReg, SmallVectorImpl<MCInst> &Insts);
135+
+
136+
// Helper to generate an instruction sequence that can materialize the given
137+
// immediate value into a register using an additional temporary register. This
138+
// handles cases where the constant can be generated by (ADD (SLLI X, C), X) or
139+
--
140+
2.42.0
141+

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