forked from skristiansson/linux
-
Notifications
You must be signed in to change notification settings - Fork 14
/
Copy pathcvmx-gmxx-defs.h
2529 lines (2427 loc) · 77.4 KB
/
cvmx-gmxx-defs.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_GMXX_DEFS_H__
#define __CVMX_GMXX_DEFS_H__
#define CVMX_GMXX_BAD_REG(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_BIST(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_CLK_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_HG2_CONTROL(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_INF_MODE(block_id) \
CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_NXA_ADR(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_IFG(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_PASS_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_PRTS(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_PRT_INFO(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_TX_STATUS(block_id) \
CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_SMACX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_STAT_BP(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_BURST(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_CLK(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_BP(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull))
#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_CORRUPT(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_HG2_REG1(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_HG2_REG2(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_IFG(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_INT_EN(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_JAM(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_LFSR(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_OVR_BP(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_PRTS(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_SPI_CTL(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_SPI_MAX(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull))
union cvmx_gmxx_bad_reg {
uint64_t u64;
struct cvmx_gmxx_bad_reg_s {
uint64_t reserved_31_63:33;
uint64_t inb_nxa:4;
uint64_t statovr:1;
uint64_t loststat:4;
uint64_t reserved_18_21:4;
uint64_t out_ovr:16;
uint64_t ncb_ovr:1;
uint64_t out_col:1;
} s;
struct cvmx_gmxx_bad_reg_cn30xx {
uint64_t reserved_31_63:33;
uint64_t inb_nxa:4;
uint64_t statovr:1;
uint64_t reserved_25_25:1;
uint64_t loststat:3;
uint64_t reserved_5_21:17;
uint64_t out_ovr:3;
uint64_t reserved_0_1:2;
} cn30xx;
struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
struct cvmx_gmxx_bad_reg_s cn38xx;
struct cvmx_gmxx_bad_reg_s cn38xxp2;
struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
struct cvmx_gmxx_bad_reg_cn52xx {
uint64_t reserved_31_63:33;
uint64_t inb_nxa:4;
uint64_t statovr:1;
uint64_t loststat:4;
uint64_t reserved_6_21:16;
uint64_t out_ovr:4;
uint64_t reserved_0_1:2;
} cn52xx;
struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
struct cvmx_gmxx_bad_reg_s cn58xx;
struct cvmx_gmxx_bad_reg_s cn58xxp1;
};
union cvmx_gmxx_bist {
uint64_t u64;
struct cvmx_gmxx_bist_s {
uint64_t reserved_17_63:47;
uint64_t status:17;
} s;
struct cvmx_gmxx_bist_cn30xx {
uint64_t reserved_10_63:54;
uint64_t status:10;
} cn30xx;
struct cvmx_gmxx_bist_cn30xx cn31xx;
struct cvmx_gmxx_bist_cn30xx cn38xx;
struct cvmx_gmxx_bist_cn30xx cn38xxp2;
struct cvmx_gmxx_bist_cn50xx {
uint64_t reserved_12_63:52;
uint64_t status:12;
} cn50xx;
struct cvmx_gmxx_bist_cn52xx {
uint64_t reserved_16_63:48;
uint64_t status:16;
} cn52xx;
struct cvmx_gmxx_bist_cn52xx cn52xxp1;
struct cvmx_gmxx_bist_cn52xx cn56xx;
struct cvmx_gmxx_bist_cn52xx cn56xxp1;
struct cvmx_gmxx_bist_s cn58xx;
struct cvmx_gmxx_bist_s cn58xxp1;
};
union cvmx_gmxx_clk_en {
uint64_t u64;
struct cvmx_gmxx_clk_en_s {
uint64_t reserved_1_63:63;
uint64_t clk_en:1;
} s;
struct cvmx_gmxx_clk_en_s cn52xx;
struct cvmx_gmxx_clk_en_s cn52xxp1;
struct cvmx_gmxx_clk_en_s cn56xx;
struct cvmx_gmxx_clk_en_s cn56xxp1;
};
union cvmx_gmxx_hg2_control {
uint64_t u64;
struct cvmx_gmxx_hg2_control_s {
uint64_t reserved_19_63:45;
uint64_t hg2tx_en:1;
uint64_t hg2rx_en:1;
uint64_t phys_en:1;
uint64_t logl_en:16;
} s;
struct cvmx_gmxx_hg2_control_s cn52xx;
struct cvmx_gmxx_hg2_control_s cn52xxp1;
struct cvmx_gmxx_hg2_control_s cn56xx;
};
union cvmx_gmxx_inf_mode {
uint64_t u64;
struct cvmx_gmxx_inf_mode_s {
uint64_t reserved_10_63:54;
uint64_t speed:2;
uint64_t reserved_6_7:2;
uint64_t mode:2;
uint64_t reserved_3_3:1;
uint64_t p0mii:1;
uint64_t en:1;
uint64_t type:1;
} s;
struct cvmx_gmxx_inf_mode_cn30xx {
uint64_t reserved_3_63:61;
uint64_t p0mii:1;
uint64_t en:1;
uint64_t type:1;
} cn30xx;
struct cvmx_gmxx_inf_mode_cn31xx {
uint64_t reserved_2_63:62;
uint64_t en:1;
uint64_t type:1;
} cn31xx;
struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
struct cvmx_gmxx_inf_mode_cn52xx {
uint64_t reserved_10_63:54;
uint64_t speed:2;
uint64_t reserved_6_7:2;
uint64_t mode:2;
uint64_t reserved_2_3:2;
uint64_t en:1;
uint64_t type:1;
} cn52xx;
struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
};
union cvmx_gmxx_nxa_adr {
uint64_t u64;
struct cvmx_gmxx_nxa_adr_s {
uint64_t reserved_6_63:58;
uint64_t prt:6;
} s;
struct cvmx_gmxx_nxa_adr_s cn30xx;
struct cvmx_gmxx_nxa_adr_s cn31xx;
struct cvmx_gmxx_nxa_adr_s cn38xx;
struct cvmx_gmxx_nxa_adr_s cn38xxp2;
struct cvmx_gmxx_nxa_adr_s cn50xx;
struct cvmx_gmxx_nxa_adr_s cn52xx;
struct cvmx_gmxx_nxa_adr_s cn52xxp1;
struct cvmx_gmxx_nxa_adr_s cn56xx;
struct cvmx_gmxx_nxa_adr_s cn56xxp1;
struct cvmx_gmxx_nxa_adr_s cn58xx;
struct cvmx_gmxx_nxa_adr_s cn58xxp1;
};
union cvmx_gmxx_prtx_cbfc_ctl {
uint64_t u64;
struct cvmx_gmxx_prtx_cbfc_ctl_s {
uint64_t phys_en:16;
uint64_t logl_en:16;
uint64_t phys_bp:16;
uint64_t reserved_4_15:12;
uint64_t bck_en:1;
uint64_t drp_en:1;
uint64_t tx_en:1;
uint64_t rx_en:1;
} s;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
};
union cvmx_gmxx_prtx_cfg {
uint64_t u64;
struct cvmx_gmxx_prtx_cfg_s {
uint64_t reserved_14_63:50;
uint64_t tx_idle:1;
uint64_t rx_idle:1;
uint64_t reserved_9_11:3;
uint64_t speed_msb:1;
uint64_t reserved_4_7:4;
uint64_t slottime:1;
uint64_t duplex:1;
uint64_t speed:1;
uint64_t en:1;
} s;
struct cvmx_gmxx_prtx_cfg_cn30xx {
uint64_t reserved_4_63:60;
uint64_t slottime:1;
uint64_t duplex:1;
uint64_t speed:1;
uint64_t en:1;
} cn30xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
struct cvmx_gmxx_prtx_cfg_s cn52xx;
struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
struct cvmx_gmxx_prtx_cfg_s cn56xx;
struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam0 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam0_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam1 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam1_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam2 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam2_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam3 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam3_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam4 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam4_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam5 {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam5_s {
uint64_t adr:64;
} s;
struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_cam_en {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_cam_en_s {
uint64_t reserved_8_63:56;
uint64_t en:8;
} s;
struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
};
union cvmx_gmxx_rxx_adr_ctl {
uint64_t u64;
struct cvmx_gmxx_rxx_adr_ctl_s {
uint64_t reserved_4_63:60;
uint64_t cam_mode:1;
uint64_t mcst:2;
uint64_t bcst:1;
} s;
struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
};
union cvmx_gmxx_rxx_decision {
uint64_t u64;
struct cvmx_gmxx_rxx_decision_s {
uint64_t reserved_5_63:59;
uint64_t cnt:5;
} s;
struct cvmx_gmxx_rxx_decision_s cn30xx;
struct cvmx_gmxx_rxx_decision_s cn31xx;
struct cvmx_gmxx_rxx_decision_s cn38xx;
struct cvmx_gmxx_rxx_decision_s cn38xxp2;
struct cvmx_gmxx_rxx_decision_s cn50xx;
struct cvmx_gmxx_rxx_decision_s cn52xx;
struct cvmx_gmxx_rxx_decision_s cn52xxp1;
struct cvmx_gmxx_rxx_decision_s cn56xx;
struct cvmx_gmxx_rxx_decision_s cn56xxp1;
struct cvmx_gmxx_rxx_decision_s cn58xx;
struct cvmx_gmxx_rxx_decision_s cn58xxp1;
};
union cvmx_gmxx_rxx_frm_chk {
uint64_t u64;
struct cvmx_gmxx_rxx_frm_chk_s {
uint64_t reserved_10_63:54;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} s;
struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
struct cvmx_gmxx_rxx_frm_chk_cn50xx {
uint64_t reserved_10_63:54;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t reserved_6_6:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t reserved_2_2:1;
uint64_t carext:1;
uint64_t reserved_0_0:1;
} cn50xx;
struct cvmx_gmxx_rxx_frm_chk_cn52xx {
uint64_t reserved_9_63:55;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t reserved_5_6:2;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t reserved_2_2:1;
uint64_t carext:1;
uint64_t reserved_0_0:1;
} cn52xx;
struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
};
union cvmx_gmxx_rxx_frm_ctl {
uint64_t u64;
struct cvmx_gmxx_rxx_frm_ctl_s {
uint64_t reserved_11_63:53;
uint64_t null_dis:1;
uint64_t pre_align:1;
uint64_t pad_len:1;
uint64_t vlan_len:1;
uint64_t pre_free:1;
uint64_t ctl_smac:1;
uint64_t ctl_mcst:1;
uint64_t ctl_bck:1;
uint64_t ctl_drp:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} s;
struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
uint64_t reserved_9_63:55;
uint64_t pad_len:1;
uint64_t vlan_len:1;
uint64_t pre_free:1;
uint64_t ctl_smac:1;
uint64_t ctl_mcst:1;
uint64_t ctl_bck:1;
uint64_t ctl_drp:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} cn30xx;
struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
uint64_t reserved_8_63:56;
uint64_t vlan_len:1;
uint64_t pre_free:1;
uint64_t ctl_smac:1;
uint64_t ctl_mcst:1;
uint64_t ctl_bck:1;
uint64_t ctl_drp:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} cn31xx;
struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
uint64_t reserved_11_63:53;
uint64_t null_dis:1;
uint64_t pre_align:1;
uint64_t reserved_7_8:2;
uint64_t pre_free:1;
uint64_t ctl_smac:1;
uint64_t ctl_mcst:1;
uint64_t ctl_bck:1;
uint64_t ctl_drp:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} cn50xx;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
uint64_t reserved_10_63:54;
uint64_t pre_align:1;
uint64_t reserved_7_8:2;
uint64_t pre_free:1;
uint64_t ctl_smac:1;
uint64_t ctl_mcst:1;
uint64_t ctl_bck:1;
uint64_t ctl_drp:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} cn56xxp1;
struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
};
union cvmx_gmxx_rxx_frm_max {
uint64_t u64;
struct cvmx_gmxx_rxx_frm_max_s {
uint64_t reserved_16_63:48;
uint64_t len:16;
} s;
struct cvmx_gmxx_rxx_frm_max_s cn30xx;
struct cvmx_gmxx_rxx_frm_max_s cn31xx;
struct cvmx_gmxx_rxx_frm_max_s cn38xx;
struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
struct cvmx_gmxx_rxx_frm_max_s cn58xx;
struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
};
union cvmx_gmxx_rxx_frm_min {
uint64_t u64;
struct cvmx_gmxx_rxx_frm_min_s {
uint64_t reserved_16_63:48;
uint64_t len:16;
} s;
struct cvmx_gmxx_rxx_frm_min_s cn30xx;
struct cvmx_gmxx_rxx_frm_min_s cn31xx;
struct cvmx_gmxx_rxx_frm_min_s cn38xx;
struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
struct cvmx_gmxx_rxx_frm_min_s cn58xx;
struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
};
union cvmx_gmxx_rxx_ifg {
uint64_t u64;
struct cvmx_gmxx_rxx_ifg_s {
uint64_t reserved_4_63:60;
uint64_t ifg:4;
} s;
struct cvmx_gmxx_rxx_ifg_s cn30xx;
struct cvmx_gmxx_rxx_ifg_s cn31xx;
struct cvmx_gmxx_rxx_ifg_s cn38xx;
struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
struct cvmx_gmxx_rxx_ifg_s cn50xx;
struct cvmx_gmxx_rxx_ifg_s cn52xx;
struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
struct cvmx_gmxx_rxx_ifg_s cn56xx;
struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
struct cvmx_gmxx_rxx_ifg_s cn58xx;
struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
};
union cvmx_gmxx_rxx_int_en {
uint64_t u64;
struct cvmx_gmxx_rxx_int_en_s {
uint64_t reserved_29_63:35;
uint64_t hg2cc:1;
uint64_t hg2fld:1;
uint64_t undat:1;
uint64_t uneop:1;
uint64_t unsop:1;
uint64_t bad_term:1;
uint64_t bad_seq:1;
uint64_t rem_fault:1;
uint64_t loc_fault:1;
uint64_t pause_drp:1;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} s;
struct cvmx_gmxx_rxx_int_en_cn30xx {
uint64_t reserved_19_63:45;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} cn30xx;
struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
struct cvmx_gmxx_rxx_int_en_cn50xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t reserved_6_6:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t reserved_2_2:1;
uint64_t carext:1;
uint64_t reserved_0_0:1;
} cn50xx;
struct cvmx_gmxx_rxx_int_en_cn52xx {
uint64_t reserved_29_63:35;
uint64_t hg2cc:1;
uint64_t hg2fld:1;
uint64_t undat:1;
uint64_t uneop:1;
uint64_t unsop:1;
uint64_t bad_term:1;
uint64_t bad_seq:1;
uint64_t rem_fault:1;
uint64_t loc_fault:1;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t reserved_9_9:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t reserved_5_6:2;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t reserved_2_2:1;
uint64_t carext:1;
uint64_t reserved_0_0:1;
} cn52xx;
struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
uint64_t reserved_27_63:37;
uint64_t undat:1;
uint64_t uneop:1;
uint64_t unsop:1;
uint64_t bad_term:1;
uint64_t bad_seq:1;
uint64_t rem_fault:1;
uint64_t loc_fault:1;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t reserved_9_9:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t reserved_5_6:2;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t reserved_2_2:1;
uint64_t carext:1;
uint64_t reserved_0_0:1;
} cn56xxp1;
struct cvmx_gmxx_rxx_int_en_cn58xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} cn58xx;
struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
};
union cvmx_gmxx_rxx_int_reg {
uint64_t u64;
struct cvmx_gmxx_rxx_int_reg_s {
uint64_t reserved_29_63:35;
uint64_t hg2cc:1;
uint64_t hg2fld:1;
uint64_t undat:1;
uint64_t uneop:1;
uint64_t unsop:1;
uint64_t bad_term:1;
uint64_t bad_seq:1;
uint64_t rem_fault:1;
uint64_t loc_fault:1;
uint64_t pause_drp:1;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} s;
struct cvmx_gmxx_rxx_int_reg_cn30xx {
uint64_t reserved_19_63:45;
uint64_t phy_dupx:1;
uint64_t phy_spd:1;
uint64_t phy_link:1;
uint64_t ifgerr:1;
uint64_t coldet:1;
uint64_t falerr:1;
uint64_t rsverr:1;
uint64_t pcterr:1;
uint64_t ovrerr:1;
uint64_t niberr:1;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t lenerr:1;
uint64_t alnerr:1;
uint64_t fcserr:1;
uint64_t jabber:1;
uint64_t maxerr:1;
uint64_t carext:1;
uint64_t minerr:1;
} cn30xx;
struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
struct cvmx_gmxx_rxx_int_reg_cn50xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;