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zifeihan
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RealFYang
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8334078: RISC-V: TestIntVect.java fails after JDK-8332153 when running without RVV
Reviewed-by: fyang, mli
1 parent 0d1080d commit ef7923e

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14 files changed

+58
-204
lines changed

14 files changed

+58
-204
lines changed

‎src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,10 @@ void VM_Version::setup_cpu_available_features() {
131131
if (_feature_list[i]->feature_string()) {
132132
const char* tmp = _feature_list[i]->pretty();
133133
if (strlen(tmp) == 1) {
134-
strcat(buf, " ");
134+
// Feature string is expected to be in multi-character form
135+
// like rvc, rvv, etc so that it will be easier to specify
136+
// target feature string in tests.
137+
strcat(buf, " rv");
135138
strcat(buf, tmp);
136139
} else {
137140
// Feature string is expected to be lower case.

‎test/hotspot/jtreg/compiler/c2/cr7200264/TestIntVect.java

Lines changed: 19 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -480,10 +480,7 @@ void test_suba(int[] a0, int[] a1, int[] a2) {
480480

481481
@Test
482482
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
483-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
484-
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
485-
applyIfPlatform = {"riscv64", "true"},
486-
applyIfCPUFeature = {"v", "true"})
483+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
487484
void test_mulc(int[] a0, int[] a1) {
488485
for (int i = 0; i < a0.length; i+=1) {
489486
a0[i] = (int)(a1[i]*VALUE);
@@ -492,10 +489,7 @@ void test_mulc(int[] a0, int[] a1) {
492489

493490
@Test
494491
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
495-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
496-
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
497-
applyIfPlatform = {"riscv64", "true"},
498-
applyIfCPUFeature = {"v", "true"})
492+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
499493
void test_mulc_n(int[] a0, int[] a1) {
500494
for (int i = 0; i < a0.length; i+=1) {
501495
a0[i] = (int)(a1[i]*(-VALUE));
@@ -527,15 +521,7 @@ void test_mula(int[] a0, int[] a1, int[] a2) {
527521
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
528522
IRNode.SUB_VI,
529523
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
530-
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
531-
@IR(counts = { IRNode.ADD_VI,
532-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
533-
IRNode.RSHIFT_VI,
534-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
535-
IRNode.SUB_VI,
536-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
537-
applyIfPlatform = {"riscv64", "true"},
538-
applyIfCPUFeature = {"v", "true"})
524+
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true", "rvv", "true"})
539525
// Not vectorized: On aarch64, vectorization for this example results in
540526
// MulVL nodes, which asimd does not support.
541527
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
@@ -555,15 +541,7 @@ void test_divc(int[] a0, int[] a1) {
555541
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
556542
IRNode.SUB_VI,
557543
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
558-
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
559-
@IR(counts = { IRNode.ADD_VI,
560-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
561-
IRNode.RSHIFT_VI,
562-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
563-
IRNode.SUB_VI,
564-
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
565-
applyIfPlatform = {"riscv64", "true"},
566-
applyIfCPUFeature = {"v", "true"})
544+
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true", "rvv", "true"})
567545
// Not vectorized: On aarch64, vectorization for this example results in
568546
// MulVL nodes, which asimd does not support.
569547
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
@@ -683,10 +661,7 @@ void test_xora(int[] a0, int[] a1, int[] a2) {
683661

684662
@Test
685663
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
686-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
687-
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
688-
applyIfPlatform = {"riscv64", "true"},
689-
applyIfCPUFeature = {"v", "true"})
664+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
690665
void test_sllc(int[] a0, int[] a1) {
691666
for (int i = 0; i < a0.length; i+=1) {
692667
a0[i] = (int)(a1[i]<<VALUE);
@@ -695,10 +670,7 @@ void test_sllc(int[] a0, int[] a1) {
695670

696671
@Test
697672
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
698-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
699-
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
700-
applyIfPlatform = {"riscv64", "true"},
701-
applyIfCPUFeature = {"v", "true"})
673+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
702674
void test_sllc_n(int[] a0, int[] a1) {
703675
for (int i = 0; i < a0.length; i+=1) {
704676
a0[i] = (int)(a1[i]<<(-VALUE));
@@ -710,12 +682,7 @@ void test_sllc_n(int[] a0, int[] a1) {
710682
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
711683
IRNode.LOAD_VECTOR_I, "> 0",
712684
IRNode.STORE_VECTOR, "> 0" },
713-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
714-
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
715-
IRNode.LOAD_VECTOR_I, "> 0",
716-
IRNode.STORE_VECTOR, "> 0" },
717-
applyIfPlatform = {"riscv64", "true"},
718-
applyIfCPUFeature = {"v", "true"})
685+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
719686
void test_sllc_o(int[] a0, int[] a1) {
720687
for (int i = 0; i < a0.length; i+=1) {
721688
a0[i] = (int)(a1[i]<<SHIFT);
@@ -727,12 +694,7 @@ void test_sllc_o(int[] a0, int[] a1) {
727694
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
728695
IRNode.LOAD_VECTOR_I, "> 0",
729696
IRNode.STORE_VECTOR, "> 0" },
730-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
731-
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
732-
IRNode.LOAD_VECTOR_I, "> 0",
733-
IRNode.STORE_VECTOR, "> 0" },
734-
applyIfPlatform = {"riscv64", "true"},
735-
applyIfCPUFeature = {"v", "true"})
697+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
736698
void test_sllc_on(int[] a0, int[] a1) {
737699
for (int i = 0; i < a0.length; i+=1) {
738700
a0[i] = (int)(a1[i]<<(-SHIFT));
@@ -741,10 +703,7 @@ void test_sllc_on(int[] a0, int[] a1) {
741703

742704
@Test
743705
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
744-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
745-
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
746-
applyIfPlatform = {"riscv64", "true"},
747-
applyIfCPUFeature = {"v", "true"})
706+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
748707
void test_sllv(int[] a0, int[] a1, int b) {
749708
for (int i = 0; i < a0.length; i+=1) {
750709
a0[i] = (int)(a1[i]<<b);
@@ -753,10 +712,7 @@ void test_sllv(int[] a0, int[] a1, int b) {
753712

754713
@Test
755714
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
756-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
757-
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
758-
applyIfPlatform = {"riscv64", "true"},
759-
applyIfCPUFeature = {"v", "true"})
715+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
760716
void test_srlc(int[] a0, int[] a1) {
761717
for (int i = 0; i < a0.length; i+=1) {
762718
a0[i] = (int)(a1[i]>>>VALUE);
@@ -765,10 +721,7 @@ void test_srlc(int[] a0, int[] a1) {
765721

766722
@Test
767723
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
768-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
769-
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
770-
applyIfPlatform = {"riscv64", "true"},
771-
applyIfCPUFeature = {"v", "true"})
724+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
772725
void test_srlc_n(int[] a0, int[] a1) {
773726
for (int i = 0; i < a0.length; i+=1) {
774727
a0[i] = (int)(a1[i]>>>(-VALUE));
@@ -780,12 +733,7 @@ void test_srlc_n(int[] a0, int[] a1) {
780733
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
781734
IRNode.LOAD_VECTOR_I, "> 0",
782735
IRNode.STORE_VECTOR, "> 0" },
783-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
784-
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
785-
IRNode.LOAD_VECTOR_I, "> 0",
786-
IRNode.STORE_VECTOR, "> 0" },
787-
applyIfPlatform = {"riscv64", "true"},
788-
applyIfCPUFeature = {"v", "true"})
736+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
789737
void test_srlc_o(int[] a0, int[] a1) {
790738
for (int i = 0; i < a0.length; i+=1) {
791739
a0[i] = (int)(a1[i]>>>SHIFT);
@@ -797,12 +745,7 @@ void test_srlc_o(int[] a0, int[] a1) {
797745
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
798746
IRNode.LOAD_VECTOR_I, "> 0",
799747
IRNode.STORE_VECTOR, "> 0" },
800-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
801-
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
802-
IRNode.LOAD_VECTOR_I, "> 0",
803-
IRNode.STORE_VECTOR, "> 0" },
804-
applyIfPlatform = {"riscv64", "true"},
805-
applyIfCPUFeature = {"v", "true"})
748+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
806749
void test_srlc_on(int[] a0, int[] a1) {
807750
for (int i = 0; i < a0.length; i+=1) {
808751
a0[i] = (int)(a1[i]>>>(-SHIFT));
@@ -811,10 +754,7 @@ void test_srlc_on(int[] a0, int[] a1) {
811754

812755
@Test
813756
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
814-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
815-
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
816-
applyIfPlatform = {"riscv64", "true"},
817-
applyIfCPUFeature = {"v", "true"})
757+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
818758
void test_srlv(int[] a0, int[] a1, int b) {
819759
for (int i = 0; i < a0.length; i+=1) {
820760
a0[i] = (int)(a1[i]>>>b);
@@ -823,10 +763,7 @@ void test_srlv(int[] a0, int[] a1, int b) {
823763

824764
@Test
825765
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
826-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
827-
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
828-
applyIfPlatform = {"riscv64", "true"},
829-
applyIfCPUFeature = {"v", "true"})
766+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
830767
void test_srac(int[] a0, int[] a1) {
831768
for (int i = 0; i < a0.length; i+=1) {
832769
a0[i] = (int)(a1[i]>>VALUE);
@@ -835,10 +772,7 @@ void test_srac(int[] a0, int[] a1) {
835772

836773
@Test
837774
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
838-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
839-
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
840-
applyIfPlatform = {"riscv64", "true"},
841-
applyIfCPUFeature = {"v", "true"})
775+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
842776
void test_srac_n(int[] a0, int[] a1) {
843777
for (int i = 0; i < a0.length; i+=1) {
844778
a0[i] = (int)(a1[i]>>(-VALUE));
@@ -850,12 +784,7 @@ void test_srac_n(int[] a0, int[] a1) {
850784
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
851785
IRNode.LOAD_VECTOR_I, "> 0",
852786
IRNode.STORE_VECTOR, "> 0" },
853-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
854-
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
855-
IRNode.LOAD_VECTOR_I, "> 0",
856-
IRNode.STORE_VECTOR, "> 0" },
857-
applyIfPlatform = {"riscv64", "true"},
858-
applyIfCPUFeature = {"v", "true"})
787+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
859788
void test_srac_o(int[] a0, int[] a1) {
860789
for (int i = 0; i < a0.length; i+=1) {
861790
a0[i] = (int)(a1[i]>>SHIFT);
@@ -867,12 +796,7 @@ void test_srac_o(int[] a0, int[] a1) {
867796
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
868797
IRNode.LOAD_VECTOR_I, "> 0",
869798
IRNode.STORE_VECTOR, "> 0" },
870-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
871-
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
872-
IRNode.LOAD_VECTOR_I, "> 0",
873-
IRNode.STORE_VECTOR, "> 0" },
874-
applyIfPlatform = {"riscv64", "true"},
875-
applyIfCPUFeature = {"v", "true"})
799+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
876800
void test_srac_on(int[] a0, int[] a1) {
877801
for (int i = 0; i < a0.length; i+=1) {
878802
a0[i] = (int)(a1[i]>>(-SHIFT));
@@ -881,10 +805,7 @@ void test_srac_on(int[] a0, int[] a1) {
881805

882806
@Test
883807
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
884-
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
885-
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
886-
applyIfPlatform = {"riscv64", "true"},
887-
applyIfCPUFeature = {"v", "true"})
808+
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
888809
void test_srav(int[] a0, int[] a1, int b) {
889810
for (int i = 0; i < a0.length; i+=1) {
890811
a0[i] = (int)(a1[i]>>b);

‎test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535
* @key randomness
3636
* @summary Auto-vectorization enhancement for unsigned shift right on signed subword types
3737
* @requires ((os.arch=="amd64" | os.arch=="x86_64") & (vm.opt.UseSSE == "null" | vm.opt.UseSSE > 3)) | os.arch=="aarch64" |
38-
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
38+
* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
3939
* @library /test/lib /
4040
* @run driver compiler.c2.irTests.TestVectorizeURShiftSubword
4141
*/

‎test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
* (vm.cpu.features ~= ".*bmi2.*" & vm.cpu.features ~= ".*bmi1.*" &
3232
* vm.cpu.features ~= ".*sse2.*")) |
3333
* (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*") |
34-
* (os.arch=="riscv64" & vm.cpu.features ~= ".*v,.*"))
34+
* (os.arch=="riscv64" & vm.cpu.features ~= ".*rvv.*"))
3535
* @library /test/lib /
3636
* @run driver compiler.intrinsics.TestBitShuffleOpers
3737
*/

‎test/hotspot/jtreg/compiler/intrinsics/chacha/TestChaCha20.java

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@
3838
* @library /test/lib
3939
* @requires (vm.cpu.features ~= ".*avx512.*" | vm.cpu.features ~= ".*avx2.*" | vm.cpu.features ~= ".*avx.*") |
4040
* (os.arch=="aarch64" & vm.cpu.features ~= ".*simd.*") |
41-
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
41+
* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
4242
* @build compiler.intrinsics.chacha.ExerciseChaCha20
4343
* jdk.test.whitebox.WhiteBox
4444
* @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox
@@ -60,13 +60,9 @@ private static List<String> mix(List<String> o, String... mix) {
6060
return n;
6161
}
6262

63-
private static boolean containsFuzzy(List<String> list, String sub, Boolean matchExactly) {
63+
private static boolean containsFuzzy(List<String> list, String sub) {
6464
for (String s : list) {
65-
if (matchExactly) {
66-
if (s.equals(sub)) return true;
67-
} else {
68-
if (s.contains(sub)) return true;
69-
}
65+
if (s.contains(sub)) return true;
7066
}
7167
return false;
7268
}
@@ -86,27 +82,27 @@ public static void main(String... args) throws Exception {
8682
}
8783

8884
// Otherwise, select the tests that make sense on current platform.
89-
if (containsFuzzy(cpuFeatures, "avx512", false)) {
85+
if (containsFuzzy(cpuFeatures, "avx512")) {
9086
System.out.println("Setting up AVX512 worker");
9187
configs.add(List.of("-XX:UseAVX=3"));
9288
}
93-
if (containsFuzzy(cpuFeatures, "avx2", false)) {
89+
if (containsFuzzy(cpuFeatures, "avx2")) {
9490
System.out.println("Setting up AVX2 worker");
9591
configs.add(List.of("-XX:UseAVX=2"));
9692
}
97-
if (containsFuzzy(cpuFeatures, "avx", false)) {
93+
if (containsFuzzy(cpuFeatures, "avx")) {
9894
System.out.println("Setting up AVX worker");
9995
configs.add(List.of("-XX:UseAVX=1"));
10096
}
10197
} else if (Platform.isAArch64()) {
10298
// AArch64 intrinsics require the advanced simd instructions
103-
if (containsFuzzy(cpuFeatures, "simd", false)) {
99+
if (containsFuzzy(cpuFeatures, "simd")) {
104100
System.out.println("Setting up ASIMD worker");
105101
configs.add(new ArrayList());
106102
}
107103
} else if (Platform.isRISCV64()) {
108104
// Riscv64 intrinsics require the vector instructions
109-
if (containsFuzzy(cpuFeatures, "v", true)) {
105+
if (containsFuzzy(cpuFeatures, "rvv")) {
110106
System.out.println("Setting up vector worker");
111107
configs.add(List.of("-XX:+UseRVV"));
112108
}

‎test/hotspot/jtreg/compiler/lib/ir_framework/test/IREncodingPrinter.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ public class IREncodingPrinter {
108108
"asimd",
109109
"sve",
110110
// Riscv64
111-
"v",
111+
"rvv",
112112
"zvbb"
113113
));
114114

‎test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastRVV.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
* @modules jdk.incubator.vector
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* @modules java.base/jdk.internal.misc
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* @summary Test that vector cast intrinsics work as intended on riscv (rvv).
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* @requires os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*"
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* @requires os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*"
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* @library /test/lib /
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* @run main/timeout=300 compiler.vectorapi.reshape.TestVectorCastRVV
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*/

‎test/hotspot/jtreg/compiler/vectorization/TestSignumVector.java

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@@ -28,7 +28,7 @@
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* and riscv64 (vector)
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx.*") | os.arch == "aarch64" |
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestSignumVector
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*/

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