Skip to content

Commit c899c23

Browse files
barni2000barni2000
committed
arm64: dts: qcom: msm8917: Add camss and cci
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
1 parent 32e3751 commit c899c23

File tree

1 file changed

+158
-0
lines changed

1 file changed

+158
-0
lines changed

‎arch/arm64/boot/dts/qcom/msm8917.dtsi‎

Lines changed: 158 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -846,6 +846,20 @@
846846
bias-pull-down;
847847
};
848848

849+
cci0_default: cci0-default-state {
850+
pins = "gpio29", "gpio30";
851+
function = "cci_i2c";
852+
drive-strength = <2>;
853+
bias-disable;
854+
};
855+
856+
cci1_default: cci1-default-state {
857+
pins = "gpio31", "gpio32";
858+
function = "cci_i2c";
859+
drive-strength = <2>;
860+
bias-disable;
861+
};
862+
849863
sdc1_default: sdc1-default-state {
850864
clk-pins {
851865
pins = "sdc1_clk";
@@ -1145,6 +1159,150 @@
11451159
};
11461160
};
11471161

1162+
camss: camss@1b00000 {
1163+
compatible = "qcom,msm8917-camss";
1164+
reg = <0x01b34000 0x1000>,
1165+
<0x01b00030 0x4>,
1166+
<0x01b35000 0x1000>,
1167+
<0x01b00038 0x4>,
1168+
<0x01b30000 0x100>,
1169+
<0x01b30400 0x100>,
1170+
<0x01b30800 0x100>,
1171+
<0x01b31000 0x500>,
1172+
<0x01b00020 0x10>,
1173+
<0x01b10000 0x1000>,
1174+
<0x01b14000 0x1000>;
1175+
reg-names = "csiphy0",
1176+
"csiphy0_clk_mux",
1177+
"csiphy1",
1178+
"csiphy1_clk_mux",
1179+
"csid0",
1180+
"csid1",
1181+
"csid2",
1182+
"ispif",
1183+
"csi_clk_mux",
1184+
"vfe0",
1185+
"vfe1";
1186+
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1187+
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1188+
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1189+
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1190+
<GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
1191+
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1192+
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
1193+
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
1194+
interrupt-names = "csiphy0",
1195+
"csiphy1",
1196+
"csid0",
1197+
"csid1",
1198+
"csid2",
1199+
"ispif",
1200+
"vfe0",
1201+
"vfe1";
1202+
power-domains = <&gcc VFE0_GDSC>, <&gcc VFE1_GDSC>;
1203+
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1204+
<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1205+
<&gcc GCC_CAMSS_MICRO_AHB_CLK>,
1206+
<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1207+
<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1208+
<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1209+
<&gcc GCC_CAMSS_CSI0_CLK>,
1210+
<&gcc GCC_CAMSS_CSI0PHY_CLK>,
1211+
<&gcc GCC_CAMSS_CSI0PIX_CLK>,
1212+
<&gcc GCC_CAMSS_CSI0RDI_CLK>,
1213+
<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1214+
<&gcc GCC_CAMSS_CSI1_CLK>,
1215+
<&gcc GCC_CAMSS_CSI1PHY_CLK>,
1216+
<&gcc GCC_CAMSS_CSI1PIX_CLK>,
1217+
<&gcc GCC_CAMSS_CSI1RDI_CLK>,
1218+
<&gcc GCC_CAMSS_CSI2_AHB_CLK>,
1219+
<&gcc GCC_CAMSS_CSI2_CLK>,
1220+
<&gcc GCC_CAMSS_CSI2PHY_CLK>,
1221+
<&gcc GCC_CAMSS_CSI2PIX_CLK>,
1222+
<&gcc GCC_CAMSS_CSI2RDI_CLK>,
1223+
<&gcc GCC_CAMSS_AHB_CLK>,
1224+
<&gcc GCC_CAMSS_VFE0_CLK>,
1225+
<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1226+
<&gcc GCC_CAMSS_VFE0_AHB_CLK>,
1227+
<&gcc GCC_CAMSS_VFE0_AXI_CLK>,
1228+
<&gcc GCC_CAMSS_VFE1_CLK>,
1229+
<&gcc GCC_CAMSS_CSI_VFE1_CLK>,
1230+
<&gcc GCC_CAMSS_VFE1_AHB_CLK>,
1231+
<&gcc GCC_CAMSS_VFE1_AXI_CLK>;
1232+
clock-names = "top_ahb",
1233+
"ispif_ahb",
1234+
"micro_ahb",
1235+
"csiphy0_timer",
1236+
"csiphy1_timer",
1237+
"csi0_ahb",
1238+
"csi0",
1239+
"csi0_phy",
1240+
"csi0_pix",
1241+
"csi0_rdi",
1242+
"csi1_ahb",
1243+
"csi1",
1244+
"csi1_phy",
1245+
"csi1_pix",
1246+
"csi1_rdi",
1247+
"csi2_ahb",
1248+
"csi2",
1249+
"csi2_phy",
1250+
"csi2_pix",
1251+
"csi2_rdi",
1252+
"ahb",
1253+
"vfe0",
1254+
"csi_vfe0",
1255+
"vfe_ahb",
1256+
"vfe_axi",
1257+
"vfe1",
1258+
"csi_vfe1",
1259+
"vfe1_ahb",
1260+
"vfe1_axi";
1261+
iommus = <&apps_iommu 0x14>;
1262+
status = "disabled";
1263+
ports {
1264+
#address-cells = <1>;
1265+
#size-cells = <0>;
1266+
};
1267+
};
1268+
1269+
cci: cci@1b0c000 {
1270+
compatible = "qcom,msm8974-cci";
1271+
#address-cells = <1>;
1272+
#size-cells = <0>;
1273+
reg = <0x01b0c000 0x1000>;
1274+
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1275+
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1276+
<&gcc GCC_CAMSS_CCI_AHB_CLK>,
1277+
<&gcc GCC_CAMSS_CCI_CLK>,
1278+
<&gcc GCC_CAMSS_AHB_CLK>;
1279+
clock-names = "camss_top_ahb",
1280+
"cci_ahb",
1281+
"cci",
1282+
"camss_ahb";
1283+
assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1284+
<&gcc GCC_CAMSS_CCI_CLK>;
1285+
assigned-clock-rates = <80000000>, <19200000>;
1286+
pinctrl-0 = <&cci0_default>,
1287+
<&cci1_default>;
1288+
pinctrl-names = "default";
1289+
status = "disabled";
1290+
1291+
cci_i2c0: i2c-bus@0 {
1292+
reg = <0>;
1293+
clock-frequency = <400000>;
1294+
#address-cells = <1>;
1295+
#size-cells = <0>;
1296+
};
1297+
1298+
cci_i2c1: i2c-bus@1 {
1299+
reg = <1>;
1300+
clock-frequency = <400000>;
1301+
#address-cells = <1>;
1302+
#size-cells = <0>;
1303+
};
1304+
};
1305+
11481306
apps_iommu: iommu@1e20000 {
11491307
compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
11501308
ranges = <0 0x01e20000 0x20000>;

0 commit comments

Comments
 (0)