updated Jupyter notebooks for C2S based on DX testing (#1511)

* 2023.1 Release PR (#1499)

* FPGA: Update dsp_control README (#1269)

* FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281)

This reverts commit 86c4aa8 and
reenables the db9 code sample in 2023.1

* FPGA: Batch PR - sim support - selectors update - readme rework (#1280)

This PR:
- adds simulation support to almost all of the remaining FPGA code samples
- reworks all the FPGA code sample READMEs to update the software requirements
- reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information
- changes all FPGA samples selectors to comply with the 2023.1 new selectors
- edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow

* FPGA: Remove all references to Windows in README (#1273)

* Update samples to SYCL 2023 specifications (#1286)

* FPGA: fix io_streaming assets location (#1289)

* FPGA: remove instructions to build merge_sort on Windows (#1290)

* FPGA: Update printf readme and fixed some typos (#1288)

* Added simulation instructions to README for 2023.1

* Corrected for running simulation since windows need multiple commmands to run

* FPGA: Top level readme update (#1285)

* removed dpc_common.hpp dependency (#1282)

Co-authored-by: Rakshith Krishnappa <krisrak@gmail.com>

* FPGA: add simulation support to the private_copies samples (#1296)

* Reverted PR#1265 and PR#1266 (#1298)

* Update repo Readme.md (#1308)

Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits.

* FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307)

# Existing Sample Changes
## Description

All of the FPGA samples are moved to the IP Authoring flow.
The default target for all samples is now Agilex.
For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name.

* matrix_mul_mkl: use single precision for compatibility with all devices (#1310)

* updated latest GPU devices in Occupancy Calculator (#1309)

* FPGA: add a warning when compiling the CRR design in the simulation flow (#1318)

The simulation runtime of the CRR design is very long.
This PR adds a message that the users can see when they compile for simulation warning them about this long runtime.

* FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325)

* FPGA: Update QRD s10 default seed  (#1324)

This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1

* FPGA: Add `device_global` sample (#1291)

* update the sample with mcg59 as a default engine (#1331)

* FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321)

* FPGA: create new invocation interfaces sample (#1303)

* FPGA: New Code Sample `minimum_latency` (#1302)

* FPGA: Fix typo (#1342)

* FPGA: Add `fpga_template` sample (#1262)

* FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340)

* FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351)

* Compilator update (#1349)

* Change compiler in makefiles

* Change compiler in cmake files

* Updated TBB source files to use default_selector_v (#1360)

Co-authored-by: gta <gta@DUT043-DG1RVC.fm.intel.com>

* update Makefile to compile with icpx (#1363)

Co-authored-by: rupakroyintel <rupakroy@rupakroy-mobl1.amr.corp.intel.com>

* FPGA: Typo for s10 support in `device_globals` (#1359)

* FPGA: Add platform designer tutorial (#1348)

* FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367)

* FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369)

* FPGA: Update onchip memory cache readme (#1358)

Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer.

* FPGA: Remove Windows simulator command for memory_attributes (#1374)

* Fix compilation error (#1371)

* FPGA: replace Agilex™ with Agilex® (#1372)

* FPGA: Fix decompress emulation flow not using the correct files(#1373)

* FPGA: Fix race condition in the buffered_host_streaming sample (#1375)

* Update FPGA optimize inner loop readme (#1380)

Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch).

* FPGA: incorrect path update (#1382)

* Relax correctness test for Ch04 matrix multiply (#1378)

Co-authored-by: gta <gta@DUT046-DG1RVC.fm.intel.com>

* FPGA: Reduce the design size of the memory_attributes design in simulation (#1383)

* FPGA: Fix inconsistent device flags in 4 samples (#1384)

Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex.
This change makes all the samples consistent with the second option.

* FPGA Shannonization Sample readme update (#1386)

Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows.  Rewrote and restructured some sections for clarity.

* FPGA: Update Host-Device Streaming using USM readme (#1391)

Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity.

* Update FPGA pipe array readme (#1385)

Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity.

* Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389)

This reverts commit 149dbb6.

* FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392)

* FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390)

* FPGA: update gzip seed (#1381)

* FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388)

* FPGA: make the decompress design use shared memory allocations in IPA flow (#1396)

* FPGA: check USM support in fpga_template (#1397)

* FPGA: Add the missing simulator selector to the CRR design. (#1398)

* ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387)

Affected samples: array-transform, jacobi.

Remove the custom selector.hpp files.
Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments.
Update sample.json files.

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>

* FPGA: improve the minimum_latency cmake device detection (#1399)

* Triangular Loop readme update (#1393)

Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity.

* Zero Copy Data Transfer readme update (#1394)

Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity.

* FPGA: Improve the `fpga_compile` tutorial (#1347)

* FPGA: Add platform designer tutorial: Readme clarification (#1400)

* FPGA compile update - fix compile problem with USM device check (#1402)

* FPGA: compile - remove +/- in path (#1404)

* Document that simulator for mvdr_beamforming can take a long time (#1405)

* FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements  (#1407)

* changed the default sub-group size to 32 (#1406)

Co-authored-by: Praveen Kundurthy <u137620@s001-n067.aidevcloud>

* FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414)

* FPGA: Reduce test size for simple_host_streaming simulator target (#1415)

* ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416)

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>

* FPGA: fix anr cmake file (#1420)

The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10".
This PR addresses this gap.

* Added release.json for samples CI (#1418)

* FPGA: add include path in compile command (#1423)

* FPGA: fix the HW compile seed for the ivdep sample (#1427)

This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards.
This PR fixes the seed so that we know it compiles cleanly on PAC boards.

* updated GPU Occupancy Calculator with PVC GPU (#1425)

* updated GPU Occupancy Calculator with PVC GPU

* updated GPU names in Occupancy Calculator

* Tools/ApplicationDebugger: update jacobi sample. (#1421)

* Restructure the source code:
  - the common parts are moved to jacobi.cpp;
  - the computation parts have two flavors:
    - bugged.cpp contains computation with bugs;
    - fixed.cpp contains fixed computation;
* Simplify reductions;
* Update README.

Signed-off-by: Saiapova, Natalia <natalia.saiapova@intel.com>

* Update GPU-Opt-Guide examples to 2023.03.14 (#1432)

* FPGA: Provide smaller input file size option for gzip (#1431)

Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE.

* updated oneapi_essentials module2 notebook and code sample (#1430)

* updated oneapi_essentials module2 notebook and code sample

* updated Makefile

* Add all files (#1437)

* Add all files (#1436)

* Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442)

* change compiler for new oneDNN release (#1435)

* adding Jupyter Notebooks for cuda to sycl migration learning path (#1439)

* FPGA: Reduce array size for simulation in the loop_unroll sample (#1443)

The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours).

This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows.

* FPGA: fix incorrect paths in Windows CI steps (#1445)

Some FPGA samples had incorrect path in their CI steps in the sample.json file.

* Pred modeling updates (#1446)

* Predictive Modeling Updates

* fix complete

---------

Co-authored-by: u51369 <u51369@s001-n066.aidevcloud>

* Rendering: path tracing with embree cpu updates (#1362)

* First pass at CPU Embree 4 changes, need to change header

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Added embree 4 headers and CMake flexibility

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* warning fixes for boolean

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* README, coherent ray updates for embree 4

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* style formatting

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* README fixes and removal of stub mis code

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Updating sample.json for dirs and ONSAM-1563

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* sample.json for MacOS per ONSAM ticket

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* pathtracer lib ref update for macos validation consistency

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

---------

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Rendering: IntroToRayTracingWithEmbree embree4 update (#1354)

* rkRayTracer Embree4 GPU: Updated sample.json for validation

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Embree 4 compatibility updates for Ray Tracer

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Ray Tracer Embree4 sample.json update

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Firmer reference to rkcommon (macOS validation helper)

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Cleaning up helper script/CMake syntax

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

---------

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Rendering Embree4 GSG Updates (#1353)

* stage embree gsg for cpu

Signed-off-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>

* Add gpu to Rendering 02_embree... TODO: test/json val/readme

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Adding license file in all folders for 02_embree

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Update Embree gsg README.md

* Update embree4 readme.md

* embree minimal samples updated for embree 4... prewindows testing

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* Checked on Windows, fixed readme... ready for PR review

Signed-off-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>

* Embree4 gsg JSON automation updates

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* README updates... thx to @jkinsky feedback

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

---------

Signed-off-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>
Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>
Co-authored-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>

* Fix double to float (#1447)

* FPGA: Platform designer readme touchup (#1449)

* Added SECURITY.md (#1450)

* Removed Windows validation step from ciTests (#1451)

* Rtk development branch fix for validation 20230320 (#1458)

* sample.json update for macos validation workaround

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* samples.json workaround for validation rtk pathtracer

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

---------

Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>

* FPGA: Fix windows CI steps in platform designer (#1459)

* Updated Makefile.win to resolve Windows compilation errors (#1460)

* Updated makefile to remove sycl.lib (#1468)

* Allow Ch18 DPC++ book code samples to compile (#1467)

* Uncommented CMakeLists.txt for Ch18 DPC++ book code samples

* Updated CMakeLists.txt

* Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470)

* Tools/ApplicationDebugger/jacobi: remove Windows from sample.json

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>

* Update sample.json

---------

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>
Co-authored-by: Jimmy Wei <jimmy.t.wei@intel.com>

* FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472)

* FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476)

This is a port of #1474

* FPGA: reduce snappy decompression simulation duration (#1478)

When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475.

* FPGA: Set fp model to "precise" for ac_fixed sample (#1483)

* set fp-model to precise for emu only

* set fp-model to precise for all platforms

---------

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>
Signed-off-by: Saiapova, Natalia <natalia.saiapova@intel.com>
Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>
Signed-off-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>
Co-authored-by: Shuo Niu <shuo.niu@intel.com>
Co-authored-by: Justin Rosner <justin.rosner@intel.com>
Co-authored-by: yuguen-intel <yohann.uguen@intel.com>
Co-authored-by: Peng Tu <peng.tu@intel.com>
Co-authored-by: Hao Xiang Yang <111762426+haoxian2@users.noreply.github.com>
Co-authored-by: Rakshith <rakshith.krishnappa@intel.com>
Co-authored-by: Rakshith Krishnappa <krisrak@gmail.com>
Co-authored-by: Artem Radzikhovskyy <artem.radzikhovskyy@intel.com>
Co-authored-by: jkinsky <106110367+jkinsky@users.noreply.github.com>
Co-authored-by: petercad <peter.caday@intel.com>
Co-authored-by: Andrei Fedorov <andrey.fedorov@intel.com>
Co-authored-by: Brox Chen <brox.chen@intel.com>
Co-authored-by: intel-jisheng1 <shengxiang.ji@intel.com>
Co-authored-by: Paul White <paul.white@intel.com>
Co-authored-by: alisanikiforova <alisa.nikiforova@intel.com>
Co-authored-by: IgorOchocki <36711066+IgorOchocki@users.noreply.github.com>
Co-authored-by: gta <gta@DUT043-DG1RVC.fm.intel.com>
Co-authored-by: Roy-Rupak <rupak.ndc144@gmail.com>
Co-authored-by: rupakroyintel <rupakroy@rupakroy-mobl1.amr.corp.intel.com>
Co-authored-by: intel-liudean <dean.liu@intel.com>
Co-authored-by: gta <gta@DUT046-DG1RVC.fm.intel.com>
Co-authored-by: nsaiapova <natalia.saiapova@intel.com>
Co-authored-by: Kevin Xu <wenkai.xu@mail.utoronto.ca>
Co-authored-by: praveenkk123 <praveen.k.kundurthy@intel.com>
Co-authored-by: Praveen Kundurthy <u137620@s001-n067.aidevcloud>
Co-authored-by: Louie Tsai <louie.tsai@intel.com>
Co-authored-by: IlanTruanovsky <ilan.truanovsky@intel.com>
Co-authored-by: bjodom <bjodom@users.noreply.github.com>
Co-authored-by: u51369 <u51369@s001-n066.aidevcloud>
Co-authored-by: MichaelRCarroll-Intel <101751670+MichaelRCarroll-Intel@users.noreply.github.com>
Co-authored-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>
Co-authored-by: wangdi4 <101905226+wangdi4@users.noreply.github.com>

* Fixed merge issue in dbdata.cpp (#1501)

* Add entry in third-party-programs.txt for use of Google Fonts API (#1503)

- Google fonts are used in the oneAPI Samples Catalog.

Signed-off-by: michael vincerra <michael.vincerra@intel.com>

* updated Jupyter notebooks for C2S based on DX testing

---------

Signed-off-by: Natalia Saiapova <natalia.saiapova@intel.com>
Signed-off-by: Saiapova, Natalia <natalia.saiapova@intel.com>
Signed-off-by: Carroll, Michael R <michael.r.carroll@intel.com>
Signed-off-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>
Signed-off-by: michael vincerra <michael.vincerra@intel.com>
Co-authored-by: Jimmy Wei <jimmy.t.wei@intel.com>
Co-authored-by: Shuo Niu <shuo.niu@intel.com>
Co-authored-by: Justin Rosner <justin.rosner@intel.com>
Co-authored-by: yuguen-intel <yohann.uguen@intel.com>
Co-authored-by: Peng Tu <peng.tu@intel.com>
Co-authored-by: Hao Xiang Yang <111762426+haoxian2@users.noreply.github.com>
Co-authored-by: Rakshith Krishnappa <krisrak@gmail.com>
Co-authored-by: Artem Radzikhovskyy <artem.radzikhovskyy@intel.com>
Co-authored-by: jkinsky <106110367+jkinsky@users.noreply.github.com>
Co-authored-by: petercad <peter.caday@intel.com>
Co-authored-by: Andrei Fedorov <andrey.fedorov@intel.com>
Co-authored-by: Brox Chen <brox.chen@intel.com>
Co-authored-by: intel-jisheng1 <shengxiang.ji@intel.com>
Co-authored-by: Paul White <paul.white@intel.com>
Co-authored-by: alisanikiforova <alisa.nikiforova@intel.com>
Co-authored-by: IgorOchocki <36711066+IgorOchocki@users.noreply.github.com>
Co-authored-by: gta <gta@DUT043-DG1RVC.fm.intel.com>
Co-authored-by: Roy-Rupak <rupak.ndc144@gmail.com>
Co-authored-by: rupakroyintel <rupakroy@rupakroy-mobl1.amr.corp.intel.com>
Co-authored-by: intel-liudean <dean.liu@intel.com>
Co-authored-by: gta <gta@DUT046-DG1RVC.fm.intel.com>
Co-authored-by: nsaiapova <natalia.saiapova@intel.com>
Co-authored-by: Kevin Xu <wenkai.xu@mail.utoronto.ca>
Co-authored-by: praveenkk123 <praveen.k.kundurthy@intel.com>
Co-authored-by: Praveen Kundurthy <u137620@s001-n067.aidevcloud>
Co-authored-by: Louie Tsai <louie.tsai@intel.com>
Co-authored-by: IlanTruanovsky <ilan.truanovsky@intel.com>
Co-authored-by: bjodom <bjodom@users.noreply.github.com>
Co-authored-by: u51369 <u51369@s001-n066.aidevcloud>
Co-authored-by: MichaelRCarroll-Intel <101751670+MichaelRCarroll-Intel@users.noreply.github.com>
Co-authored-by: MichaelRoyceCarroll <michael.carroll@alumni.usc.edu>
Co-authored-by: wangdi4 <101905226+wangdi4@users.noreply.github.com>
Co-authored-by: michael vincerra <michael.vincerra@intel.com>

Author: 34 people

DirectProgramming/C++SYCL/Jupyter/cuda-to-sycl-migration-training/01_SYCL_Migration_Simple_VectorAdd/01_SYCL_Migration_Simple_VectorAdd.ipynb

@@ -144,11 +144,10 @@
     "  - copy link to latest `linux_release.tgz` from assets\n",
     "  - on the CUDA development machine: `mkdir syclomatic; cd syclomatic`\n",
     "  - `wget <link to linux_release.tgz>`\n",
-    "  - `tar -cvf linux_release.tgz`\n",
-    "  -  `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
-    "- Copy the above `vectoradd.cu` CUDA source to this machine\n",
-    "- Compile and run the `vectoradd.cu`\n",
-    "  - nvcc vectoradd.cu\n",
+    "  - `tar -xvf linux_release.tgz`\n",
+    "  - `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - Verify installation: `c2s --version`\n",
+    "- Create a working directory and copy the above `vectoradd.cu` CUDA source to this machine\n",
     "\n",
     "\n",
     "### Migrate CUDA source to SYCL source using SYCLomatic\n",
@@ -168,7 +167,7 @@
     "Next we will use the `c2s --out-root` option to specify a custom output directory like shown below:\n",
     "\n",
     "```\n",
-    "c2s --out-root sycl_code vectoradd.cu\n",
+    "c2s vectoradd.cu --use-custom-helper=api --out-root sycl_code\n",
     "```\n",
     "\n",
     "This command should migrate the CUDA source to SYCL source in a folder named `sycl_code`\n",
@@ -249,7 +248,14 @@
     "        sycl::free(d_C, q_ct1);\n",
     "        return 0;\n",
     "}\n",
-    "```"
+    "```\n",
+    "\n",
+    "The migrated SYCL code can be compiled using the following command in terminal:\n",
+    "```sh\n",
+    "icpx -fsycl -I include vectoradd.dp.cpp\n",
+    "```\n",
+    "\n",
+    "OR you can compile and run by executing the cell below:"
    ]
   },
   {
@@ -323,7 +329,7 @@
    "source": [
     "## Manually Optimize the migrated SYCL source\n",
     "\n",
-    "The SYCLomaticy Tool will migrate the CUDA code to the SYCL code to get functionality, but you may have to manually optimize the resulting SYCL code for optimal performance.\n",
+    "The SYCLomatic Tool will migrate the CUDA code to the SYCL code to get functionality, but you may have to manually optimize the resulting SYCL code for optimal performance.\n",
     "\n",
     "Now that we have successfully migrated the CUDA code to the SYCL code and executed on an Intel CPU/GPU, let’s look at what manual optimizations we can do.\n",
     "\n",
@@ -339,7 +345,7 @@
     "The above code is also creating a SYCL queue with an `in_order` queue property and is doing a default device selection, which is the same as the code below using just SYCL api syntax:\n",
     "\n",
     "```cpp\n",
-    "sycl::queue q_ct1{sycl::default_selector(), sycl::property::queue::in_order()};\n",
+    "sycl::queue q_ct1{sycl::default_selector_v(), sycl::property::queue::in_order()};\n",
     "```\n",
     "\n",
     "Using an `in_order` queue property will not allow kernels with no dependency to overlap execution. Therefore, we will remove the `in_order` queue property and add event-based dependency between kernels.\n",

DirectProgramming/C++SYCL/Jupyter/cuda-to-sycl-migration-training/02_SYCL_Migration_SortingNetworks/02_SYCL_Migration_SortingNetworks.ipynb

@@ -123,8 +123,9 @@
     "  - copy link to latest `linux_release.tgz` from assets\n",
     "  - on the CUDA development machine: `mkdir syclomatic; cd syclomatic`\n",
     "  - `wget <link to linux_release.tgz>`\n",
-    "  - `tar -cvf linux_release.tgz`\n",
-    "  -  `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - `tar -xvf linux_release.tgz`\n",
+    "  - `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - Verify installation: `c2s --version`\n",
     "- pull the CUDA samples repo to this machine\n",
     "  - `git clone https://github.com/NVIDIA/cuda-samples.git`\n",
     "- Compile and run the `sortingNetworks` sample\n",

DirectProgramming/C++SYCL/Jupyter/cuda-to-sycl-migration-training/03_SYCL_Migration_Jacobi_Iterative/03_SYCL_Migration_Jacobi_Iterative.ipynb

@@ -124,8 +124,9 @@
     "  - copy link to latest `linux_release.tgz` from assets\n",
     "  - on the CUDA development machine: `mkdir syclomatic; cd syclomatic`\n",
     "  - `wget <link to linux_release.tgz>`\n",
-    "  - `tar -cvf linux_release.tgz`\n",
-    "  -  `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - `tar -xvf linux_release.tgz`\n",
+    "  - `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - Verify installation: `c2s --version`\n",
     "- pull the CUDA samples repo to this machine\n",
     "  - `git clone https://github.com/NVIDIA/cuda-samples.git`\n",
     "- Compile and run the `jacobiCudaGraphs` sample\n",

DirectProgramming/C++SYCL/Jupyter/cuda-to-sycl-migration-training/04_SYCL_Migration_MatrixMul_CuBlas/04_SYCL_Migration_MatrixMul_CuBlas.ipynb

@@ -109,8 +109,9 @@
     "  - copy link to latest `linux_release.tgz` from assets\n",
     "  - on the CUDA development machine: `mkdir syclomatic; cd syclomatic`\n",
     "  - `wget <link to linux_release.tgz>`\n",
-    "  - `tar -cvf linux_release.tgz`\n",
-    "  -  `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - `tar -xvf linux_release.tgz`\n",
+    "  - `export PATH=\"/home/$USER/syclomatic/bin:$PATH\"`\n",
+    "  - Verify installation: `c2s --version`\n",
     "- pull the CUDA samples repo to this machine\n",
     "  - `git clone https://github.com/NVIDIA/cuda-samples.git`\n",
     "- Compile and run the `matrixMulCUBLAS` sample\n",

DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/dbdata.cpp

@@ -955,4 +955,4 @@ void Database::PrintQ12(std::string& SM1, std::string& SM2,
   // Restore the output format of cout
   std::cout.copyfmt(oldState);
 
-}
+}